SLAC EPICS Meeting 2012 Timing Workshop
Micro-Research Finland OySLAC EPICS Meeting 2012Timing WorkshopJukka PietarinenTuesday, April 24, 2012
Micro-Research Finland OyPCIe-EVR-300–PCI Express–Lattice ECP3 FPGA–I/O on VHDCIconnector–SFP transceiver–two RGB LEDs–91.7 mm x 79.2 mm–14 layer PCB24 April 2012Tuesday, April 24, 2012jukka.pietarinen@mrf.fi
Micro-Research Finland OyInterface Board IFB-300 Schroff 24572-100 ratiopacPRO case– 1U 42.5 mm high, 255.5 mm deep– Holds one 6U PCB Eight Universal I/O slots Four indicator/status LEDs 19” Rack mount brackets available24 April 2012Tuesday, April 24, 2012jukka.pietarinen@mrf.fi
Micro-Research Finland OyInterface Board IFB-300– Front side has a handle on the right hand side– To replace I/O modules one has to take off back side VHDCI connector screwsand loosen front panel fastening screws. PCB will slide out.24 April 2012Tuesday, April 24, 2012jukka.pietarinen@mrf.fi
Micro-Research Finland OyPCIe-EVR / IFB-300 Current Status First production batch shipped to Diamond inNovember 2011 New production batch in progress24 April 2012Tuesday, April 24, 2012jukka.pietarinen@mrf.fi
Micro-Research Finland OyPXIe-EVR-300 An Event Receiver for the PXIe System Timing Slot24 April 2012Tuesday, April 24, 2012jukka.pietarinen@mrf.fi
Micro-Research Finland OyPXIe-EVR-300 Design - Features Eight bit PXI trigger bus 17 Star triggers, one to each individual slot 3 x 17 Differential lines, three to each individual slot–one clock signal DSTARA from EVR to peripheral–one trigger signal DSTARB from EVR to peripheral–one signal DSTARC from peripheral to EVR Capability to provide 10 MHz reference to backplane(backplane generates 100 MHz from 10 MHz) Two front panel TTL inputs Two front panel Universal I/O slot Optionally VHDCI connector for cable to Interface boardIFB-300 with eight Universal I/O slots24 April 2012Tuesday, April 24, 2012jukka.pietarinen@mrf.fi
Micro-Research Finland Oy1x2(2x2) 50/125µm Multi-Mode Broadband Splitter (Mixer)Passive Optical Splitters inTiming Distribution NetworkTest setup and report by Yuri Chernouskoyuri.chernousko@diamond.ac.ukProduct FeatureszLow Insertion LosszHigh DirectivityzTelcordia 1221 CompliancezVery Compact SizeProduct ApplicationsSpecificationszOptical Communication SystemzLANzOptical SensorzAccess NetworkSplitting Ratio:ParameterUnitGradeUCentral WavelengthnmBandwidth50:501x2 or 2x2PAUP1550 or 1310A850nm 20Insertion LossMax.dB3.54.04.53.85.05.5Excess 0.80.50.50.8Return Loss*Min.dBOperating powerMax.40W5Operating Temperature C-40 to 85Storage Temperature CPackage Typemm-50 to 85S6Ø3x54: for bare fiberS8Ø3x70: for 0.9mm loose tubeM110x20x90: for 0.9mm loose tube or 3mm cable* Test at central wavelength only.Splitting Ratio & Insertion Loss Conversion Table for 1550, 1310 20nmUltra-PremiumSplitting 7.811.215Maximum Insertion Loss (dB)PremiumOutput Port23.25.02.46.31.78.21.2120.816Output 13.72.92.31.81.5A gradeOutput 25.67.09.012.816.8Splitting Ratio & Insertion Loss Conversion Table for 850 20nmSplitting Ratio60:4070:3080:2090:1095:5Ultra-PremiumOutput Port2Output Port 13.05.02.46.21.78.11.211.41.014.3Maximum Insertion Loss (dB)PremiumOutput Port1Output Port24.06.03.37.32.39.22.012.51.616.5A gradeOutput Port1Output Port24.76.63.98.03.210.02.713.52.417.5Ordering InformationMBSWavelength4 1550nm7 1310nmA 850nmStructure1 1x22 2x2Splitting Ratio95 95:590 90:1080 80:2070 70:3060 60:4050 50:50GradeU-Ultra-PremiumP PremiumA A gradePackage5 S67 S8D M1Fiber Type2 50/125µmPigtailS 250 mBare fiberM 0.9mmLoose tubeL 3mm CableFiber Length0 0.5m1 0.75m2 1.0mConnector0 None1 FC/PC2 FC/SPC3 FC/APC4 SC/SPC5 SC/APC6 ST7 FC/UPC8 SC/UPC9 MUA LCB SC/PCNote: All specifications are before connectors and are subject to change without notice.Measured under the stable mode condition with LED source.24 April 2012Tuesday, April 24, 2012jukka.pietarinen@mrf.fi
Micro-Research Finland OySchematic of T est SetupY. Chernousko, 30/03/2012CH 2CH 1CH 2CH 1Splitter1000m OM3 6 xCouplersSplitterEVGEVRDirectDelayedTo ScopeSourcePowerPowerMeterStatusOK - /OK!"# %&'%()* ",#%24SampleApril! 2012NumberTuesday, April 24, @mrf.fi5 ,". %.&44". &4%67778%9 :,"%;% 1&-)*",#%% ?@%( 3 -#%AB8%dBm%%
To ScMicro-Research Finland OyPowerMeterStatusOK - /OK!"# %&'%()* 0142309!(&-,."%/&0",%!12344"*%AB8%!5 ,". %.&44". &4%67778%9 :,"%;% 1&-)*",#%% ?@%( 3 -#%%%AB8%dBm%%"# %&!'!-11.71"'( )(!* !!!%!-11.02"'( %,!* !"# -%!'!-11.25"'( -%!* !!!%!-11.74"'( .%!* !"# -#!'!-11.59"'( )-!* !!!%!-10.96"'( %%!* !"# )'!'!-11.79"'( .)!* !!!%!-11.41"'( -,!* !"# %,!'!-11.33"'( ('!* !!!%!-11.39"'( (.!* !"# -&!'!-11.38"'( .'!* !!!%!-11.68"'( .)!* !"# .,!'!-11.64"'( )&!* !!!%!-11.41"'( )-!* !"# -(!'!-11.64"'( )%!* !!!%!-11.29"'( /#!* !"# %,!'!-11.54"'( .'!* !!!%!-11.19"'( -'!* !"# ()!'!-11.64"'( ##!* !!!%!-11.15"'( -'!* !Parameters of transceivers for D LS Timing system (O M3, 2.5G bps - M3-250-P A T, F T L F8524P2B N L)Aver. Output power- (7.9-9.5) dBm24 April 2012Tuesday, April 24, 2012Min. Input Power-17 dBmE ye diagramsjukka.pietarinen@mrf.fi
Micro-Research Finland OyEVG OECEye window 260-280psEVG (1000m OM3 6xCouplers) OECEye window 260-280ps24 April 2012Tuesday, April 24, 2012EVG (550m OM3 4xCouplers) SP L T OEC - Typical situation for networkEye window 240-280psEVG (1000m OM3 6xCouplers) SP L T OEC Extremal situation for networkEye window 220-260psConclusion:Using splitter is allowed in the timing distribution system:- The actual signal levels exceed on 2-3 dBm receiver sensitivity of transceiver.- Eye diagram of the data signal after the splitter remains practically unchanged.jukka.pietarinen@mrf.fi
Micro-Research Finland OyPassive Optical Splitters inTiming Distribution Network 2-way splitter insertion loss 3 dBUse of splitter to connect EVG to fan-outFan-out to fan-out connectionsReduce number of fan-out levels24 April 2012Tuesday, April 24, 2012jukka.pietarinen@mrf.fi
Micro-Research Finland OyVME-ADC-300 Design New digitizer design National Semiconductor ADC12D1000–12-bit–1.0 GSPS dual ADC–ENOB 9.6 Bits (typ)–SNR 60.2 dB (typ)–Full Power Bandwidth 2.8 GHz Mezzanine for Analog Front End Integrated EVR with timing (conversion clock andtriggers) from Event System Allow use of VME P0 for gigabit serial connectivity24 April 2012Tuesday, April 24, 2012jukka.pietarinen@mrf.fi
Micro-Research Finland OyForm FactorsVMEEVGEVRxxPMCxCompactPCI 3UxxCompactPCI 6UxxPCI ExpressPXI Express 3U24 April 2012Tuesday, April 24, 2012x(x)xjukka.pietarinen@mrf.fi
Micro-Research Finland OyFuture Form Factors? AMC? or XMC (VITA 42)?–I/O through VHDCI connector?–could be used on an AMC carrier24 April 2012Tuesday, April 24, 2012jukka.pietarinen@mrf.fi
24 April 2012 jukka.pietarinen@mrf.fi Interface Board IFB-300 Schroff 24572-100 ratiopacPRO case – 1U 42.5 mm high, 255.5 mm deep – Holds one 6U PCB Eight Universal I/O slots Four indicator/status LEDs 19” Rack mount brackets available Tuesday, April 24, 2012
Ergonomics Ergonomic Evaluation Procedures . 19 August 2022 SLAC-I-730-0A21S-059-R004 6 of 6 . 5 References . SLAC Environment, Safety, and Health Manual (SLAC-I-720-0A29Z-001) Chapter 54, "Ergonomics" Other SLAC Documents SLAC Training Assignment (STA) ESH Course 291, Ergonomics Training - Office Worker (ESH Course 291)
APS EPICS Training Andrew Johnson 2014-09-18 Introduction to EPICS 8 2: EPICS Control System Architecture Servers give Clients access to named Process Variables (PVs) – Each PV holds a piece of data associated with the machine Status, read-back, set-point, parameter
R. Helmke ERL@CESR Controls 8-3-2007 3 ERL Gun Prototype Control ("W128") Prototype ERL Gun has been constructed in Room W128 Wilson Lab. Controls for the Gun and associated instrumentation based on EPICS software. Provided our first significant experience with EPICS and opportunity to assess feaopportunity to assess feasibility of using EPICS for an ERL sibility of using EPICS for an ERL
timing pulleys timing pulleys with pilot bore type mxl - xl - l - h - xh page 4 export timing pulleys type xl - l - h page 20 taper-lock timing pulleys type l - h page 29 htd timing pulleys with pilot bore type 3m - 5m - 8m - 14m page 38 htd taper lock timing pulleys type 5m - 8m - 14m page 54 gt timing pulleys type 3mr - 5mr page 65 poly chain gt timing pulleys
SEM service desk at x8901. DOE Security Conditions and New SLAC Badge Policy AS ALL OF YOU know, since September 11th SLAC . as SLAC and Fermilab. Speakers included Tim Berners-Lee (via video from MIT), Paul Kunz and Tony Johnson of SLAC, and Chris Quigg and David Ritchie of Fermila
Drive Belt Tensioner Drive Belt Tensioner Damper M/T Air Cleaner Duct Oil Filler Cap No.3 Timing Belt Cover Gasket No.2 Timing Belt Cover No.5 Air Hose Water Pump Pulley Drive Belt Camshaft Timing Pulley Drive Belt Tensioner Hold-Down Clamp Idler Pulley Battery Insulator Battery Tray Battery Timing Belt Gasket No.1 Timing Belt Cover Crankshaft .
The ControlLogix analog I/O modules have the capability to convert signals to engineering units Thermocouple and RTD signals should be converted to engineering units by the T/C and RTD I/O modules. » The converted values will be monitored by EPICS Linear analog input signals should be converted to engineering units by the analog input module .
Russell, S. and P. Norvig Artificial Intelligence: A Modern Approach. (Upper Saddle River, NJ: Prentice Hall, c2010) third edition [ISBN 9780132071482 (pbk); 9780136042594 (hbk)]. Russell and Norvig is one of the standard AI textbooks and covers a great deal of material; although you may enjoy reading all of it, you do not need to. The chapters that you should read are identified in the .
