A Constant ON-Time 3-Level Buck Converter For Low Power .
A Constant ON-Time 3-Level Buck Converter for Low PowerApplicationsBrian Michael CassidyThesis submitted to the faculty of theVirginia Polytechnic Institute and State Universityin partial fulfillment of the requirements for the degree ofMaster of ScienceInElectrical EngineeringDong S. Ha, ChairQiang Li, Co-ChairKwang-Jin KohJanuary 30, 2015Blacksburg, VAKeywords: 3-Level Buck Converter, Constant ON-Time Control (COT), Light-loadefficiency, Pulse Frequency Modulation, Low Power ApplicationsCopyright 2015, Brian Michael Cassidy
A Constant ON-Time 3-Level Buck Converter for Low Power ApplicationsBrian Michael CassidyABSTRACTSmart cameras operate mostly in sleep mode, which is light load for power supplies.Typical buck converter applications have low efficiency under the light load condition, primarilyfrom their power stage and control being optimized for heavy load. The battery life of a smartcamera can be extended through improvement of the light load efficiency of the buck converter.This thesis research investigated the first stage converter of a car black box to provide power to amicroprocessor, camera, and several other peripherals. The input voltage of the converter is 12V, and the output voltage is 5 V with the load range being 20 mA (100 mW) to 1000 mA (5000mW). The primary design objective of the converter is to improve light load efficiency.A valley current mode controlled 3-level buck converter proposed by Reusch wasadopted for the converter in this thesis. A 3-level buck converter has two more MOSFETs andone more capacitor than a synchronous buck converter. Q1 and Q2 are considered the topMOSFETs, while Q3 and Q4 are the synchronous ones. The extra capacitor is used as a secondpower source to supply the load, which is connected between the source of Q1 and the drain ofQ2 and the source of Q3 and the drain of Q4. The methods considered to improve light loadefficiency are: PFM (pulse frequency modulation) control scheme with DCM (discontinuousconduction mode) and use of Schottky diodes in lieu of the synchronous MOSFETs, Q3 and Q4.The 3-level buck converter operates in CCM for heavy load above 330 mA and DCM for lightload below 330 mA. The first method uses a COT (constant on-time) valley current modecontroller that has a built in inductor current zero-crossing detector. COT is used to implementPFM, while the zero-crossing detector allows for DCM. The increase in efficiency comes fromreducing the switching frequency as the load decreases by minimizing switching and gate drivingloss. The second method uses an external current sense amplifier and a comparator to detectwhen to shut down the gate drivers for Q3 and Q4. Schottky diodes in parallel with Q3 and Q4
carry the load current when the MOSFETs are off. This increases the efficiency through areduction in switching loss, gate driving loss, and gate driver power consumption.The proposed converter is prototyped using discrete components. LTC3833 is used as theCOT valley current mode controller, which is the center of the control scheme. The efficiency ofthe 3-level buck converter was measured and ranges from 82% to 95% at 100 mW and 5000mW, respectively. The transient response of the converter shows no overshoot due to a 500 mAload step up or down, and the output voltage ripple is 30 mV. The majority of the loss comesfrom the external components, which include a D FF (D flip-flop), AND gate, OR gate, currentsense chip, comparator, and four gate drivers. The proposed converter was compared to two offthe-shelf synchronous buck converters. The proposed converter has good efficiency andperformance when compared to the other converters, despite the fact that the converter isrealized using discrete components.iii
To my parents, sister and brothersiv
AcknowledgementsFirst and foremost I would like to offer my sincerest gratitude and thanks to my advisor,Dr. Dong S. Ha, who has guided me throughout my graduate study at Virginia Tech. I wouldlike thank Dr. Qiang Li for his help, guidance, and expert knowledge in power electronics thathelp me enormously with my thesis research. I would also like to thank Dr. Kwang-Jin Koh forbeing part of my advisory committee and his sincere interest in my studies.I would like to thank Virginia Tech and Dr. De La Ree for the opportunity to be agraduate teaching assistant that provide scholarship and funding for my graduate study. Inaddition, I would like to thank Texas Instruments, Linear Technology, and Coilcraft forproviding sample components for my prototype. This work was supported in part by the Centerfor Integrated Smart Sensors funded by the Korea Ministry of Science, ICT & Future Planningas Global Frontier Project (CISS-2-3).My sincerest appreciation goes to my colleagues, Taylor Yeago, Ross Kerley, ThomasO’Connor, and Dan Ridenour for their help on my thesis research as well as their support. Manythanks go to my colleagues in the MICS group for their support and insight throughout.Special thanks go to Erica Eley for her love and support throughout graduate school.Thanks to my friends for making my graduate experience at Virginia Tech unforgettable.Finally, I would like to thank my parents, Tim and Kathy, my brothers, Kenny, Brett,and Timmy, and my sister, Jennifer, for their never ending love, encouragement, and patience. Iwould also like to thank my grandparents, aunts, and uncles for their support. It means more tome than I can express.v
Tabel of ContentsABSTRACT . iiAcknowledgements . vTabel of Contents . viList of Figures . ixList of Tables . xiiiChapter 1, Introduction . 11.1 Motivation . 11.2 Scope of the Proposed Research . 11.3 Technical Contributions of the Proposed Research . 31.4 Organization of the Thesis . 3Chapter 2, Preliminaries . 52.1 Design Requirements . 52.2 Buck Converter . 62.2.1 Approach to Improve Efficiency .102.2.2 Breakdown Voltage . 112.2.3 Zhou’s Approaches . 112.2.4 Shortcomings . 142.3 3-Level Buck Converrter . 142.3.1 Reusch Valley Current Mode 3-Level Buck Converter . 142.3.2 Low Voltage Devices . 182.3.3 Component Design . 20vi
2.3.4 Shortcomings . 212.4 Chapter summary . 21Chapter 3, Proposed 3-Level Buck Converter . 223.1 Specification of the Proposed Converter . 223.2 Block Diagram of the Proposed Converter . 223.3 Power Stage . 243.3.1 Circuit Diagram . 243.3.2 Phases Operation . 253.4 Control Block Diagram of the Controller . 263.4.1 Contoller Design . 273.4.2 Operation under Three Different Load Conditions . 293.4.3 Bandwidth of the Controller . 323.4.4 Gate Driving Circuit . 333.5 Component Design and Selection . 353.6 Chapter Summary . 39Chapter 4, Expiremental Results. 404.1 Measurement Setup . 404.2 Measurement Results . 434.2.1 Transient Waveforms . 444.2.1.1 Light Load . 444.2.1.2 Heavy Load . 454.2.1.3 Load Trasient Performance . 474.2.2 Efficiency. 494.2.3 Loss Breakdown . 534.3 Efficiency Comparison . 55vii
4.3.1 Comparison with Active-Semi ACT4070B . 554.3.2 Comparison with Linear Technology LTC3646 . 564.4 Chapter Summary . 58Chapter 5, Conclusion. 59Appendix, Additional Information. 61A. Previous Gate Driving Method. 61B. Control Loop Design . 63C. Pulse Skipping . 66D. EXTVcc . 69References . 70viii
List of FiguresFigure 2.1 Power block diagram for Car Black Box. . 6Figure 2.2 Asynchronous buck converter from E. V. Mehta and E. P. Malik, "Comparisonbetween Asynchronous and Synchronous Buck Converter Topology," InternationalJournal of Applied Engineering Research, vol. 7, no. 11, 2012. Used under fair use, 2015. 6Figure 2.3 Synchronous buck converter D. Reusch, High Frequency, High Power DensityIntegrated Point of Load and Bus Converters, Ph.D. dissertation, ECE, Virginia Tech,Blacksburg, VA, 2012. Used under fair use, 2015. . 7Figure 2.4 (a) Multi-phase buck converter schematic from P. Xu, Multiphase Voltage RegulatorModules with Magnetic Integration to Power Microprocessors, Ph.D. dissertation, ECE,Virginia Tech, Blacksburg, VA, 2002. (b) Timing diagram for two phase buck from D.Baba, Benefits of a multiphase buck converter, Texas Instruments Application Note, 2012.Used under fair use, 2015. . 9Figure 2.5 Constant frequency control loss breakdown from P. Vivek, Extending Efficiency in aDC/DC converter with automatic mode switching from PFM to PWM, M.S. Thesis, ECE,Arizon Statue University, Phoenix, AZ, 2014. Used under fair use, 2015. 10Figure 2.6 PFM control loss breakdown from P. Vivek, Extending Efficiency in a DC/DCconverter with automatic mode switching from PFM to PWM, M.S. Thesis, ECE, ArizonStatue University, Phoenix, AZ, 2014. Used under fair use, 2015. . 10Figure 2.7 Schematic of the proposed converter from X. Zhou, M. Donati, L. Amoroso, and F.C. Lee, "Improved Light-Load Efficiency for Synchronous Rectifier Voltage RegulatorModule," in IEEE Transactions on Power Electronics, Vol. 15, No. 5, pp. 826-834, 2000.Used under fair use, 2015. . 12Figure 2.8 Efficiency of CCM and Schottky diode DCM (w/o Ssyn) from X. Zhou, M. Donati,L. Amoroso, and F. C. Lee, "Improved Light-Load Efficiency for Synchronous RectifierVoltage Regulator Module," in IEEE Transactions on Power Electronics, Vol. 15, No. 5,pp. 826-834, 2000. Used under fair use, 2015. 12Figure 2.9 Efficiency curve from X. Zhou, M. Donati, L. Amoroso, and F. C. Lee, "ImprovedLight-Load Efficiency for Synchronous Rectifier Voltage Regulator Module," in IEEEix
Transactions on Power Electronics, Vol. 15, No. 5, pp. 826-834, 2000. Used under fair use,2015. . 13Figure 2.10 Efficiency of the hybrid MOSFET (w/ Ssyn) and hybrid Schottky diode (w/o Ssyn)method from X. Zhou, M. Donati, L. Amoroso, and F. C. Lee, "Improved Light-LoadEfficiency for Synchronous Rectifier Voltage Regulator Module," in IEEE Transactions onPower Electronics, Vol. 15, No. 5, pp. 826-834, 2000. Used under fair use, 2015. . 13Figure 2.11 3-Level Buck Converter schematic and timing diagram. . 14Figure 2.12 Four phases of operation a) Phase 1, b) Phase 2, c) Phase 3, d) Phase 4. . 15Figure 2.13 3-level buck converter schematic and timing diagram from D. Reusch, HighFrequency, High Power Density Integrated Point of Load and Bus Converters, Ph.D.dissertation, ECE, Virginia Tech, Blacksburg, VA, 2012. Used under fair use, 2015. . 16Figure 2.14 Inductor current balancing due to valley threshold when Vc 0.5 Vin from D.Reusch, High Frequency, High Power Density Integrated Point of Load and BusConverters, Ph.D. dissertation, ECE, Virginia Tech, Blacksburg, VA, 2012. Used under fairuse, 2015. . 17Figure 2.15 Inductor current balancing due to valley threshold when Vc 0.5 Vin from D.Reusch, High Frequency, High Power Density Integrated Point of Load and BusConverters, Ph.D. dissertation, ECE, Virginia Tech, Blacksburg, VA, 2012. Used under fairuse, 2015. . 18Figure 2.16 MOSFET FOM versus breakdown voltage from D. Reusch, High Frequency, HighPower Density Integrated Point of Load and Bus Converters, Ph.D. dissertation, ECE,Virginia Tech, Blacksburg, VA, 2012. Used under fair use, 2015. . 19Figure 2.17 Efficiency comparison of traditional buck versus 3-level buck converter from D.Reusch, High Frequency, High Power Density Integrated Point of Load and BusConverters, Ph.D. dissertation, ECE, Virginia Tech, Blacksburg, VA, 2012. Used under fairuse, 2015. . 19Figure 2.18 Inductance of a 3-level buck versus a traditional buck converters from D. Reusch,High Frequency, High Power Density Integrated Point of Load and Bus Converters, Ph.D.dissertation, ECE, Virginia Tech, Blacksburg, VA, 2012. Used under fair use, 2015. 20Figure 3.1 Block diagram of 3-level buck converter with control logic. . 24Figure 3.2 Circuit Diagram of the Power Stage of the Proposed Converter. 25x
Figure 3.3 Four Phases of operation (a) Phase 1, (b) Phase 2, (c) Phase 3, (d) Phase 4. . 26Figure 3.4 Control loop of the prototyped converter. . 28Figure 3.5 Heavy load timing diagram. . 30Figure 3.6 Light load timing diagram. . 31Figure 3.7 Very light load timing diagram. . 32Figure 3.8 Control loop bandwidth of converter from LTpowerCAD II. . 33Figure 3.9 3-level buck converter gate drivers and the power stage. . 34Figure 3.10 Node A and SW are connected, allowing Q1 bootstrap capacitor to charge. . 34Figure 3.11 CCM loss breakdown of each MOSFET. . 38Figure 3.12 DCM MOSFET Loss at 100 mA. . 39Figure 4.1 Prototype of the Proposed Converter. . 41Figure 4.2 Efficiency measurement test setup. . 42Figure 4.3 Load transient test setup. . 43Figure 4.4 Switching frequency versus load current under light load. . 44Figure 4.5 Output ripple voltage, frequency, and load current load current under light load. . 45Figure 4.6 Switching frequency versus load current under heavy load. . 46Figure 4.7 Output ripple voltage under maximum load. 46Figure 4.8 Output voltage and Q1 gate signal due to load step up. . 47Figure 4.9 Inductor current change due to load step. 48Figure 4.10 Output voltage and Q1 gate signal due to load step down. . 49Figure 4.11 Inductor current change due to load step down. . 49Figure 4.12 CCM efficiency versus load current. . 50Figure 4.13 Light load DCM and CCM efficiency versus load current. . 51Figure 4.14 Very light load DCM efficiency versus load current. . 52Figure 4.15 Ideal efficiency over load range 1 mA to 1650 mA. . 53Figure 4.16 Breakdown of losses. . 54Figure 4.17 ACT4070B efficiency versus load current from A. Semi, "Wide Input 3A StepDown Conveter," ACT4070B datasheet, 2013. [Online]. Available: http://www.activesemi.com/sheets/ACT4070B Datasheet.pdf. [Accessed 15- May- 2014]. Used under fairuse, 2015. . 55Figure 4.18 3-level buck vs. ACT4070B power loss comparison. . 56xi
Figure 4.19 Efficiency vs load current from L. Technology, "40V, 1A Synchronous Step-DownConverter," LTC3646 datasheet. [Online]. 36461fb.pdf. [Accessed 10- Dec- 2014]. Usedunder fair use 2015. . 57Figure 4.20 3-level buck vs. LTC3646 power loss comparison. . 58Figure A.1 Reusch gate driving method from D. Reusch, High Frequency, High Power DensityIntegrated Point of Load and Bus Converters, Ph.D. dissertation, ECE, Virginia Tech,Blacksburg, VA, 2012. Used under fair use, 2015. . 61Figure A.2 Very light load schematic . 62Figure B.1 SIMPLIS Schematic . 64Figure B.2 Flying capacitor balancing at one-half Vin (14 V). . 65Figure C.1 LTC3833 Pin Label from L. Technology, "Fast Accurate Step-Down DC/DCContoller with Differential Output Sensing," LTC3833 datasheet. [Online]. 3833f.pdf. [Accessed 10- Jun- 2014]. Used underfair use, 2015. 66Figure C.2 Example of burst mode. . 67Figure C.3 Proper operation of the controller with 5 V input. . 68xii
List of TablesTable 1 First Stage Buck Converter Specifications . 22Table 2 MOSFET Survey of TI NexFETs [23] [24] [25]. . 37xiii
Chapter 1Introduction1.1 MotivationEvent data recorders, often called car black boxes, are being installed in most Americancars today. The device collects information such as speed, accelerator position, brake position,etcetera of during a crash and the prior moment. As of September 1st 2014, the NationalHighway Traffic Safety Administration mandates every car to be equipped with a car black box[1].The car black box proposed by the Korean Advanced Institute of Science andTechnology (KAIST) team in Korea records video of the front and rear view of the car. The carblack box is mostly in sleep mode while waiting for detection of an event. Upon detection of anevent, it wakes up and starts to record. Since a car black box is powered by the car battery andmostly in sleep mode, high efficiency for light load is important, especially when the engine isturned off. The proposed research in this thesis is to improve light load efficiency of a powerconverter, targeting the black box developed by the KAIST team.1.2 Scope of the Proposed ResearchDC-to-DC buck converters are used to convert the car battery voltage down to lower DCvoltages necessary for the black box. A two stage approach is usually taken to efficiently step a12 V input voltage down to lower voltages. The first stage steps the battery voltage down to aregulated 5 V for USB hosts and a camera. The second stage steps down the 5 V to various DCvoltages.A traditional synchronous buck converter can be used for both the first and second stage.1
One major difference between the two stages is the breakdown voltage required for theMOSFETs. The breakdown voltage of a MOSFET used in a buck converter is typically twotimes the input voltage, which prevents overshoot, ringing and others from damaging the device[2]. Therefore, the first stage requires the breakdown voltage of about 30 V, considering themaximum car battery voltage of 14.2 V. Low voltage devices typically have bettercharacteristics, such as low on-resistance and gate charge, which improves the light loadefficiency. The proposed research is to improve light load efficiency of the first stage converter,specifically a 12 V to 5 V DC/DC converter, through adoption of a 3-level buck converterconfiguration that enables use of devices with a lower breakdown voltage.The proposed 3-level buck converter uses research by Reusch as the starting point [3].The 3-level buck converter has four phases of operation, in which the inductor and outputcapacitor are charged twice within one switching period. It has two additional MOSFETs and anextra capacitor compared to a traditional buck. The main advantages of the 3-level buckconverter are the ability to use low voltage devices and smaller passive values compared to atraditional buck at the same frequency.The 3-level buck converter designed in [3] adopts a constant frequency control method.This control method is efficient for heavy load, but light load efficiency suffers significantly.This is essentially due to the converter connecting the input voltage source to the load moreoften than necessary for light load. It wastes power in the form of conduction loss, gate drivingloss, and switching loss to result in low efficiency.Zhou proposed several methods to improve light load efficiency of buck converters [4].Among the methods, a hybrid control approach adopts PFM (pulse frequency modulation) inDCM (discontinuous conduction mode) that reduces the switching frequency proportional to theload. Reducing the switching frequency decreases the amount of conduction, switching, andgate driving losses. The converter only connects the input source to the load only when it isnecessary, which is inherently more efficient for light load.A 3-level buck converter was investigated that adopts the control approach to improvelight load efficiency. The 3-level buck converter utilizes constant on-time (COT) control inPFM, with DCM being implemented by detecting the point when the inductor current reacheszero. The reduction in switching frequency as the load decreases leads to less loss and higher2
efficiency when compared to CCM (continuous conduction mode).1.3 Technical Contributions of the Proposed ResearchThe first stage buck converter targeted for the KAIST car black box was designed andprototyped. The major design objective of the converter is high efficiency at light load.Technical contributions of the proposed research are as follows.First, the power stage of the converter was successfully designed to meet the objective,high efficiency in light load, for the target application. The MOSFET selection was discussed indetail, and the power stage was optimized iteratively through simulation and performancemeasurement of prototypes.Second, the control loop was successfully designed to meet the same objective, and itadopts COT valley current mode control and DCM. An off-the-shelf synchronous buckcontroller was selected as the core of the control loop. The gate signals, generated by thecontroller, are passed through a series of digital gates to generate the appropriate driving signalfor each MOSFET in the 3-level buck converter. The control loop was simulated in LTspice toensure proper operation.Third, the proposed converter is prototyped using discrete components and an existingcontroller to demonstrate the control scheme and design. The prototype demonstrates correctoperation of the control scheme such that the switching frequency reduces with the load currentin light load. It also demonstrates correct operation of the DCM, which shuts down thesynchronous MOSFETs when the inductor current touches zero. Performance of the converterwas measured using the final prototype. The efficiency is significantly improved whencompared with the CCM mode adopted in Reusch’s converter and other comparable buckconverters.1.4 Organization of the ThesisThe organization of the thesis is as follows. Chapter 2 provides background andpreliminaries for the proposed research wo
A valley current mode controlled 3-level buck converter proposed by Reusch was adopted for the converter in this thesis. A 3-level buck converter has two more MOSFETs and one more capacitor than a synchronous buck converter. Q1 and Q2 are considered t
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