9. Synopsys PrimeTime Support

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9. Synopsys PrimeTime SupportDecember 2010QII53005-10.0.1QII53005-10.0.1PrimeTime is the Synopsys stand-alone full chip, gate-level static timing analyzer. TheQuartus II software makes it easy for designers to analyze their Quartus II projectsusing the PrimeTime software. The Quartus II software exports a netlist, designconstraints (in the PrimeTime format), and libraries to the PrimeTime softwareenvironment. Figure 9–1 shows the PrimeTime flow diagram.Figure 9–1. PrimeTime Software Flow DiagramThe Quartus II SoftwareDesign Netlist(Verilog HDL orVHDL Format)Constraints inPrimeTimeFormatStandard DelayFormat OutputFile (TimingInformation)The PrimeTime SoftwareTiming Reports GeneratedDB libHDL libThis chapter contains the following sections: “Quartus II Settings for Generating the PrimeTime Software Files” “Files Generated for the PrimeTime Software Environment” on page 9–2 “Running the PrimeTime Software” on page 9–6 “PrimeTime Timing Reports” on page 9–7 “Static Timing Analyzer Differences” on page 9–18Quartus II Settings for Generating the PrimeTime Software FilesTo set up the Quartus II software to generate files for the PrimeTime software,perform the following steps:1. In the Quartus II software, on the Assignments menu, click Settings, and thenclick EDA Tool Settings.2. In the Category list, under EDA Tool Settings, select Timing Analysis.3. In the Tool name list, select PrimeTime, and in the Format for output netlist list,select either Verilog HDL or VHDL. 2010 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off.and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described atwww.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, butreserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of devicespecifications before relying on any published information and before placing orders for products or services.Quartus II Handbook Version 11.0 Volume 3: VerificationDecember 2010Subscribe

9–2Chapter 9: Synopsys PrimeTime SupportFiles Generated for the PrimeTime Software EnvironmentWhen you compile your project after making these settings, the Quartus II softwareruns the EDA Netlist Writer to create three files for the PrimeTime software. Thesefiles are saved in the revision name /timing/primetime directory by default, where revision name is the name of your Quartus II software revision. If it is not, you haveused the wrong variable name.Files Generated for the PrimeTime Software EnvironmentThe Quartus II software generates a flattened netlist, a Standard Delay Output File(.sdo), and a Tcl script that prepares the PrimeTime software for timing analysis of theQuartus II project. These files are saved in the project directory /timing/primetimedirectory.The Quartus II software uses the EDA Netlist Writer to generate PrimeTime filesbased on either the Classic Timing Analyzer or the TimeQuest Timing Analyzer statictiming analysis results. When you run the EDA Netlist Writer, the PrimeTime .sdofiles are based on delays generated by the currently selected timing analysis tool inthe Quartus II software.To specify the timing analyzer, on the Assignments menu, click Settings. The Settingsdialog box appears. Under Category, click Timing Analysis Settings. Select thetiming analyzer of your choice.f For more information about specifying the Quartus II timing analyzers, refer to eitherthe Quartus II Classic Timing Analyzer or the Quartus II TimeQuest Timing Analyzerchapter in volume 3 of the Quartus II Handbook. Also, refer to the Switching to theQuartus II TimeQuest Timing Analyzer chapter in volume 3 of the Quartus II Handbook tohelp you decide which timing analyzer is most appropriate for your design.The NetlistDepending on whether Verilog HDL or VHDL is selected as the Format for outputnetlist option, in the Tool name list on the Timing Analysis page of the Settingsdialog box, the netlist is written and saved as either project name .vo or project name .vho, respectively. This file contains the flattened netlist representingthe entire design.1When you select the TimeQuest analyzer, only a Verilog HDL PrimeTime netlist canbe generated.The .sdo FileThe Quartus II software saves the .sdo file as either revision name v.sdo or revision name vhd.sdo, depending on whether you select Verilog HDL or VHDLin the Tool name list on the Timing Analysis page of the Settings dialog box.This file contains the timing information for each timing path between any two nodesin the design.When you enable the Classic Timing Analyzer, the slow-corner (worst-case) timingmodels are used by default when generating the .sdo file. To generate the .sdo fileusing the fast-corner (best-case) timing models, perform the following steps:Quartus II Handbook Version 11.0 Volume 3: VerificationDecember 2010 Altera Corporation

Chapter 9: Synopsys PrimeTime SupportFiles Generated for the PrimeTime Software Environment9–31. In the Quartus II software, on the Processing menu, point to Start and click StartClassic Timing Analyzer (Fast Timing Model).2. After the fast-corner timing analysis is complete, on the Processing menu, point toStart and click Start EDA Netlist Writer to create a revision name v fast.sdo or revision name vhd fast.sdo file, which contains the best-case delay values foreach timing path.1If you are running a best-case timing analysis, the Quartus II software generates a Tclscript similar to the following: revision name pt v fast.tcl.When the TimeQuest analyzer is run with the fast-corner netlist, or when theOptimize fast-corner timing check box is selected in the Fitter Settings dialog box,the fast-corner Synopsys Design Constraints File (.sdc) file is generated.After the EDA Netlist Writer has finished, two .sdc files are created: revision name v.sdo (slow corner) and revision name v fast.sdo (fast corner).Generating Multiple Operating Conditions with the TimeQuest AnalyzerYou can specify different operating conditions to the EDA Netlist Writer forPrimeTime analysis. The different operating conditions are reflected in the .sdo filegenerated by the EDA Netlist Writer.1From the TimeQuest analyzer console pane, use the commandget available operating conditions to obtain a list of available operatingconditions for the target device.The following steps show how to generate the .sdo files for the three differentoperating conditions for a Stratix III design. Enter each command at the commandprompt.1The --tq2pt option for quartus sta is required only if the project does not specifythat the PrimeTime tool is be used as the timing analysis tool.1. Generate the first slow-corner model at the operating conditions: slow, 1100 mV,and 85º C.quartus sta --model slow --voltage 1100 --temperature 85 project name 2. Generate the fast-corner model at the operating conditions: fast, 1100 mV, and 0º C.quartus sta --model fast --voltage 1100 --temperature 0--tq2pt project name 3. Generate the PrimeTime output files for the corners specified above. The outputfiles are generated in the primetime two corner files directory.quartus eda --timing analysis --tool primetime--format verilog--output directory primetime two corner files--write settings files off project name December 2010Altera CorporationQuartus II Handbook Version 11.0 Volume 3: Verification

9–4Chapter 9: Synopsys PrimeTime SupportFiles Generated for the PrimeTime Software Environment4. Generate the second slow-corner model at the operating conditions: slow,1100 mV, and 0º C.quartus sta --model slow --voltage 1100 --temperature 0--tq2pt project name 5. Generate the PrimeTime output files for the second slow corner. The output filesare generated in the primetime one slow corner files directory.quartus eda --timing analysis --tool primetime--format verilog--output directory primetime one slow corner files--write settings files off revisionTo summarize, the previous steps generate the following files for the three operatingconditions:1 First slow corner (slow, 1100 mV, 85º C):.vo file—primetime two corner files/ project name .vo.sdo file—primetime two corner files/ project name v.sdo Fast corner (fast, 1100 mV, 0º C):.vo file—primetime two corner files/ project name .vo.sdo file—primetime two corner files/ project name v fast.sdo Second slow corner (slow, 1100 mV, 0º C):.vo file—primetime one slow corner files/ project name .vo.sdo file—primetime one slow corner files/ project name v.sdoThe primetime one slow corner files directory may also have files for fast corner.These files can be ignored because they were already generated in theprimetime two corner files directory.The Tcl ScriptThe Tcl script generated by the Quartus II software contains information required bythe PrimeTime software to analyze the timing and set up your post-fit design. Thisscript specifies the search path and the names of the PrimeTime database library filesprovided with the Quartus II software. The search path and link path variables aredefined at the beginning of the Tcl file. The link path variable is a space-delimited listthat contains the names of all database files used by the PrimeTime software.Depending on whether you select Verilog HDL or VHDL in the Format for outputnetlist list on the Timing Analysis page of the Settings dialog box, when the ClassicTiming Analyzer is enabled, the EDA Netlist Writer generates and saves the script aseither revision name pt v.tcl or revision name pt vhd.tcl.To access the EDA Settings dialog box, perform the following:1. On the Assignments menu, click Settings, and then click EDA Tool Settings2. Expand EDA Tool Settings under the Category list.In the dialog box, you can specify VHDL or Verilog HDL for the format of the outputnetlist.Quartus II Handbook Version 11.0 Volume 3: VerificationDecember 2010 Altera Corporation

Chapter 9: Synopsys PrimeTime SupportFiles Generated for the PrimeTime Software Environment19–5The script also directs the PrimeTime software to use the device family all pt.v or device family all pt.vhd file, which contains the Verilog HDL or VHDL descriptionof library cells for the targeted device family.Example 9–1 shows the search path and link path variables defined in the Tcl script:Example 9–1. Sample PrimeTime Setup Scriptset quartus root "altera/quartus/"set search path [list . [format "%s%s" quartus root "eda/synopsys/primetime/lib"]]set link path [list * stratixii lcell comb lib.db stratixii lcell ff lib.dbstratixii asynch io lib.db stratixii io register lib.db stratixii termination lib.dbbb2 lib.db stratixii ram internal lib.db stratixii memory register lib.dbstratixii memory addr register lib.db stratixii mac out internal lib.dbstratixii mac mult internal lib.db stratixii mac register lib.dbstratixii lvds receiver lib.db stratixii lvds transmitter lib.dbstratixii asmiblock lib.db stratixii crcblock lib.db stratixii jtag lib.dbstratixii rublock lib.db stratixii pll lib.db stratixii dll lib.db alt vtl.db]read vhdl-vhdl compilerstratixii all pt.vhdThe EDA Netlist Writer converts any Classic Timing Analyzer timing assignments tothe PrimeTime software constraints and exceptions when it generates the PrimeTimefiles. The converted constraints are saved to the Tcl script. The Tcl script also includesa PrimeTime software command that reads the .sdo file generated by the Quartus IIsoftware. You can place additional commands in the Tcl script to analyze or report ontiming paths.Table 9–1 shows some examples of timing assignments converted by the Quartus IIsoftware for the PrimeTime software. For example, the set input delay -maxcommand sets the input delay on an input pin.Table 9–1. Equivalent Quartus II and PrimeTime Software ConstraintsQuartus II EquivalentPrimeTime ConstraintClock defined on input pin, clock of 10 nsperiod and 50% duty cyclecreate clock -period 10.000 -waveform {0 5.000} \[get ports clk] -name clkInput maximum delay of 1 ns on input pin, dinset input delay -max -add delay 1.000 -clock \[get clocks clk] [get ports din]Input minimum delay of 1 ns on input pin, dinset input delay -min -add delay 1.000 -clock \[get clocks clk] [get ports din]Output maximum delay of 3 ns on output pin,outset output delay -max -add delay 3.000 -clock \[get clocks clk] [get ports out]When the TimeQuest analyzer is turned on, the EDA Netlist Writer generates andsaves the script as revision name .pt.tcl.The EDA Netlist Writer converts all TimeQuest analyzer .sdc constraints andexceptions into compatible PrimeTime software constraints and exceptions when itgenerates the PrimeTime files. The constraints and exceptions are saved to the revision name .constraints.sdc file.December 2010Altera CorporationQuartus II Handbook Version 11.0 Volume 3: Verification

9–6Chapter 9: Synopsys PrimeTime SupportRunning the PrimeTime SoftwareGenerated File SummaryThe files that are generated by the EDA Netlist Writer for the PrimeTime softwaredepend on the Quartus II timing analysis tool you select.Table 9–2 shows the files that are generated for the PrimeTime software when theClassic Timing Analyzer is selected.Table 9–2. Classic Timing Analyzer-Generated PrimeTime FilesFileDescription revision name .vho revision name .voThe PrimeTime software output netlist. Either a VHDL Output File (.vho) or a VerilogOutput File (.vo) is generated, depending on the output netlist language set. revision name vhd.sdo revision name v.sdoThe PrimeTime software standard delay file. Either a VHDL Standard Delay Output File(vhd.sdo) or a Verilog Standard Delay Output File (v.sdo) is generated, depending on theoutput netlist language set. revision name pt vhd.tcl revision name pt v.tclPrimeTime setup and constraint script. Either a VHDL Tcl Script File (vhd.tcl) or aVerilog Tcl Script File (v.tcl) is generated, depending on the output netlist language set.Table 9–3 shows the files that are generated for the PrimeTime software when theTimeQuest analyzer is selected. The EDA Netlist Writer supports the output netlistformat only when the TimeQuest analyzer is enabled.Table 9–3. TimeQuest Timing Analyzer-Generated PrimeTime FilesFileDescription revision name .voThe PrimeTime software output netlist. When the TimeQuest analyzer is enabled,only PrimeTime (Verilog HDL) is supported. revision name v.sdo revision name v fast.sdoThe PrimeTime software standard delay file. When the TimeQuest analyzer isenabled, only PrimeTime (Verilog HDL) is supported. revision name .pt.tclPrimeTime setup and constraint script. When the TimeQuest analyzer is enabled,only PrimeTime (Verilog HDL) is supported. revision name .collections.sdcContains the mapping from the TimeQuest analyzer netlist to the PrimeTime netlist. revision name .constraints.sdcContains the converted TimeQuest analyzer constraints for the PrimeTimesoftware.Running the PrimeTime SoftwareThe PrimeTime software runs only on UNIX operating systems. If the Quartus IIoutput files for the PrimeTime software were generated by running the Quartus IIsoftware on a PC/Windows-based system, follow these steps to run the PrimeTimesoftware using Quartus II output files:1. Install the PrimeTime libraries on a UNIX system by installing the Quartus IIsoftware on UNIX.The PrimeTime libraries are located in the Quartus II installationdirectory /eda/synopsys/primetime/lib directory.2. Copy the Quartus II output files to the appropriate UNIX directory. You may needto run a PC to UNIX program, such as dos2unix, to remove any control characters.Quartus II Handbook Version 11.0 Volume 3: VerificationDecember 2010 Altera Corporation

Chapter 9: Synopsys PrimeTime SupportPrimeTime Timing Reports9–73. Modify the Quartus II path in Tcl scripts to point to the PrimeTime libraries usingthe first line of Example 9–1:set quartus root "altera/quartus/" set search path [list . [format"%s%s" quartus root "eda/synopsys/primetime/lib"] ]Analyzing Quartus II ProjectsThe PrimeTime software is controlled with Tcl scripts and can be run throughpt shell. You can run the revision name pt v.tcl script file. For example, type thefollowing at a UNIX system command prompt:pt shell -f revision name pt v.tcl rWhen the TimeQuest analyzer is selected, type the following at a UNIX systemcommand prompt:pt shell -f revision name .pt.tcl rAfter all Tcl commands in the script are interpreted, the PrimeTime software returnscontrol to the pt shell prompt, which allows you to use other commands.Other pt shell CommandsYou can run additional pt shell commands at the pt shell prompt, including theman program. For example, to read documentation about the report timingcommand, type the following at the pt shell prompt:man report timing rYou can list all commands available in pt shell by typing the following at thept shell prompt:help rType quit r at the pt shell prompt to close pt shell.1You can also run pt shell without a script file by typing pt shellr at the UNIXcommand line prompt.PrimeTime Timing ReportsThis section describes PrimeTime timing reports.Sample PrimeTime Software Timing ReportAfter running the script, the PrimeTime software generates a timing report. If thetiming constraints are not met, Violated is displayed at the end of the timing report.The timing report also gives the negative slack.December 2010Altera CorporationQuartus II Handbook Version 11.0 Volume 3: Verification

9–8Chapter 9: Synopsys PrimeTime SupportPrimeTime Timing ReportsThe PrimeTime software timing report is similar to the sample shown in Example 9–2.The starting point in this report is a register clocked by clock signal, clock, and theendpoint is another register, inst3-I.lereg.Example 9–2. Hold Path Report in PrimeTimeStartpoint: inst2 I.lereg(rising edge-triggered flip-flop clocked by clock)Endpoint: inst3 I.lereg(rising edge-triggered flip-flop clocked by clock)Path Group: clockPath Type: -----------------------------clock clock (rise edge)0.0000.000clock network delay (propagated)3.1663.166inst2 I.lereg.clk (stratix lcell register)0.0003.166rinst2 I.lereg.regout (stratix lcell register) - 0.176*3.342rinst2 I.regout (stratix lcell)0.000*3.342rinst3 I.datac (stratix lcell)0.000*3.342rinst3 I.lereg.datac (stratix lcell register)3.413*6.755rdata arrival time6.755clock clock (rise edge)0.0000.000clock network delay (propagated)3.0023.002inst3 I.lereg.clk (stratix lcell register)3.002rlibrary hold time0.100*3.102data required ---------------------data required time3.102data arrival ----------------------slack (MET)3.653Comparing Timing Reports from the Classic Timing Analyzer and thePrimeTime SoftwareBoth the Classic Timing Analyzer and the TimeQuest analyzer generate a static timinganalysis report for every successful design compilation. The timing report lists all ofthe timing paths in your design that were analyzed, and indicates whether these pathshave met or violated their timing requirements. Violations are reported only if timingconstraints were specified.The TimeQuest analyzer and PrimeTime use an equivalent set of equations whenreporting the static timing analysis results for a design. However, the Classic TimingAnalyzer uses slightly different reporting equations when reporting the static timinganalysis results for a design. This section describes the differences between the ClassicTiming Analyzer and the PrimeTime software.The timing report generated by the Classic Timing Analyzer differs from the reportgenerated by the PrimeTime software. Both tools provide the same data, but the datais presented in different formats. The following sections show how the PrimeTimesoftware reports the following slack values differently from the Classic TimingAnalyzer report: “Clock Setup Relationship and Slack” on page 9–9 “Clock Hold Relationship and Slack” on page 9–12 “Input Delay and Output Delay Relationships and Slack” on page 9–16Quartus II Handbook Version 11.0 Volume 3: VerificationDecember 2010 Altera Corporation

Chapter 9: Synopsys PrimeTime SupportPrimeTime Timing Reports9–9Clock Setup Relationship and SlackThe Classic Timing Analyzer performs a setup check that ensures that the datalaunched by source registers is latched correctly at the destination registers. TheClassic Timing Analyzer does this by determining the data arrival time and clockarrival time at the destination registers, and compares this data with the setup timedelay of the destination register. Equation 9–1 expresses the inequality that is used fora setup check. The data arrival time includes the longest path from the clock to thesource register, the clock-to-out micro delay of the source register, and the longestpath from the source register to the destination register. The clock arrival time is theshortest delay from the clock to the destination register.Equation 9–1.Clock Arrival – Data Arrival t suSlack is the margin by which a timing requirement is met or not met. Positive slackindicates the margin by which a requirement is met. Negative slack indicates themargin by which a requirement is not met. The Classic Timing Analyzer determinesthe clock setup slack, as shown in Equation 9–2:Equation 9–2.Clock Setup Slack Largest Register-to-Register Requirement – Longest Register-to-Register Delay1The longest register-to-register delay in the previous equation is equal to theregister-to-register data delay.Equation 9–3.Largest Register-to-Register Requirement Setup Relationship between Source and Destination Largest Clock Skew –Micro t co of Destination Register – Micro t su of Destination RegisterSetup Relationship between Source and Destination Latch Edge – Launch EdgeClock Skew Shortest Clock Path to Destination – Longest Clock Path to SourceFigure 9–2 shows a simple three-register design.Figure 9–2. Simple Three-Register DesignDecember 2010Altera CorporationQuartus II Handbook Version 11.0 Volume 3: Verification

9–10Chapter 9: Synopsys PrimeTime SupportPrimeTime Timing ReportsThe Classic Timing Analyzer generates a report for the design, as shown inFigure 9–3.Figure 9–3. Timing Analyzer Report from Figure 9–2Equation 9–1, Equation 9–2, and Equation 9–3 are similar to those found in otherstatic timing analysis tools, such as the PrimeTime software. Equation 9–4 throughEquation 9–7, used by the PrimeTime software, are essentially the same as those usedby the Classic Timing Analyzer, but they are rearranged.Equation 9–4.Slack Data Required – Data ArrivalEquation 9–5.Clock Arrival Latch Edge Shortest Clock Path to DestinationEquation 9–6.Data Required Clock Arrival – Micro t suEquation 9–7.Data Arrival Launch Edge Longest Clock Path to Source Micro tco Longest Data Delay1The longest data delay in the previous equation is equal toregister-to-register data delay.Quartus II Handbook Version 11.0 Volume 3: VerificationDecember 2010 Altera Corporation

Chapter 9: Synopsys PrimeTime SupportPrimeTime Timing Reports9–11Figure 9–4 shows a clock setup check in the Quartus II software.Figure 9–4. Clock Setup Check Reporting with the Classic Timing AnalyzerThe results in Equation 9–8 are obtained by extracting the numbers from the ClassicTiming Analyzer report and applying them to the clock setup slack equations fromthe Classic Timing Analyzer:Equation 9–8.Setup Relationship between Source and Destination Latch Edge – Launch Edge –Clock Setup Uncertainty8.0 – 0.0 – 0.0 8.0nsClock Skew Shortest Clock Path to Destination – Longest Clock Path to Source3.002 – 3.166 – 0.164nsLargest Register-to-Register Requirement Setup Relationship between Source & Destination Largest Clock Skew– Micro t co of Source Register – Micro t su of Destination Register8 – 0.164 – 0.176 – 0.010 7.650nsClock Setup Slack Largest Register-to-Register Requirement – Longest Register-to-Register Delay7.650 – 3.413 4.237nsDecember 2010Altera CorporationQuartus II Handbook Version 11.0 Volume 3: Verification

9–12Chapter 9: Synopsys PrimeTime SupportPrimeTime Timing ReportsFor the same register-to-register path, the PrimeTime software generates a clock setupreport as shown in Example 9–3:Example 9–3. Setup Path Report in PrimeTimeStartpoint: inst2 I.lereg(rising edge-triggered flip-flop clocked by clock)Endpoint: inst3 I.lereg(rising edge-triggered flip-flop clocked by clock)Path Group: clockPath Type: -----------------------------clock clock (rise edge)0.0000.000clock network delay (propagated)3.1663.166inst2 I.lereg.clk (stratix lcell register)0.0003.166rinst2 I.lereg.regout (stratix lcell register) - 0.176*3.342rinst2 I.regout (stratix lcell) 0.000*3.342rinst3 I.datac (stratix lcell) 0.000*3.342rinst3 I.lereg.datac (stratix lcell register)3.413*6.755rdata arrival time6.755clock clock (rise edge)8.0008.000clock network delay (propagated)3.00211.002inst3 I.lereg.clk (stratix lcell register11.002rlibrary setup time-0.010* 10.992data required -----------------------data required time10.992data arrival -----------------------slack (MET)4.237Clock Hold Relationship and SlackThe Classic Timing Analyzer performs a hold time check along everyregister-to-register path in the design to ensure that no hold time violations haveoccurred. The hold time check verifies that data from the source register does notreach the destination until after the hold time of the destination register. The conditionused for a hold check is shown in Equation 9–9:Equation 9–9.Data Arrival – Clock Arrival t HQuartus II Handbook Version 11.0 Volume 3: VerificationDecember 2010 Altera Corporation

Chapter 9: Synopsys PrimeTime SupportPrimeTime Timing Reports9–13The Classic Timing Analyzer determines the clock hold slack with Equation 9–10,Equation 9–11, Equation 9–12, and Equation 9–13:Equation 9–10.Clock Hold Slack Shortest Register-to-Register Delay – Smallest Register-to-Register RequirementEquation 9–11.Smallest Register-to-Register Requirement Hold Relationship between Source & Destination Smallest Clock Skew – Micro t su of Source Micro t H of DestinationEquation 9–12.Hold Relationship between Source & Destination Latch Edge – Launch EdgeEquation 9–13.Smallest Clock Skew Longest Clock Path from Clock to Destination Register –Shortest Clock Path from Clock to Source RegisterFigure 9–5 shows a simple three-register design.Figure 9–5. Simple Three-Register DesignDecember 2010Altera CorporationQuartus II Handbook Version 11.0 Volume 3: Verification

9–14Chapter 9: Synopsys PrimeTime SupportPrimeTime Timing ReportsThe Classic Timing Analyzer generates a report as shown in Figure 9–6.Figure 9–6. Timing Analyzer Report Generated from the Three-Register DesignThe previous equations are similar to those found in the Quartus II software.Equation 9–14 through Equation 9–17 are the same equations that are used by thePrimeTime software, but they are rearranged.Equation 9–14.Slack Data Required – Data ArrivalEquation 9–15.Clock Arrival Latch Edge Longest Clock Path to DestinationEquation 9–16.Data Required Clock Arrival – Micro t HEquation 9–17.Data Arrival Launch Edge Longest Clock Path to Source Micro tco Shortest Data Delay1The shortest register-to-register delay in the previous equation is equal toregister-to-register data delay.Quartus II Handbook Version 11.0 Volume 3: VerificationDecember 2010 Altera Corporation

Chapter 9: Synopsys PrimeTime SupportPrimeTime Timing Reports9–15Figure 9–7 shows a clock setup check with the Classic Timing Analyzer.Figure 9–7. Clock Hold Check Reporting with the Classic Timing AnalyzerThe results in Equation 9–18 are obtained by extracting the numbers from the TimingAnalysis report and applying the clock setup slack equations from the Classic TimingAnalyzer.Equation 9–18.Clock Hold Slack Shortest Register-to-Register Delay – Smallest Register-to-Register Requirement3.413 – – 0.240 3.653nsSmallest Register-to-Register Requirement Hold Relationship between Source & Destination Smallest Clock Skew – Micro t co of Source Micro t H of Destination0 – 0.164 – 0.176 0.100 – 0.240nsHold Relationship between Source & Destination Latch – Launch0.0 – 0.0nsSmallest Clock Skew Longest Clock Path from Clock to Destination Register –Shortest Clock Path from Clock to Source Register3.002 – 3.166 – 0.164nsDecember 2010Altera CorporationQuartus II Handbook Version 11.0 Volume 3: Verification

9–16Chapter 9: Synopsys PrimeTime SupportPrimeTime Timing ReportsFor the same register-to-register path, the PrimeTime software generates the reportshown in Example 9–4:Example 9–4. Hold Path Report in PrimeTimeStartpoint: inst2 I.lereg(rising edge-triggered flip-flop clocked by clock)Endpoint: inst3 I.lereg(rising edge-triggered flip-flop clocked by clock)Path Group: clockPath Type: -----------------------------clock clock (rise edge)0.0000.000clock network delay (propagated)3.1663.166inst2 I.lereg.clk (stratix lcell register)0.0003.166rinst2 I.lereg.regout (stratix lcell register) - 0.176*3.342rinst2 I.regout (stratix lcell)0.000*3.342rinst3 I.datac (stratix lcell)0.000*3.342rinst3 I.lereg.datac (stratix lcell register)3.413*6.755rdata arrival time6.755clock clock (rise edge)0.0000.000clock network delay (propagated)3.0023.002in

the PrimeTime software constraints and exceptions when it generates the PrimeTime files. The converted constraints are saved to the Tcl script. The Tcl script also includes a PrimeTime software command that reads the .sdo file generated by the Quartus II software. You can place additional commands in the Tcl script to analyze or report on

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