MSC8156 AMC Base Card Detailed Design Specifications
Freescale SemiconductorTechnical DataDocument Number: MSC8156AMCBCDDSRev.0, 01/2010MSC8156 AMC Base CardDetailed Design Specification11.1OverviewScopeThis document provides a detailed design description of theAMC base card describing its architecture, interconnect, andcomponents.1.2ReferencesThe following documents are referenced for this hardwarespecifications:1. MSC8156 Reference Manual2. MSC8156 Hardware Specification3. PICMG AMC.0 R2.0 “Advanced Mezzanine CardBase Specification”4. PICMG AMC.2 “PCIe Advanced Mezzanine CardBase Specification”5. PICMG AMC.4 “SRIO Advanced Mezzanine CardBase Specification” Freescale Semiconductor, Inc., 2010. All rights reserved.Contents1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1. Scope. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11.2. References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11.3. Definitions, Acronyms, and Abbreviations . . . . . . . .22. AMC Base Card Overview . . . . . . . . . . . . . . . . . . . . . 23. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44. AMC Base Card Design Description . . . . . . . . . . . . . 64.1. SRIO Switching Environment . . . . . . . . . . . . . . . . . .64.2. Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124.3. System FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224.4. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244.5. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254.6. UART Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . .274.7. JTAG Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . .284.8. USB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294.9. Mezzanine Board Identification Pins . . . . . . . . . . . .304.10. Mezzanine High-Speed Connector Interface . . . . .314.11. Backplane Interface . . . . . . . . . . . . . . . . . . . . . . . .424.12. DIP Switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .464.13. LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .474.14. Push Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .474.15. Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . .484.16. MMC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .534.17. Boundary-Scan Testing. . . . . . . . . . . . . . . . . . . . . .564.18. Expansion Connector and Card . . . . . . . . . . . . . . .564.19. Mechanicals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .575. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
AMC Base Card Overview1.3Definitions, Acronyms, and AbbreviationsTable 1 contains definitions, acronyms, and abbreviations used in this document.Table 1. Definitions, Acronyms, and Abbreviations2AMCAdvanced Mezzanine Card (AdvancedMC )ATCAAdvanced Telecommunications Computing ArchitectureBDMBackground Debug ModeBTSBase Transceiver StationCPLDComplex Programmable Logic DeviceDIPDual In Line PackageDNPDo Not PopulateDSPDigital Signal ProcessorEEPROMElectrically Erasable Programmable Read Only MemoryFPGAField Programmable Gate ArrayGETHGiga-bit EthernetHSCHigh Speed ConnectorHWHardwareI2C(bus)Inter-Integrated CircuitLTELong-Term EvolutionMTCAMicro Telecommunications Computing Architecture ( MicroTCA )RCWReset Configuration WordSRIOSerial RapidIOUARTUniversal Asynchronous Receiver/TransmitterUECUCC Gigabit Ethernet ControllerWIMAXWorldwide Interoperability for Microwave AccessAMC Base Card OverviewThe primary goals of the AMC base card are as follows: When fitted with MSC8156, mezzanine provides a high-density MSC8156 DSP reference platformin an AMC form factor Enable rapid prototyping of MSC8156-based systems for customers, third parties, and Freescale Specific targets include BTS systems for the WIMAX and LTE applications Provide design material and collateral for customers and third parties Create a third-party handover package that can be passed on to CEMs for any required productizing Provide a generic base card for future mezzanine cards, including P2020 and its derivativesMSC8156 AMC Base Card Detailed Design Specification, Rev.02Freescale Semiconductor
AMC Base Card OverviewThe AMC base card is designed to comply with the PICMG AMC.0 R2.0 specifications with AMC.4(SRIO), fitting into a single-width, full-height mezzanine card. It provides Ethernet and SRIO switchingcapability to the mezzanines as well as general board support, such as clocks and power.The mezzanine concept is designed to be flexible and to provide system-building blocks using devices,such as MSC8156, MSC815x, MSBA1000, and P2020. This allows AMC prototyping systems to bequickly enabled.SRIO traffic is routed from the backplane ports [4:7], [8:11], [12:15], and [17:20] through 10-port IDTswitch to the three mezzanines. Each mezzanine is connected to the SRIO switch through two x4 SRIOinterfaces.To facilitate PCIe development work, a single mezzanine site has its PCIe split from SRIO and routeddirectly to the backplane port [4:7] through 2:1 differential broadband Pericom PI2DBS212multiplex/de-multiplex switch.Gigabyte Ethernet traffic is routed from the two backplane ports 0 and 1, and from the two front panelsRJ45 to three mezzanines through Vitesse VSC7384 12-port RGMII switch. The transceiver ports areconfigured for RGMII to 1000-Base-X conversion and routed to the backplane, while the remaining twoports are routed to the RJ45 front panel.The FPGA collects and distributes the remaining interfacing logic, including resets, GPIOs, IRQs, LEDs,and JTAGs.A module management controller (MMC) provides board bring up and hot swap support and sequencesthe power up of all components. The MMC runs on the 3.3-V management power (IPMCV).Figure 1 shows the AMC base card and MSC8156 mezzanine architecture.NOTEThe AMC base card and MSC8156 mezzanine are jointly referred asMSC8156 AMC.MSC8156 AMC Base Card Detailed Design Specification, Rev.0Freescale Semiconductor3
FeaturesFigure 1. AMC Base Card and MSC8156 Mezzanine Architecture (MSC8156 AMC)3FeaturesThis section summarizes features of the AMC base card. Target use— System component for BTS systems, including WIMAX and LTE applications— Software development platform for WIMAX and LTE applications— Design reference and enablement platform for customers and third parties Form factor— Single-width AMC size, full-height module Connectivity— Two SRIO (x4) interfaces from backplane, “fat pipes region,” ports [4:7] and [8:11] routed tomezzanines through SRIO switch— Two SRIO (x4) interfaces from backplane, “extended pipes region,” ports [12:15] and [17:20]routed to mezzanines through SRIO switch— One mezzanine PCIe interface routed to the backplane ports [4:7] (Assembly option)— 1000-Base-X Gigabit Ethernet from the backplane ports [0] and [1] routed to mezzaninesthrough Ethernet switch and PHY— Two Gigabit Ethernet interfaces routed to front panel through PHYMSC8156 AMC Base Card Detailed Design Specification, Rev.04Freescale Semiconductor
Features — Mezzanine UART interfaces multiplexed through the FPGA to a single mini-USB Type Bconnector on the front panel through a UART/USB transceiver— Two UART ports over a single USB cable— I2C bus connecting mezzanines for boot and configuration— Serial peripheral interface (SPI) bus connecting mezzanines for boot and configuration— USB v2.0 interface for P2020 development workHardware blocks— IDT CPS-10Q 10 port SRIO switch– Two lanes of x4 SRIO from Mezzanine 1– Two lanes of x4 SRIO from Mezzanine 2– Two lanes of x4 SRIO from Mezzanine 3– Two lanes of x4 SRIO to backplane ports [4:7]– Two lanes of x4 SRIO to backplane ports [8:11]– Two lanes of x4 SRIO to backplane ports [12:15]– Two lanes of x4 SRIO to backplane ports [17:20]— Ethernet switch– Two lanes of RGMII from Mezzanine 1– Two lanes of RGMII from Mezzanine 2– Two lanes of RGMII from Mezzanine 3– Two lanes of 1000-Base-X to backplane ports 0 and 1– Two lanes of Gigabit Ethernet to front panel RJ45 connectorsBoot— Mezzanine boot options– SRIO through backplane– Ethernet through backplane or front panel– From on-board I2C EEPROM– From on-board serial Flash through SPIDebug— All JTAGs routed through FPGA to enable full BSCAN chain during factory test— JTAG header provided for MSC8156 mezzanines— COP header provided for P2020 mezzaninesModule management controller— Hot swapping— FRU storage— Status LEDs— Temperature and voltage monitoringPower supplyMSC8156 AMC Base Card Detailed Design Specification, Rev.0Freescale Semiconductor5
AMC Base Card Design Description 4— 12 V payload and 3.3 V IPMCV, provided from AMC edge connector— 12 V barrel connector for stand-alone work— On-board voltage requirements are generated through DC–DC voltage regulatorsConnectors— Three mezzanine high-speed connectors— AMC edge connector— EONCE JTAG header— Integrated RJ45 and USB type A— Mini-USB Type B (UART)— Expansion connector to offload– FPGA programming header– MMC programming header– COP JTAG header– Two RS232 (MMC)AMC Base Card Design DescriptionThis section provides the design details of various components of AMC base card, including hardwareblocks, interfaces, and general board controls (such as switches, connectors MMC, and power).4.1SRIO Switching EnvironmentThe IDT CPS10Q switch has high-performance SRIO interface that provides connectivity for control anddata plane applications. It features ten, x4 SRIO ports running up to 3.125 GHz. Six of the ports areconnected to the mezzanine connectors and four to the AMC backplane as shown in Figure 2. Out of thefour, two ports interface to the fat pipes section of the AMC connector ports—[4:7] and [8:11], and theother two ports connect the extended options, backplane ports—[12:15] and [17:20].MSC8156 AMC Base Card Detailed Design Specification, Rev.06Freescale Semiconductor
AMC Base Card Design JTAGSRIO/PCIePCIe2:1SRIO2:1SRIO SWITCH[IDT 80KSW0005]4x4x4x4x4x4x4xHSC2SRIOx TXD0 NSRIOx TXD0 PSRIOx TXD1 NSRIOx TXD1 PSRIOx TXD2 NSRIOx TXD2 PSRIOx TXD3 NSRIOx TXD3 P100ohm diff pairPort 4:7Port 8:11Port 12:154x4x4xPort 17:204xsRIO1sRIO04xFPGAMMSPD[1:0]HSC3JTAGSRIOx RXD0 NSRIOx RXD0 PSRIOx RXD1 NSRIOx RXD1 PSRIOx RXD2 NSRIOx RXD2 PSRIOx RXD3 NSRIOx RXD3 PRESETsRIO1sRIO04x4xIRQ0.1uF at device receiver endFigure 2. SRIO ConnectivityThe mezzanine SRIO interfaces to the SRIO switch, and are all identical with the exception of SRIO1 onMezzanine connector 1. This is a multiplexed SRIO/PCIe interface that connects PCIe direct to thebackplane ports [4:7] through multiplex/de-multiplex devices. For further details, refer to Section 4.1.4,“PCIe Interface.”The port mappings shown in Figure 3 are based on the AMC port positions and the pin out of the CPS10Q.Pin 1321Ethernet &SRIO Port [17:20]9 8071 CPS10Q 6253 4Port [4:7]Port [12:15]Port [8:11]Figure 3. CPS10Q Port AllocationTable 2 shows CPS10Q port allocation.MSC8156 AMC Base Card Detailed Design Specification, Rev.0Freescale Semiconductor7
AMC Base Card Design DescriptionTable 2. CPS10Q Port AllocationPortSignal (Net name)End PointCPS10QSignal NameCPS10QIO0M2 SRIO0 TXD[0:3] PM2 SRIO0 TXD[0:3] NMezzanine 2SRIO0RX[0:3] RX[0:3]I0.1 μFat CPS10QpinsTX[0:3] TX[0:3]-OOn mezzanineRX[4:7] RX[4:7]-I0.1 μF at CPS10QpinsTX[4:7] TX[4:7]-OOn mezzanineRX[8:11] RX[8:11]-I0.1 μF at CPS10QpinsTX[8:11] TX[8:11]-OOn mezzanineRX[12:15] RX[12:15]-I0.1 μF at CPS10QpinsTX[12:15] TX[12:15]-OOn mezzanineBackplaneSRIO1Ports [8:11]RX[16:19] RX[16:19]-I0.1 μF at CPS10QpinsTX[16:19] TX[16:19]-ODirect connection toAMC edge connectorBackplaneSRIO2Ports[12:15]RX[20:23] RX[20:23]-I0.1 μF at CPS10QpinsTX[20:23] TX[20:23]-ODirect connection toAMC edge connectorBackplaneSRIO0Ports[4:7]RX[16:19] RX[16:19]-I0.1 μF at CPS10QpinsTX[16:19] TX[16:19]-OConnection to AMCedge connector bymultiplexingBackplaneSRIO3Ports[17:20]RX[28:31] RX[28:31]-I0.1 μF at CPS10QpinsTX[28:31] TX[28:31]-ODirect connection toAMC edge connectorMezzanine 1SRIO0RX[32:35] RX[32:35]-I0.1 μF at CPS10QpinsTX[32:35] TX[32:35]-OOn mezzanineM2 SRIO0 RXD[0:3] PM2 SRIO0 RXD[0:3] N1M2 SRIO1 TXD[0:3] PM2 SRIO1 TXD[0:3] NMezzanine 2SRIO1M2 SRIO1 RXD[0:3] PM2 SRIO1 RXD[0:3] N2M3 SRIO0 TXD[0:3] PM3 SRIO0 TXD[0:3] NMezzanine 3SRIO0M3 SRIO0 RXD[0:3] PM3 SRIO0 RXD[0:3] N3M3 SRIO1 TXD[0:3] PM3 SRIO1 TXD[0:3] NMezzanine 3SRIO1M3 SRIO1 RXD[0:3] PM3 SRIO1 RXD[0:3] N4AMC SRIO1 TXD[0:3] PAMC SRIO1 TXD[0:3] NAMC SRIO1 RXD[0:3] PAMC SRIO1 RXD[0:3] N5AMC SRIO2 TXD[0:3] PAMC SRIO2 TXD[0:3] NAMC SRIO2 RXD[0:3] PAMC SRIO2 RXD[0:3] N6AMC SRIO0 TXD[0:3] PAMC SRIO0 TXD[0:3] NAMC SRIO0 RXD[0:3] PAMC SRIO0 RXD[0:3] N7AMC SRIO3 TXD[0:3] PAMC SRIO3 TXD[0:3] NAMC SRIO3 RXD[0:3] PAMC SRIO3 RXD[0:3] N8M1 SRIO0 TXD[0:3] PM1 SRIO0 TXD[0:3] NM1 SRIO0 RXD[0:3] PM1 SRIO0 RXD[0:3] NDC blocking capMSC8156 AMC Base Card Detailed Design Specification, Rev.08Freescale Semiconductor
AMC Base Card Design DescriptionTable 2. CPS10Q Port Allocation (continued)PortSignal (Net name)End PointCPS10QSignal NameCPS10QIO9M1 SRIO1 TXD[0:3] PM1 SRIO1 TXD[0:3] NMezzanine 1SRIO1RX[36:39] RX[36:39]-I0.1 μF at CPS10QpinsTX[36:39] TX[36:39]-OOn mezzanineM1 SRIO1 RXD[0:3] PM1 SRIO1 RXD[0:3] N4.1.1DC blocking capCPS10Q ConfigurationThe CPS10Q can be programmed through two different interfaces: In band through CPU/ DSP attached to one of the SRIO ports Out of band through either the I2C or JTAGTypically, a CPU/DSP attached to an SRIO port is used for configuration. However, the option also existsto configure the device through I2C configuration memory, enabling the user to run the CPS10Q in remotestand-alone mode.The JTAG interface of CPS10Q can be used for BSCAN and JTAG tools access. The JTAG interface isconnected to the FPGA, where it can be configured for BSCAN testing or routed to one of the existingon-board headers (COP or EONCE) for debugging.A number of configuration pins are sampled on power-up. These pins are controlled directly by the FPGA.Table 3 lists the configuration settings for the CPS10Q.Table 3. CPS10Q ConfigurationSignal NameIODescriptionConfigurationADSIPull down through 1 KΩ to 0 V for 7-bit addressingmodeDNC—ID[9:7]ID[6:0]INot used tie to GND. (7-bit addressing only)Set I2C EEPROM address ID[6:0] to 0010 010(Note ID pull ups to 1.2 V through 10 KΩ)MMIConnect to FPGA1 Master mode; boot from I2C0 Slave mode ; default configuration valuesSPD[1:0]IConnect to FPGA. Sets port frequency00 1.25 GGHz01 3.125 GHz10 2.5 GHz11 illegalIConnect to FPGA, pull up through 10 KΩ to 3.3 VDo not connect (leave floating)ResetRSTMSC8156 AMC Base Card Detailed Design Specification, Rev.0Freescale Semiconductor9
AMC Base Card Design DescriptionTable 3. CPS10Q Configuration (continued)Signal NameIODescriptionI2CBBConnects to EEPROM through I2C bus(Address 0x52)IRQOConnect to FPGA, pull up through 10 KΩ to 3.3 VTCKTDITDOTMSTRSTIIOIIConnect JTAG to FPGASCLSDAInterruptJTAG4.1.2TerminationThe SRIO interface have a 0.1-μF DC blocking capacitor placed at the CPS10Q receiver end.4.1.3ClockingThe CPS10Q runs on a fixed-clock frequency of 156.25 MHz, enabling it to run at 3.125, 2.5, and1.25 GHz. The low-jitter Vectron VCC6-L/V is used to drive the CPS10Q clocks. The LVDS to CMLtermination scheme uses a 2-KΩ resistor and 0.1-μF AC decoupling, as shown in Figure 4.CPS10Q0.1uFSRIO REF CLK P156.25MHzoscillator2KREF CLK PSRIO REF CLK NREF CLK N0.1uF[LVDS- CML Interface]Figure 4. CPS10Q Clock SchemeFor Mezzanine 1, SRIO1 clock uses a multiplexed PCIe/SRIO clock system. For SRIO, a125-MHz VCC6-L/V clock is switched through the ICS854054 multiplexer. For PCIe, there are twomultiplexing options: a dedicated 100-MHz VCC6-L/V or an external PCIe clock from the backplane(Fabric Clock A). Two select signals control the multiplexing option and are controlled from the FPGA.The remaining five clocks are generated from 125-MHz VCC6-L/V oscillator that are distributed to themezzanines through ICS854S006I fan out buffer.MSC8156 AMC Base Card Detailed Design Specification, Rev.010Freescale Semiconductor
AMC Base Card Design DescriptionFigure 5. SERDES to Mezzanine Clocking4.1.4PCIe InterfaceMezzanine position 1 has a multiplexed SRIO1/PCIe interface. This enables both SRIO and PCIe toconnect directly to the backplane port [4:7]. The PCIe signals have been splitted using PericomPI2DBS412 differential signal multiplex/de-multiplex devices, bypassing the SRIO switch.Table 4 describes the PCI and SRIO multiplexed signals.Table 4. PCI and SRIO Multiplexed SignalsSignalIOMultiplexed withPE TXD0 POSRIO1 TXD0 PPE TXD0 NOSRIO1 TXD0 NPE TXD1 POSRIO1 TXD1 PPE TXD1 NOSRIO1 TXD1 NPE TXD2 POSRIO1 TXD2 PPE TXD2 NOSRIO1 TXD2 NPE TXD3 POSRIO1 TXD3 PMSC8156 AMC Base Card Detailed Design Specification, Rev.0Freescale Semiconductor11
AMC Base Card Design DescriptionTable 4. PCI and SRIO Multiplexed Signals (continued)SignalIOMultiplexed withPE TXD3 NOSRIO1 TXD3 NPE RXD0 PISRIO1 RXD0 PPE RXD0 NISRIO1 RXD0 NPE RXD1 PISRIO1 RXD1 PPE RXD1 NISRIO1 RXD1 NPE RXD2 PISRIO1 RXD2 PPE RXD2 NISRIO1 RXD2 NPE RXD3 PISRIO1 RXD3 PPE RXD3 NISRIO1 RXD3 NFigure 6 details the multiplex/de-multiplex configuration. It shows the logical split, as in the design RXand TX; pairs have been moved between Pericom devices to ease routing. The select signal from eachmultiplexer is tied together and connected to the FPGA for static control.AMCConnectorHSC1PCIE TXD[0:3]pPCIE TXD[0:3]nSRIO1 TXD[0:3]p /PCIE TXD[0:3]pSRIO1 TXD[0:3]n /PCIE TXD[0:3]nAMC SRIO0 TXD[0:3]p PCIe TXD[0:3]pPI2DBS412SRIO1 TXD[0:3]pSRIO1 TXD[0:3]nCPS10QSRIO SwitchAMC SRIO0 TX[0:3]pAMC SRIO0 TX[0:3]nPI2DBS412 AMC SRIO0 TXD[0:3]n /PCIe TXD[0:3]nMux SelMux SelSRIO1 RXD[0:3]pSRIO1 RXD[0:3]p / PCIE RXD[0:3]pSRIO1 RXD[0:3]n / PCIE RXD[0:3]nAMC SRIO0 RXD[0:3]pAMC SRIO0 RXD[0:3]nSRIO1 RXD[0:3]nPI2DBS412AMC SRIO0 RXD[0:3]p/PCIE RXD[0:3]pPI2DBS412AMC SRIO0 RXD[0:3]n/PCIE RXD[0:3]nPCIE RXD[0:3]pPCIE RXD[0:3]nMux SelMux SelFigure 6. PCIe/SRIO Multiplexed Routing4.24.2.1EthernetVSC7384 Ethernet SwitchThe Ethernet subsystem switches Ethernet among the mezzanine tiles, AMC backplane ports, and frontpanel RJ45. A Vitesse VSC7384 12-port RGMII Ethernet switch provides the switching fabric. In total, itswitches 10 Ethernet sources as shown in Figure 7.MSC8156 AMC Base Card Detailed Design Specification, Rev.012Freescale Semiconductor
AMC Base Card Design DescriptionFigure 7. Ethernet ConnectivityFigure 8 shows the interface between the MSC8156 and VSC7384 switch. The transmit signals from theMSC8156 mezzanine have source termination resistors, while the VS7384 transmit signals use VSC7384device internal termination. For clocking, a 125-MHz oscillator feeds an ICS552 buffer that distributes asingle clock to the Ethernet switch and two clocks to each of the mezzanines.MSC8156 AMC Base Card Detailed Design Specification, Rev.0Freescale Semiconductor13
AMC Base Card Design DescriptionMSC8156 #1125MHzGE1GE1 TX CLK125MHzRGMII RX CLKRGMII RX CTRLRGMII RD[0:3]GE1 GTX CLKGE1 TX CTLGE1 TXD[0:3]RGMII TX CTRLGE1 RX CTLGE1 RX CLKGE1 RXD[0:3]RGMII TX CLKRGMII TD[0:3]VSC7384Ethernet SwitchGE2125MHzGE2 TX CLKRGMII RX CLKRGMII RX CTRLRGMII RD[0:3]GE2 GTX CLKGE2 TX CTLGE2 TXD[0:3]RGMII TX CTRLGE2 RX CTLGE2 RX CLKGE2 RXD[0:3]RGMII TX CLKRGMII TD[0:3]MSC8156 #2125MHzGE1GE1 TX CLKGE1 GTX CLKGE1 TX CTLGE1 TXD[0:3]RGMII RX CLKRGMII RX CTRLRGMII RD[0:3]RGMII TX CTRLGE1 RX CTLGE1 RX CLKGE1 RXD[0:3]RGMII TX CLKRGMII TD[0:3]Figure 8. RGMII Interface to MSC81564.2.2Ethernet RGMII Clock DelaysThe RGMII specification requires the signal clock to be delayed by 1.5–2 ns at the receiving end of thedata path. This clock delay can be added externally (extending clock trace length) or by using internaldelays built into the device. The MSC8156 tap value can be selected by the user through the GCR4 register.The default GCR4 value which is initially set in ROM code differs between MSC8156 Rev. 1 silicon (usedin Prototype MSC8156 AMC) and MSC8156 Rev. 2 silicon (used in Pilot MSC8156).The GE1 track lengths differ on the AMC base card versions to accommodate boot over Ethernet that usesthe default GCR4. Note that DSP2 GE1 has been changed to accommodate both MSC8156 and QoreIQmezzanines.MSC8156 AMC Base Card Detailed Design Specification, Rev.014Freescale Semiconductor
AMC Base Card Design DescriptionTable 5. MSC8156 RGMII Delay [Prototype Build]Mezzanine4.2.3AMC Base Card - PrototypeAMC Base Card - PilotRX Clock Delay(ns)TX Clock Delay(ns)RX Clock Delay(ns)TX Clock Delay(ns)DSP1 GE11.61.600DSP1 GE21.61.600DSP2 GE11.61.600DSP2 GE20000DSP3 GE11.61.600DSP3 GE20000VSC7384 Ethernet Switch ConfigurationOn power up, the Ethernet switch is configured over its SPI bus through the FPGA. The FPGA alsocontrols the switches reset and GPIO0 signals. For BSCAN purposes, the JTAG interface is connected tothe FPGA for distribution.The Ethernet switch configures the VSC8224 transceiver through the management interface. The MDIOsignal is pulled to 3.3 V through 1.5 KΩ resistor, while the MDC signal drives the clock through 33 Ωsource termination.MDIOMDCMDIO PortMDIO PortLED RJ45SPI MOSISPI MISOSPI CLKSPI SELn2VSC82242ResetGPIO0JTAGFPGALED RJ45RJ45RJ4525MHzoscVSC738422LED PORT0LED PORT1ResetinterruptJTAGLEDBankFigure 9. Ethernet ConfigurationTable 6 and Table 7 summarize the port mapping and the complete interconnect interface on the VSC7384.MSC8156 AMC Base Card Detailed Design Specification, Rev.0Freescale Semiconductor15
AMC Base Card Design DescriptionTable 6. VSC7384 Port MappingVSC7384 PortInterconnect InterfaceTarget0RGMIIMezzanine 1 (1)1RGMIIMezzanine 1 (2)2RGMIIMezzanine 2 (1)3RGMIIMezzanine 2 (2)4RGMIIMezzanine 3 (1)5RGMIIMezzanine 3 (2)6RGMIIVSC8224 Transceiver [Port 0]7RGMIIVSC8224 Transceiver [Port 1]8RGMIIVSC8224 Transceiver [Port 2]9RGMIIVSC8224 Transceiver [Port 3]10Not used—11Not used—Table 7. VSC7384 InterconnectSignalIODescriptionClock InterfaceCLKIConnects to 125-MHz clockCLK125 ENIEnable 125-MHz clock, pulled up through 10 KΩ to 3.3 VPLL ENIInternal test, pulled up through 10 KΩ to 3.3 VPLL CAP0PLL CAP1A100-nF capacitor connected between pinsIIIOOO4222IIIOIConnected direct to FPGARGMII PortsRGMII n RD[3:0]RGMII n RX CLKRGMII n RX CTLRGMII n TD[3:0]RGMII n GTX CLKRGMII n TX CTLRGMII Interfaces connected to Ethernet TransceiverRGMII Interfaces connected to Mezzanine 1RGMII Interfaces connected to Mezzanine 2RGMII interfaces connected to Mezzanine 3JTAGTRSTTCKTDITDOTMSICPU/PI External Memory Interface (neither used)MSC8156 AMC Base Card Detailed Design Specification, Rev.016Freescale Semiconductor
AMC Base Card Design DescriptionTable 7. VSC7384 Interconnect (continued)SignalIODescriptionPI Addr[0:15]PI Data[0:15]PI nCSPI nOEPI nWRIBIIIPulled up through single 10 KΩ to 3.3 VPI nDoneOPulled up through 10 KΩ to 3.3 VPI IRQOPulled up through 10 KΩ to 3.3 VICPU ENISelect PI (Note: Both PI and ICPU interfaces are notused.)Pulled down through 100 Ω and connected to FPGASI CLKIConnect to FPGA, pull up through10 KΩ to 3.3 VSI DIIConnect to FPGA, pull up through10 KΩ to 3.3 VSI DOOConnect to FPGA, pull up through10 KΩ to 3.3 VSI nEnIPull down to 0 V through 1 KΩ to enable SI, andconnected to FPGAMDIOBConnected to Ethernet TransceiverMDCOConnected to Ethernet TransceiverGPIO0GPIO[1:4]BConnected direct to FPGANot used, pulled low to 0VnResetIConnected to FPGA, pulled up through 10 KΩ to 3.3 VTest Enable0Pulled low to 0 VSI InterfaceManagement InterfaceGPIOsMiscellaneous4.2.4VSC8224 Ethernet TransceiverA Vitesse VSC8224 quad-port transceiver is used to switch from RGMII to 1000-Base-X on the backplaneport [0:1], and from RGMII to twisted pair/RJ45 on the front panel. The RJ45 contains integratedmagnetics with two indicator LEDs.The two 1000-Base-X port LED control signals—LED[0] and LED[2]—are connected directly to theFPGA, where they can be distributed to the FPGA’s LED bank. These can be configured to provide a rangeof Ethernet activity information, such as link, RX, and TX . During normal operations, each port registersactivity on a single LED.MSC8156 AMC Base Card Detailed Design Specification, Rev.0Freescale Semiconductor17
AMC Base Card Design Description4.2.5VSC8224 Ethernet Transceiver ConfigurationOn power up, the VSC8224 is configured through the CMODE pins. This configures a subset of the MIIregisters within the device. The register block can also be programmed through the management interfacethat connects to the Ethernet switch.Reset control is from the FPGA that also collects the JTAG interface for BSCAN purposes. Theconfiguration of the device is described in Table 8.Table 8. VSC8224 InterconnectSignal NameIODescriptionRGMII InterfaceTXD[3:0] 0TXCTL 0TX CLK 0RXD[3:0] 0RX CLK 0RX CTL 0IIIOOOConnected to Ethernet switch. The output signals have an internal 50 seriesterminationTXD[3:0] 1TXCTL 1TX CLK 1RXD[3:0] 1RX CLK 1RX CTL 1IIIOOOConnected to Ethernet switch. The output signals have an internal 50 seriesterminationTXD[3:0] 2TXCTL 2TX CLK 2RXD[3:0] 2RX CLK 2RX CTL 2IIIOOOConnected to Ethernet switch. The output signals have an internal 50 seriesterminationTXD[3:0] 3TXCTL 3TX CLK 3RXD[3:0] 3RX CLK 3RX CTL 3IIIOOOConnected to Ethernet switch. The output signals have an internal 50 seriesterminationTDN 0TDP 0RDN 0RDP 0IIOOConnected to backplane Port 0TDN 1TDP 1RDN 1RDP 1IIOOConnected to backplane Port 1SIGDET0SIGDET1IPulled up through 10 KΩSerDes InterfaceMSC8156 AMC Base Card Detailed Design Specification, Rev.018Freescale Semiconductor
AMC Base Card Design DescriptionTable 8. VSC8224 Interconnect (continued)Signal NameIODescriptionTDN 2TDP 2RDN 2RDP 2IIOOPins are not used (n/c)TDN 3TDP 3RDN 3RDP 3IIOOPins are not used (n/c)SIGDET2SIGDET3IPulled down through 100 ΩTwisted Pair 2TXVND2AAAAAAAAConnect to front panel RJ45 with integrated 3TXVND3AAAAAAAAConnect to front panel RJ45 with integrated magneticsManagement InterfaceMDCMDIOIODConnects to Ethernet switchMDINT[0:3]OConnected together and connected to the FPGA; pulled up through 10 KΩ to 3.3 VBBLeft floating to indicate no EEPROMPulled low for 25-MHz input clockEEPROM InterfaceEEDATEECLKConfiguration and Control Pins (Pull Up through 10KΩ to 3.3V)CMODE7Ib0001, pull down through 2.26 KΩ to 0 VCMODE6Ib0010, pull down through 4.02 KΩ to 0 VCMODE5Ib1001, pull up through 2.26 KΩ to 3.3 VCMODE4Ib0000, pull down to 0 VCMODE3Ib0100, pull down through 8.25 KΩ to 0 VCMODE2Ib0010, pull down through 4.02 KΩ to 0 VMSC8156 AMC Base Card Detailed Design Specification, Rev.0Freescale Semiconductor19
AMC Base Card Design DescriptionTable 8. VSC8224 Interconnect (continued)Signal NameIODescriptionCMODE1Ib0100, pull down through 8.25 KΩ to 0 VCMODE0Ib0100, pull down through 8.25 KΩ to 0 VRESETnIConnect to FPGA, pull up through 10 KΩ to 3.3 VSOFT RESETnIConnect to FPGA, pull up through 10 KΩ to 3.3 VSystem Clock InterfaceCLK125macONot used, no connectOSCEN/CLK125ILeave floating to enable 25-MHz oscillator useXTAL1XTAL2IConnect to 25-MHz oscillator using XTAL1XTAL2 can be left floatingLED[4:3,1] 0LED[4:3,1] 1LED[4:3,1] 2LED[4:3,1] 3ONot used, not connectedLED[2,0] 0LED[2,0] 1LED[2,0[ 2LED[2:0] 3OConnect Port 0 (1000-Base-X) LED[2], LED[0] to FPGAConnect Port 1 (1000-Base-X) LED[2], LED[0] to FPGAConnect Port 2 (1000-Base-T) LED[2], LED[0] to RJ45 LEDsConnect Port 3 (1000-Base-T) LED[2], LED[0] to RJ45 LEDsIOIIIConnect JTAG signals direct to FPGAREF REXTAConnect to external 2 KΩ (1%) resistor to groundREF FILTAConnect to external 1 μF ( 10%) capacitor to analogue groundTXREF[3:0]VrefTie to GND (for 2.5 V/3.3 V operation)MICROREFVrefTie to GND (for 2.5 V/3.3 Voperation)LED InterfaceJTAGTDITDOTMSTCKTRSTAnalogue Bias PinsThe eight CMODE hardware configuration pins configure the VSC8224 at power up. The CMODE pinsare set by connecting the CMODE pins to either 3.3 V or GND through an external 1% resistor. Table 9describes the various options that enable a single pin to represent a 4-bit value and give up to 32 options.MSC8156 AMC Base Card Detailed Design Specification, Rev.020Freescale Semiconductor
AMC Base Card Design DescriptionTable 9. CMODE Pin CombinationsCMODE{3:0}CMODE Resistor ValueTied to 0 V or 3.3 V00000Ω0V00012.26 kΩ0V00104.02 kΩ0V00115.90 kΩ0V01008.25 kΩ0V010112.1 kΩ0V011016.9kΩ0V011122.6 kΩ0V10000Ω3.3 V10012.26 kΩ3.3 V10104.02 kΩ3.3 V10115.90 kΩ3.3 V11008.25 kΩ3.3 V110112.1 kΩ3.3 V111016.9 kΩ3.3 V111122.6 kΩ3.3 VThe hardware configuration variables that can be changed are described in Table 10, while the actualsettings used are described in Table 11.Table 10. CMODE Hardware Configuration BitsCMODE PinBit [3]Bit [2]Bit[1]Bit[0]Encoding7RGMII Clock Skew[1]SIGDET pin directionActiPHYLink SpeedDownshift00016RGMII Clock Skew[0]Remote Fault Control [1]LED Combinelink/actLED PulseStretch Blink00105PHY Address [4]Remote Fault Control [2]LED Combine LED CombineLinkCOL/DUP10/100/1000/Act10014PHY Address [3]Speed/Dup Mode [0]LED4[1]LED4[0]00003PHY Address [2]Speed/Dup Mode [1]LED3[1]LED3[0]01002MAC Interface [3]0LED2[1]LED2[0]00101MAC Interface [2]Pause Control [1]LED1[1]LED1[0]01000MAC Interface [1]Pause Control [2]LED0[1]LED0[0]0100MSC8156 AMC Base Card Detailed Design Specification, Rev.0Freescale Semiconductor21
AMC Base Card Design DescriptionTable 11. CMODE Configuration SettingsNameValueDescriptionMAC Interface000RGMII with AutoCAT5/Serial Media SensePHY Address [4:2]100Address b100xxb10000 Port 0b10001 Port 1b10010 Port 2b10011 Port 3ActiPHY0Disable Power [1:0]00 (not used)00 (not used)1000 (not used)00LED 0 Link1000/ActivityLED 2 Link Activity(LEDs 0 and 2 are used as they can be configured for RX and TX as adebug aid.)LED Pulse Stretch/Blink0Collision, Activity, RX and TX output bl
MSC8156 AMC Base Card Detailed Design Specification, Rev.0 Freescale Semiconductor 3 AMC Base Card Overview The AMC base card is designed to comply with the PICMG AMC.0 R2.0 specifications with AMC
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