The MIPS Instruction Set
The University of Adelaide, School of Computer Science17 January 2011The MIPS Instruction Setn n Used as the example throughout the bookLarge share of embedded core marketbut dwarfed by ARMn n Typical of many modern ISAsSee MIPS Reference Data tear-out card, andAppendixes B and ECSE 420Chapter 2 — Instructions: Language of the Computer — 3n Add and subtract have three operandsn n n Two sources and one destinationadd a, b, c # a gets b cAll MIPS arithmetic ops have this formDesign Principle 1:Simplicity favors regularity.n n §2.2 Operations of the Computer HardwareArithmetic OperationsRegularity makes implementation simplerRegularity enables higher performanceat lower costCSE 420Chapter 2 — Instructions: Language of the Computer — 4
The University of Adelaide, School of Computer Sciencen n Arithmetic instructions use register operandsMIPS has a 32 32-bit register filen n n Assembler namesn n n Used for frequently accessed dataNumbered 0 to 31 t0, t1, , t9 for temporary values s0, s1, , s7 for saved variablesDesign Principle 2:Smaller is faster.CSE 420§2.3 Operands of the Computer HardwareRegister Operands17 January 2011Chapter 2 — Instructions: Language of the Computer — 7Register Operand Examplen C code:f (g h) - (i j);n Register assignment?n f in s0, g in s1, h in s2, i in s3, j in s4n Temps?n Compiled MIPS code:add t0, s1, s2add t1, s3, s4sub s0, t0, t1CSE 420Chapter 2 — Instructions: Language of the Computer — 8
The University of Adelaide, School of Computer Science17 January 2011Load-Store Architecturen Data is in memoryn n n Load values from memory into registersStore result from register to memoryDetails:n Memory is byte addressedn Words are aligned in memoryn n n Each address identifies an 8-bit byteWord addresses must be a multiple of 4MIPS is Big Endiann n Most-significant byte at least address of a wordc.f. Little Endian: least-significant byte at least addressCSE 420Chapter 2 — Instructions: Language of the Computer — 9Memory Operand Example 1n C code:g h A[8];n g in s1, h in s2, base address of A in s3n Compiled MIPS code:n Index 8 requires offset of 32Why?lw t0, 32( s3)add s1, s2, t0offsetCSE 420# load wordbase registerChapter 2 — Instructions: Language of the Computer — 10
The University of Adelaide, School of Computer ScienceMemory Operand Example 2n C code:A[12] h A[8];n h in s2, base address of A in s3n Compiled MIPS code:Index 8 requires offset of 32n Index 12 requires offset of ?lw t0, 32( s3)# load wordadd t0, s2, t0sw t0, 48( s3)# store wordn CSE 420Chapter 2 — Instructions: Language of the Computer — 11Registers vs. Memoryn n n Registers are faster than memoryLoad-store è “more” instructions to be executedRegister optimization is important!CSE 420Chapter 2 — Instructions: Language of the Computer — 1217 January 2011
The University of Adelaide, School of Computer ScienceImmediate Operandsn Constant data specified in an instructionaddi s3, s3, 4n There is no “subtract immediate” instructionn Subtract is “add a negative”addi s2, s1, -4n Design Principle 3:Make the common case fast.n n n Small constants are commonImmediate operand avoids a load instructionWhy?CSE 420Chapter 2 — Instructions: Language of the Computer — 13The Constant Zeron MIPS register 0 ( zero) is the constant 0n n Useful for common operationsn n Cannot be overwrittene.g., move between registersadd t2, s1, zeroWhy a fixed register zero?CSE 420Chapter 2 — Instructions: Language of the Computer — 1417 January 2011
The University of Adelaide, School of Computer Science17 January 2011Sign Extensionn n How do yourepresent a number using more bits?e.g. move an 8-bit number into a 16-bit wordReplicate the sign bit to the leftn n Examples: 8-bit to 16-bitn n n c.f. unsigned values: extend with 0s 2: 0000 0010 0000 0000 0000 0010–2: 1111 1110 1111 1111 1111 1110In MIPS instruction setn n n addi: extend immediate valuelb, lh: extend loaded byte/halfwordbeq, bne: extend the displacementCSE 420Chapter 2 — Instructions: Language of the Computer — 19n Instructions are encoded in binaryn n MIPS instructionsn n n Called “machine code”Encoded as 32-bit instruction words (Regularity!)Small number of formats encodeopcode, register numbers, Register numbersn n n n t0 – t7 are reg’s 8 – 15 s0 – s7 are reg’s 16 – 23 t8 – t9 are reg’s 24 – 25(0-8 and 25-31 described later – procedure calls)CSE 420§2.5 Representing Instructions in the ComputerRepresenting InstructionsChapter 2 — Instructions: Language of the Computer — 20
The University of Adelaide, School of Computer Science17 January 2011MIPS R-format Instructionsn oprsrtrdshamtfunct6 bits5 bits5 bits5 bits5 bits6 bitsInstruction fieldsn n n n n n op: operation code (opcode)rs: first source register numberrt: second source register numberrd: destination register numbershamt: shift amount (00000 for now)funct: function code (extends opcode) (Why?)CSE 420Chapter 2 — Instructions: Language of the Computer — 21R-format Exampleoprsrtrdshamtfunct6 bits5 bits5 bits5 bits5 bits6 bitsadd t0, s1, s2special s1 s2 000100011001001000000001000002 0232402016CSE 420Chapter 2 — Instructions: Language of the Computer — 22
The University of Adelaide, School of Computer Science17 January 2011Hexadecimaln Base 16n n Compact representation of bit strings4 bits per hex digit0123n 101011cdef1100110111101111Example: eca8 6420n 1110 1100 1010 1000 0110 0100 0010 0000CSE 420Chapter 2 — Instructions: Language of the Computer — 23MIPS I-format Instructionsn rsrtconstant or address6 bits5 bits5 bits16 bitsImmediate arithmetic and load/store instructionsn n n n oprt: destination or source register numberConstant: –215 to 215 – 1Address: offset added to base address in rsDesign Principle 4:Good design demands good compromises.n n Different formats complicate decoding,but allow 32-bit instruction uniformityKeep formats as similar as possibleCSE 420Chapter 2 — Instructions: Language of the Computer — 24
The University of Adelaide, School of Computer Science17 January 2011Stored Program ComputersThe BIG Picturen n n Instructions represented inbinary, just like dataInstructions and datastored in memoryPrograms canoperate on programsn n CSE 420e.g., compilers, linkers, Binary compatibility allowscompiled programs to workon other computers with thesame ISA.Chapter 2 — Instructions: Language of the Computer — 25n n Instructions for bitwise manipulationOperationCJavaMIPSShift left sllShift right srlBitwise AND&&and, andiBitwise OR or, oriBitwise NOT nor§2.6 Logical OperationsLogical OperationsUseful for extracting and insertinggroups of bits in a wordCSE 420Chapter 2 — Instructions: Language of the Computer — 26
The University of Adelaide, School of Computer Science17 January 2011Branch Addressingn Branch instructions specifyn n Opcode, two registers, target addressMost branch targets are near branchn Forward or backwardoprsrtconstant or address6 bits5 bits5 bits16 bitsPC-relative addressingn n n Target address PC offset 4PC already incremented by 4 by this timeCSE 420Chapter 2 — Instructions: Language of the Computer — 53Jump Addressingn Jump (j and jal) targets could beanywhere in text segmentn n Encode full address in instructionopaddress6 bits26 bits(Pseudo)Direct jump addressingn Target address PC31 28 : (address 4)CSE 420Chapter 2 — Instructions: Language of the Computer — 54
Morgan Kaufmann Publishers26 January 2011Chapter 4The Processor§4.1 IntroductionIntroductionn CPU performance factorsn Instruction countn n CPI and Cycle timen n Determined by CPU hardwareWe will examine two MIPS implementationsn n n Determined by ISA and compilerA simplified versionA more realistic pipelined versionSimple subset, shows most aspectsn n n Memory reference: lw, swArithmetic/logical: add, sub, and, or, sltControl transfer: beq, jCSE 420Chapter 4 — The Processor — 2
Morgan Kaufmann Publishers26 January 2011Instruction Executionn n n PC instruction memory, fetch instructionRegister numbers register file, read registersDepending on instruction classn Use ALU to calculaten n n n n Arithmetic resultMemory address for load/storeBranch target addressAccess data memory for load/storePC target address or PC 4CSE 420Chapter 4 — The Processor — 3CPU OverviewCSE 420Chapter 4 — The Processor — 4
Morgan Kaufmann Publishers26 January 2011Multiplexersn Can’t just joinwires togethern CSE 420Use multiplexersChapter 4 — The Processor — 5ControlCSE 420Chapter 4 — The Processor — 6
Morgan Kaufmann Publishers26 January 2011Clocking Methodologyn Combinational logictransforms data during clock cyclesn n n Between clock edgesInput from state elements,output to state elementLongest delay determines clock periodCSE 420Chapter 4 — The Processor — 11n Datapathn Elements that process data and addressesin the CPUn n §4.3 Building a DatapathBuilding a DatapathRegisters, ALUs, mux’s, memories, We will build a MIPS datapathincrementallyn Refining the overview designCSE 420Chapter 4 — The Processor — 12
Morgan Kaufmann Publishers26 January 2011Instruction FetchIncrement by4 for nextinstruction32-bitregisterCSE 420Chapter 4 — The Processor — 13R-Format Instructionsn n n Read two register operandsPerform arithmetic/logical operationWrite register resultCSE 420Chapter 4 — The Processor — 14
Morgan Kaufmann Publishers26 January 2011Load/Store Instructionsn n Read register operandsCalculate address using 16-bit offsetn n n Use ALU, but sign-extend offsetLoad: Read memory and update registerStore: Write register value to memoryCSE 420Chapter 4 — The Processor — 15Branch Instructionsn n Read register operandsCompare operandsn n Use ALU, subtract and check Zero outputCalculate target addressn n n Sign-extend displacementShift left 2 places (word displacement)Add to PC 4n CSE 420Already calculated by instruction fetchChapter 4 — The Processor — 16
Morgan Kaufmann Publishers26 January 2011Branch InstructionsJustre-routeswiresSign-bit wirereplicatedCSE 420Chapter 4 — The Processor — 17Composing the Elementsn First-cut data pathdoes an instruction in one clock cyclen n n Each data-path elementcan only do one function at a timeHence, we needseparate instruction and data memoriesUse multiplexers where alternate datasources are used for different instructionsCSE 420Chapter 4 — The Processor — 18
Morgan Kaufmann Publishers26 January 2011R-Type/Load/Store DatapathCSE 420Full Data PathChapter 4 — The Processor — 19
Morgan Kaufmann Publishers26 January 2011§4.4 A Simple Implementation SchemeALU Controln ALU used forn n n Load/Store: F addBranch: F subtractR-type: F depends on funct fieldALU 1set-on-less-than1100NORCSE 420Chapter 4 — The Processor — 21ALU Controln Assume 2-bit ALUOp derived from opcoden Combinational logic derives ALU controlopcodeALUOpOperationfunctlw00load wordXXXXXXadd0010sw00store wordXXXXXXadd0010beq01branch 001set-on-less-than101010set-on-less-than0111CSE 420ALU functionALU controlChapter 4 — The Processor — 22
Morgan Kaufmann Publishers26 January 2011The Main Control Unitn Control signals derived from 31:2625:2120:1615:1110:65:035 or 5:2120:1615:0opcodealwaysreadCSE 420Data Path With Controlread,exceptfor loadwrite forR-typeand loadsign-extendand addChapter 4 — The Processor — 23
Morgan Kaufmann Publishers26 January 2011n Pipelined laundry: overlapping executionn n Parallelism improves performanceFour stages: Wash – Dry – Fold - Hangn Four loads:n n Speedup 8/3.5 2.3Non-stop:n CSE 420§4.5 An Overview of PipeliningPipelining AnalogySpeedup 2n/(0.5n 1.5) 4 number of stagesChapter 4 — The Processor — 31MIPS Pipelinen Five stages, one step per stage1.2.3.4.5.CSE 420IF: Instruction fetch from memoryID: Instruction decode & register readEX: Execute operation or calculate addressMEM: Access memory operandWB: Write result back to registerChapter 4 — The Processor — 32
Morgan Kaufmann Publishers26 January 2011Hazardsn n Situations that prevent starting the nextinstruction in the next cycleStructural hazardn n Data hazardn n A required resource is busyNeed to wait for previous instructionto complete its data read/writeControl hazardn Deciding on control actiondepends on previous instructionCSE 420Chapter 4 — The Processor — 37Structure Hazardsn n Conflict for use of a resourceIn MIPS pipeline with a single memoryn n Load/store requires data accessInstruction fetch would have to stallfor that cyclen n Would cause a pipeline “bubble”Hence, pipelined data paths requireseparate instruction & data memoriesn Or separate instruction & data cachesCSE 420Chapter 4 — The Processor — 38
Morgan Kaufmann Publishers26 January 2011§4.6 Pipelined Datapath and ControlMIPS Pipelined DatapathMEMRight-to-leftflow leads tohazardsWBCSE 420Chapter 4 — The Processor — 49Pipeline registersn Need registers between stagesn To hold information produced in previous cycleCSE 420Chapter 4 — The Processor — 50
Morgan Kaufmann Publishers26 January 2011Pipeline Operationn Cycle-by-cycle flow of instructionsthrough the pipelined data pathn “Single-clock-cycle” pipeline diagramn n n c.f. “multi-clock-cycle” diagramn n Shows pipeline usage in a single cycleHighlight resources usedGraph of operation over timeWe’ll look at “single-clock-cycle” diagramsfor load & storeCSE 420Chapter 4 — The Processor — 51IF for Load, Store, CSE 420Chapter 4 — The Processor — 52
Morgan Kaufmann Publishers26 January 2011ID for Load, Store, CSE 420Chapter 4 — The Processor — 53EX for LoadCSE 420Chapter 4 — The Processor — 54
Morgan Kaufmann Publishers26 January 2011MEM for LoadCSE 420Chapter 4 — The Processor — 55WB for LoadWrongregisternumberCSE 420Chapter 4 — The Processor — 56
Morgan Kaufmann Publishers26 January 2011Corrected Datapath for LoadCSE 420Chapter 4 — The Processor — 57EX for StoreCSE 420Chapter 4 — The Processor — 58
Morgan Kaufmann Publishers26 January 2011Pipelined Controln Control signals derived from instructionn As in single-cycle implementationCSE 420Chapter 4 — The Processor — 65Pipelined ControlChapter 4 — The Processor — 66
Morgan Kaufmann Publishers26 January 2011Datapath with ForwardingCSE 420Chapter 4 — The Processor — 75Load-Use Data HazardNeed to stallfor one cycleCSE 420Chapter 4 — The Processor — 76
Operation C Java MIPS Shift left sll Shift right srl Bitwise AND & & and, andi Bitwise OR or, ori Bitwise NOT nor ! Useful for extracting and inserting groups of bits in a word s . The University of Adelaide, School of Computer Science 17 January 2011 Chapter 2
May 02, 2018 · D. Program Evaluation ͟The organization has provided a description of the framework for how each program will be evaluated. The framework should include all the elements below: ͟The evaluation methods are cost-effective for the organization ͟Quantitative and qualitative data is being collected (at Basics tier, data collection must have begun)
Silat is a combative art of self-defense and survival rooted from Matay archipelago. It was traced at thé early of Langkasuka Kingdom (2nd century CE) till thé reign of Melaka (Malaysia) Sultanate era (13th century). Silat has now evolved to become part of social culture and tradition with thé appearance of a fine physical and spiritual .
bits, gọi là MIPS-64. MIPS xem xét trong môn học này là MIPS làm việc với các thanh ghi chỉ 32 bit, gọi là MIPS-32. ÞTrong phạm vi môn học này, MIPS dùng chung sẽ hiểu là MIPS-32 Tóm lại, chỉ có 3 loại toán hạng trong một lệnh của MIPS 1. Toán hạng thanh ghi (Register Operands) 2.
On an exceptional basis, Member States may request UNESCO to provide thé candidates with access to thé platform so they can complète thé form by themselves. Thèse requests must be addressed to esd rize unesco. or by 15 A ril 2021 UNESCO will provide thé nomineewith accessto thé platform via their émail address.
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The MIPS Instruction Set This section brie y describes the MIPS assembly language instruction set. In the description of the instructions, the following notation isused: If an instruction description begins with an, then the instruction is not a member of the native MIPS instruction set, but is available as a pseudoin-
Table 1: How 2020 MIPS Final Scores Relate to 2022 MIPS Payment Adjustments Final Score Points MIPS Payment Adjustment 0.00 – 11.25 points Negative (-) MIPS payment adjustment of -9% 11.26 – 44.99 points Negative (-) MIPS payment adjustment, between 0% and -9%, on a linear sliding scale 45.00 points (Performance threshold 45.00 points)
