Intel Quartus Prime Pro Edition User Guide: Design Constraints
Intel Quartus Prime Pro EditionUser GuideDesign ConstraintsUpdated for Intel Quartus Prime Design Suite: 21.3SubscribeSend FeedbackUG-20142 2021.10.04Latest document on the web: PDF HTML
ContentsContents1. Constraining Designs. 41.1. Specifying Design Constraints Designs in the GUI.41.1.1. Global Constraints and Assignments. 51.1.2. Node, Entity, and Instance-Level Constraints. 51.1.3. Probing Between Components of the Intel Quartus Prime GUI.91.1.4. Specifying Timing Constraints in the GUI.111.2. Constraining Designs with Tcl Scripts. 121.2.1. Create a Project and Apply Constraints. 121.2.2. Assigning a Pin. 131.2.3. Generating Intel Quartus Prime Settings Files. 131.2.4. Synopsys Design Constraint (.sdc) Files. 141.2.5. Tcl-only Script Flows.151.3. A Fully Iterative Scripted Flow. 161.4. Constraining Designs Revision History.162. Interface Planning. 192.1. Using Interface Planner. 192.1.1. Interface Planner User Interface.202.1.2. Interface Planner Tool Flow.242.1.3. Interface Planner Reports.342.2. Using Tile Interface Planner.412.2.1. Tile Interface Planner Terminology.422.2.2. Tile Interface Planner Tool Flow.432.2.3. Tile Interface Planner GUI Reference. 532.3. Interface Planning Revision History. 563. Managing Device I/O Pins. 583.1. I/O Planning Overview.593.1.1. Basic I/O Planning Flow. 593.1.2. Integrating PCB Design Tools. 593.1.3. Intel Device Terms. 613.2. Assigning I/O Pins.613.2.1. Assigning to Exclusive Pin Groups. 623.2.2. Assigning Slew Rate and Drive Strength.623.2.3. Assigning Differential Pins. 623.2.4. Entering Pin Assignments with Tcl Commands. 653.2.5. Entering Pin Assignments in HDL Code.653.3. Importing and Exporting I/O Pin Assignments. 663.3.1. Importing and Exporting for PCB Tools. 663.3.2. Migrating Assignments to Another Target Device. 663.4. Validating Pin Assignments.683.4.1. I/O Assignment Validation Rules. 683.4.2. I/O Assignment Analysis. 693.4.3. Understanding I/O Analysis Reports.733.5. Verifying I/O Timing. 733.5.1. Running Advanced I/O Timing.743.5.2. Adjusting I/O Timing and Power with Capacitive Loading. 773.6. Viewing Routing and Timing Delays. 78Intel Quartus Prime Pro Edition User Guide: Design Constraints2Send Feedback
Contents3.7. Scripting API. 783.7.1. Generate Mapped Netlist. 783.7.2. Reserve Pins. 783.7.3. Set Location. 793.7.4. Exclusive I/O Group. 793.7.5. Slew Rate and Current Strength.793.8. Managing Device I/O Pins Revision History. 804. Intel Quartus Prime Pro Edition User Guide: Design Constraints Document Archives.81A. Intel Quartus Prime Pro Edition User Guides. 82Send FeedbackIntel Quartus Prime Pro Edition User Guide: Design Constraints3
UG-20142 2021.10.04Send Feedback1. Constraining DesignsThe design constraints, assignments, and logic options that you specify influence howthe Intel Quartus Prime Compiler implements your design. The Compiler attemptsto synthesize and place logic in a manner than meets your constraints. In addition,design constraints also have an impact on how the Timing Analyzer and the PowerAnalyzer influence synthesis, placement, and routing.You can specify design constraints in the GUI, with scripts, or directly in the files thatstore the constraints. The Intel Quartus Prime software preserves the constraints thatyou specify in the GUI in the following files: Intel Quartus Prime Settings file ( project directory / revision name .qsf)—contains project-wide and instance-level assignmentsfor the current revision of the project, in Tcl syntax. Each revision of a project hasa separate .qsf file. Synopsys* Design Constraints file ( project directory / revision name .sdc)—the Timing Analyzer uses industry-standard SynopsysDesign Constraint format and stores those constraints in .sdc files.By combining the syntax of the .qsf files and the .sdc files with procedural Tcl, youcan automate iterations over several different settings, changing constraints andrecompiling.Related Information Intel Quartus Prime Pro Edition Settings File Reference ManualFor information about all settings and constraints in the Intel Quartus Primesoftware. Tcl ScriptingIn Intel Quartus Prime Pro Edition User Guide: Scripting Command Line ScriptingIn Intel Quartus Prime Pro Edition User Guide: Scripting1.1. Specifying Design Constraints Designs in the GUIIntel Quartus Prime software provides tools that help you manually implement yourproject. These tools can also support design visualization, pre-filled parameters, andwindow cross probing, facilitating design exploration and debugging.When you create or update a constraint in the Intel Quartus Prime software, theSystem tab of the Messages window displays the equivalent Tcl command. Utilizethese commands as references for future scripted design definition and compilation.Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of IntelCorporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to currentspecifications in accordance with Intel's standard warranty, but reserves the right to make changes to anyproducts and services at any time without notice. Intel assumes no responsibility or liability arising out of theapplication or use of any information, product, or service described herein except as expressly agreed to inwriting by Intel. Intel customers are advised to obtain the latest version of device specifications before relyingon any published information and before placing orders for products or services.*Other names and brands may be claimed as the property of others.ISO9001:2015Registered
1. Constraining DesignsUG-20142 2021.10.041.1.1. Global Constraints and AssignmentsGlobal constraints and project settings affect the entire Intel Quartus Prime projectand all the applicable logic in the design. You often define global constraints in earlyproject development; for example, when running the New Project Wizard. IntelQuartus Prime software stores global constraints in .qsf files, one for each projectrevision.Table 1.Intel Quartus Prime Tools to Set Global ConstraintsSetting TypeNew Project WizardDevice Dialog BoxSettings Dialog Third-party ToolsXIP SettingsXRelated InformationManaging Project SettingsIn Intel Quartus Prime Pro Edition User Guide: Getting Started1.1.2. Node, Entity, and Instance-Level ConstraintsNode, entity, and instance-level constraints apply to a subset of the design hierarchy.These constraints take precedence over any global assignment that affects the samesections of the design hierarchy. The following tools are available in the Intel QuartusPrime software to specify node, entity, and instance-level constraints:Table 2.Intel Quartus Prime Pro Edition Tools to Set Node, Entity and Instance LevelConstraintsAssignment TypeAssignment EditorPinInterface PlannerChip PlannerXXLocationXRoutingXXSimulationXXSend FeedbackXPin PlannerXXIntel Quartus Prime Pro Edition User Guide: Design Constraints5
1. Constraining DesignsUG-20142 2021.10.04Although you can specify constraints using a variety of tools, the following table showsthe most effective constraint tools at each design phase:Table 3.Constraint Tools per Design nnerChip PlannerTimingAnalyzerXXPin PlannerXXXX1.1.2.1. Specify Instance-Specific Constraints in Assignment EditorIntel Quartus Prime Assignment Editor (Assignments Assignment Editor)provides a spreadsheet-like interface for assigning all instance-specific settings andconstraints. To help you explore your design, the Assignment Editor allows you to filterassignments by node name or category.Figure 1.Intel Quartus Prime Assignment EditorUse the Assignment Editor to: Add, edit, or delete assignments for selected nodes Display information about specific assignments Enable or disable individual assignments Add comments to an assignmentAdditionally, you can export assignments to a Comma-Separated Value File (.csv).1.1.2.2. Specifying Multi-Dimensional Bus ConstraintsThe Intel Quartus Prime Pro Edition software traditionally supports only 1- and 2dimensional bus names for specifying constraints. The Intel Quartus Prime Pro Editionversion 19.3 and later now supports multi-dimensional bus names for more efficientconstraints.Intel Quartus Prime Pro Edition User Guide: Design Constraints6Send Feedback
1. Constraining DesignsUG-20142 2021.10.04For example, you can specify the following assignment to apply a constraint to all bitsin the reg [31:0] r [0:2][4:5] three-dimensional bus:set instance assignment -name PRESERVE REGISTER ON -to rThe constraint then applies to all bits r: [0][4][31], r[0][4][30], , r[1][5][0].1.1.2.3. Specify I/O Constraints in Pin PlannerIntel Quartus Prime Pin Planner allows you to assign design elements to I/O pins. Youcan also plan and assign IP interface or user nodes not yet defined in the design.Figure 2.Pin Planner GUITask andReportWindowsDevicePackageViewAll PinsListRelated InformationManaging Device I/O Pins on page 581.1.2.4. Plan Interface Constraints in Interface Planner and Tile InterfacePlannerThe Interface Planner simplifies the planning of accurate constraints for physicalimplementation. Similarly, you can use the Tile Interface Planner to build a plan forplacement of IP components in each tile available on Intel Agilex F-tile devices. UseInterface Planner to prototype interface implementations, plan clocks, and rapidlydefine a legal device floorplan.Interface Planner and Tile Interface Planner interact dynamically with the IntelQuartus Prime Fitter to accurately verify placement legality while you plan. You canevaluate different floorplans, using interactive reports to accurately plan the bestimplementation without iterative compilation. Fitter verification ensures the highestSend FeedbackIntel Quartus Prime Pro Edition User Guide: Design Constraints7
1. Constraining DesignsUG-20142 2021.10.04correlation between your interface plan and actual implementation results. You canapply the interface plan constraints to your project with high confidence in the finalimplementation.Figure 3.Interface Planner GUIDrag Elements toLegal LocationsRun Interface PlannerCommandsSelected Element’s PropertiesRelated Information Using Interface Planner on page 19 Using Tile Interface Planner on page 411.1.2.5. Adjust Constraints with the Chip PlannerWith the Chip Planner you can adjust existing assignments to device resources, suchas pins, logic cells, and LABs in a graphical representation of the device floorplan. Youcan also view equations and routing information and demote assignments by draggingand dropping to Logic Lock regions in the Logic Lock Regions Window.Intel Quartus Prime Pro Edition User Guide: Design Constraints8Send Feedback
1. Constraining DesignsUG-20142 2021.10.04Figure 4.Chip Planner GUIRelated InformationDesign Floorplan Analysis in the Chip PlannerIn Intel Quartus Prime Pro Edition User Guide: Design Optimization1.1.2.6. Constraining Designs with the Design Partition PlannerThe Design Partition Planner allows you to view design connectivity and hierarchy andcan assist you in creating effective design partitions.Additionally, the Design Partition Planner allows you to optimize design performanceby isolating and resolving failing paths on a partition-by-partition basis.Related InformationCreating Partitions and Logic Lock Regions with the Design Partition Planner and theChip PlannerIn Intel Quartus Prime Pro Edition User Guide: Design Optimization1.1.3. Probing Between Components of the Intel Quartus Prime GUIThe Intel Quartus Prime software allows you to locate nodes and instances within thecompilation database from any of the following: Project Navigator Assignment Editor Chip Planner Timing AnalyzerSend FeedbackIntel Quartus Prime Pro Edition User Guide: Design Constraints9
1. Constraining DesignsUG-20142 2021.10.04 Resource Property Viewer RTL Viewer Technology Map Viewer Fast Forward Viewer Design Partition Planner Pin Planner HDL design filesTo locate nodes or instances, follow these steps:1.Right-click the resource you want to display.2.Click Locate Node, and then click any of the available menu options.The corresponding window opens—or appears in the foreground if it is already open—and shows the element you clicked.Example 1.Locate a Resource Selected in the Project NavigatorIn the Entity list of the Hierarchy tab, right-click any object, and click Locate Locate in Chip Planner.Right-click Instancein Hierarchy TabThe Chip Planner opens and displays the instance you selected.Chip Planner displaysand keeps resource selectedIntel Quartus Prime Pro Edition User Guide: Design Constraints10Send Feedback
1. Constraining DesignsUG-20142 2021.10.041.1.4. Specifying Timing Constraints in the GUIYou can specify timing constraints in the Timing Analyzer GUI. Click the Constraintsmenu in the Timing Analyzer to specify timing constraints that you can apply to yourproject.Figure 5.Constraint menu in Timing AnalyzerWhen you specify a constraint in the GUI, the dialog box displays the equivalent SDCcommand syntax.Example 2.Create Clock Dialog BoxInsert ParametersEquivalentSDC CommandIndividual timing assignments override project-wide requirements. To avoid reporting incorrect or irrelevant timing violations, you can assign timingexceptions to nodes and paths. The Timing Analyzer supports point-to-point timing constraints, wildcards toidentify specific nodes when making constraints, and assignment groups to makeindividual constraints to groups of nodes.Send FeedbackIntel Quartus Prime Pro Edition User Guide: Design Constraints11
1. Constraining DesignsUG-20142 2021.10.04Related InformationUsing Timing ConstraintsFor descriptions of all Constraints menu commands1.2. Constraining Designs with Tcl ScriptsYou can perform all your design assignments using .sdc and .qsf setting files. Tointegrate these files in compilation and optimization flows, use Tcl scripts. Eventhough .sdc and .qsf files are written in Tcl syntax, they are not executable bythemselves.When you use Intel Quartus Prime Tcl packages, your scripts can open projects, makethe assignments, compile the design, and compare compilation results against knowngoals and benchmarks. Furthermore, such a script can automate the iterative designprocess by modifying constraints and recompiling the design.1.2.1. Create a Project and Apply ConstraintsThe command-line executables include options for common global project settings andcommands. You can use a Tcl script to apply constraints such as pin locations andtiming assignments. You can write a Tcl constraint file, or generate one for an existingproject by clicking Project Generate Tcl File for Project.The example creates a project with a Tcl script and applies project constraints usingthe tutorial design files in the Intel Quartus Prime installation directory /qdesigns/fir filter/ directory.project new filtref -overwrite# Assign family, device, and top-level fileset global assignment -name FAMILY "Arria 10"set global assignment -name DEVICE Device set global assignment -name VERILOG FILE filtref.v# Assign pinsset location assignment -to clk Pin 28set location assignment -to clkx2 Pin 29set location assignment -to d[0] Pin 139set location assignment -to d[1] Pin 140#project closeSave the script in a file called setup proj.tcl and type the commands illustrated inthe example at a command prompt to create the design, apply constraints, compilethe design, and perform fast-corner and slow-corner timing analysis. Timing analysisresults are saved in two files, filtref sta 1.rpt and filtref sta 2.rpt.quartus sh -t setup proj.tclquartus syn filtrefquartus fit filtrefquartus asm filtrefquartus sta filtref --model fast --export settings offmv filtref sta.rpt filtref sta 1.rptquartus sta filtref --export settings offmv filtref sta.rpt filtref sta 2.rptType the following commands to create the design, apply constraints, and compile thedesign, without performing timing analysis:quartus sh -t setup proj.tclquartus sh --flow compile filtrefIntel Quartus Prime Pro Edition User Guide: Design Constraints12Send Feedback
1. Constraining DesignsUG-20142 2021.10.04The quartus sh --flow compile command performs a full compilation, and isequivalent to clicking the Start Compilation button in the toolbar.1.2.2. Assigning a PinTo assign a signal to a pin or device location, use the Tcl command shown in thisexample:set location assignment -to signal name location Valid locations are pin location names. Some device families also support edge and I/Obank locations. Edge locations are EDGE BOTTOM, EDGE LEFT, EDGE TOP, andEDGE RIGHT. I/O bank locations include IOBANK 1 to IOBANK n, where n is thenumber of I/O banks in a device.1.2.3. Generating Intel Quartus Prime Settings FilesIntel Quartus Prime software allows you to generate .qsf files from your revision. Youcan embed these constraints in a scripted compilation flow, and even create setsof .qsf files for design optimization.To generate a .qsf file from the Intel Quartus Prime software, click Assignments Export Assignments.To organize the .qsf in a human readable form, Project Organize Intel QuartusPrime Settings File.Example 3.Organized .qsf FileThis example shows how .qsf files characterize a design revision. Theset global assignment command makes all global constraints and softwaresettings and set location assignment constrains each I/O node in the design toa physical pin on the device.# Project-Wide Assignments# set global assignment -name SYSTEMVERILOG FILE top.svset global assignment -name SYSTEMVERILOG FILE blinking led.svset global assignment -name SDC FILE blinking led.sdcset global assignment -name SDC FILE jtag.sdcset global assignment -name PROJECT OUTPUT DIRECTORY output filesset global assignment -name LAST QUARTUS VERSION "17.1.0 Pro Edition"set global assignment -name TEXT FILE blinking led generated.txt# Pin & Location Assignments# set location assignment PIN AN18 -to clockset location assignment PIN AR23 -to led zero onset location assignment PIN AM21 -to led two onset location assignment PIN AR22 -to led one onset location assignment PIN AL20 -to led three on# Analysis & Synthesis Assignments# set global assignment -name FAMILY "Arria 10"set global assignment -name TOP LEVEL ENTITY top# Fitter Assignments# set global assignment -name DEVICE 10AS066N3F40E2SG# ----------------# start ENTITY(top)# Fitter Assignments# Send FeedbackIntel Quartus Prime Pro Edition User Guide: Design Constraints13
1. Constraining DesignsUG-20142 2021.10.04set instance assignmentset instance assignmentset instance assignmentset instance assignmentset instance assignmentset instance assignmentset instance assignmentset instance assignmentset instance assignmentset instance assignmentset instance assignmentset instance assignmentset instance assignment# end ENTITY(top)# -name-name-name-name-name-nameIO STANDARD "1.8 V" -to led zero onIO STANDARD "1.8 V" -to led one onIO STANDARD "1.8 V" -to led two onIO STANDARD "1.8 V" -to led three onSLEW RATE 1 -to led zero onSLEW RATE 1 -to led one onSLEW RATE 1 -to led two onSLEW RATE 1 -to led three onCURRENT STRENGTH NEW 12MA -to clockCURRENT STRENGTH NEW 12MA -to led zero onCURRENT STRENGTH NEW 12MA -to led one onCURRENT STRENGTH NEW 12MA -to led two onCURRENT STRENGTH NEW 12MA -to led three onRelated InformationIntel Quartus Prime Pro Edition Settings File Reference ManualFor information about all settings and constraints in the Intel Quartus Primesoftware.1.2.4. Synopsys Design Constraint (.sdc) FilesIntel Quartus Prime software keeps timing constraints in .sdc files, which use Tclsyntax. You can embed these constraints in a scripted compilation flow, and evencreate sets of .sdc files for timing optimization.Example 4.sdc FileThe example shows the timing constrains of a small design.## PROGRAM "Quartus Prime"## VERSION "Version 17.1.0 Internal Build 91 05/07/2017 SJ Pro Edition"## DATE"Wed May 10 14:22:08 2017"#### DEVICE *********************************# Time ************************set time format -unit ns -decimal places **************# Create ******************create clock -name {clk in} -period 10.000 -waveform { 0.000 5.000 } [get ports{clk *****************# Create Generated ******************derive pll *******************# Set Clock ************************derive clock ************************# Set Input ******************set input delay -add delay -clock [get clocks {clk in}] 1.500 [get ports{async rst}]set input delay -add delay -clock [get clocks {clk in}] 1.200 [get ports{data *****************# Set Output ******************set output delay -add delay -clock [get clocks {clk in}] 2.000 [get portsIntel Quartus Prime Pro Edition User Guide: Design Constraints14Send Feedback
1. Constraining DesignsUG-20142 2021.10.04{data ******************# Set Multicycle *****************set multicycle path -setup -end -from [get keepers *] -to [get keepers {reg2}] 2Related InformationConstraining and Analyzing with Tcl CommandsIn Intel Quartus Prime Pro Edition User Guide: Timing Analyzer1.2.5. Tcl-only Script FlowsAs an alternative to .sdc and .qsf files, you can perform all design assignments andtiming constraints inside the Tcl scripts. In this case, the script that automatescompilation and custom results reporting also contains the design constraints.You can export a design's contents to a procedural, executable Tcl (.tcl) file, andthen use the generated script to restore settings after experimenting with otherconstraints.To export your constraints as an executable Tcl script, click Project Generate TclFile for Project.Example 5.blinking led generated.tcl File####Quartus Prime: Generate Tcl File for ProjectFile: blinking led generated.tclGenerated on: Wed May 10 10:14:44 2017Load Quartus Prime Tcl Project packagepackage require ::quartus::projectset need to close project 0set make assignments 1# Check that the right project is openif {[is project open]} {if {[string compare quartus(project) "blinking led"]} {puts "Project blinking led is not open"set make assignments 0}} else {# Only open if not already openif {[project exists blinking led]} {project open -revision blinking led blinking led} else {project new -revision blinking led blinking led}set need to close project 1}# Make assignmentsif { make assignments} {set global assignment -name SYSTEMVERILOG FILE top.svset global assignment -name SYSTEMVERILOG FILE blinking led.svset global assignment -name SDC FILE blinking led.sdcset global assignment -name SDC FILE jtag.sdcset global assignment -name PROJECT OUTPUT DIRECTORY output filesset global assignment -name LAST QUARTUS VERSION "17.1.0 Pro Edition"set global assignment -name TEXT FILE blinking led generated.txtset global assignment -name FAMILY "Arria 10"set global assignment -name TOP LEVEL ENTITY topset global assignment -name DEVICE 10AS066N3F40E2SGset location assignment PIN AN18 -to clockset location assignment PIN AR23 -to led zero onset location assignment PIN AM21 -to led two onset location assignment PIN AR22 -to led one onSend FeedbackIntel Quartus Prime Pro Edition User Guide: Design Constraints15
1. Constraining DesignsUG-20142 2021.10.04set location assignment PIN AL20 -to led three onset instance assignment -name IO STANDARD "1.8 V" -to led zero onset instance assignment -name IO STANDARD "1.8 V" -to led one onset instance assignment -name IO STANDARD "1.8 V" -to led two onset instance assignment -name IO STANDARD "1.8 V" -to led three onset instance assignment -name SLEW RATE 1 -to led zero onset instance assignment -name SLEW RATE 1 -to led one onset instance assignment -name SLEW RATE 1 -to led two onset instance assignment -name SLEW RATE 1 -to led three onset instance assignment -name CURRENT STRENGTH NEW 12MA -to clockset instance assignment -name CURRENT STRENGTH NEW 12MA -to led zero onset instance assignment -name CURRENT STRENGTH NEW 12MA -to led one onset instance assignment -name CURRENT STRENGTH NEW 12MA -to led two onset instance assignment -name CURRENT STRENGTH NEW 12MA -to led three on# Commit assignmentsexport assignments# Close projectif { need to close project} {project close}}The example: Opens the project Assigns Constraints Writes assignments to QSF file Closes project1.3. A Fully Iterative Scripted FlowThe ::quartus::flow Tcl package in the Intel Quartus Prime Tcl API allows you tomodify design constraints and recompile in an iterative flow.Related Information ::quartus::flowIn Intel Quartus Prime Help Command Line ScriptingIn Intel Quartus Prime Pro Edition User Guide: Scripting1.4. Constraining Designs Revision HistoryDocument VersionIntel QuartusPrime Version2021.10.0421.3Changes Removed obsolete Tcl-only Timing Analysis topic.Updated Node, Entity, and Instance-Level Constraints topic for latesttools and Constraint Tools per Design Phase table.Revised Plan Interface Constraints topic for Tile Interface Planner.Revised Probing Between Components of the Intel Quartus Prime GUIfor latest tools.2019.10.1619.3 Added "Specifying Multi-Dimensional Bus Constraints" topic.Updated examples in "Create a Project and Apply Constraints."2019.08.2118.1Corrected minor typo in "Tcl-only Script Flows" topic.continued.Intel Quartus P
Synopsys* Design Constraints file ( project_directory / revision_name .sdc)—the Timing Analyzer uses industry-standard Synopsys Design Constraint format and stores those constraints in .sdc. files. By combining the syntax of the
For an overall summary of Quartus II features, refer to the Introduction to the Quartus II Software manual. 8–4 Altera Corporation May 2008 Quartus II Handbook, Volume 1 Figure 8–1 shows the basic design flow using Quartus II integrated synthesis. Figure 8–1. Quartus II Design Flow Using Quartus II Integrated Synthesis
To use the Intel Quartus Prime Command-Line and Tcl API Help browser, type the following command: quartus_sh --qhelp This command starts the Intel Quartus Prime Command-Line and Tcl API Help browser, a viewer for information about the Intel Quartus Prime Command-Line executables and Tcl
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You must specify or create an Intel Quartus Prime Pro Edition project when you create or open a new Platform Designer system. Platform Designer inherits the device family or number from the Intel Quartus Prime Pro Edition software, which guarantees the or Platform Designer coherency. To open the
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QUARTUS PRIME INTRODUCTION USING SCHEMATIC DESIGNS For Quartus Prime 15.1 For some commands it is necessary to access two or more menus in sequence. We use the convention Menu1 Menu2 Item to indicate that to select the desired command the user should first click the left mouse button on Menu1, then within this menu click on Menu2, and then within Menu2 click on Item.
