Vivado Design Suite User Guide Using Constraints (UG903)

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Vivado Design SuiteUser GuideUsing ConstraintsUG903 (v2021.1) July 15, 2021See all versionsof this document

Revision HistoryThe following table shows the revision history for this document.SectionRevision Summary07/15/2021 Version 2021.1Use of set output delay Command OptionsAdded diagram.Setting XDC File Scoping Properties ExampleAdded a note for ORIG REF NAME property.Constraints EfficiencyUpdated the report list under Reviewing ConstraintsCoverage.Using ConstraintsUG903 (v2021.1) July 15, 2021www.xilinx.comSend Feedback2

Table of ContentsRevision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Chapter 1: IntroductionMigrating From UCF Constraints to XDC Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Navigating Content by Design Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7About XDC Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Chapter 2: Constraints MethodologyAbout Constraints Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Organizing Your Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Ordering Your Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Entering Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Creating Synthesis Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59Creating Implementation Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65Constraints Scoping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68Constraints Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76Chapter 3: Defining ClocksAbout Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Primary Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Virtual Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Generated Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Clock Groups. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Clock Latency, Jitter, and Uncertainty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .818386879699Chapter 4: Constraining I/O DelayAbout Constraining I/O Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102Input Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102Output Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105Chapter 5: Timing ExceptionsAbout Timing Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109Multicycle Paths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110Using ConstraintsUG903 (v2021.1) July 15, 2021www.xilinx.comSend Feedback3

False Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Min/Max Delays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Case Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Disabling Timing Arcs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125129137139Chapter 6: CDC ConstraintsAbout CDC Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141Constraining Bus Skew. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141Chapter 7: XDC PrecedenceAbout XDC Precedence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147XDC Constraints Order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147Exceptions Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147Chapter 8: Physical ConstraintsAbout Physical Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Netlist Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I/O Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Placement Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Routing Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Configuration Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151152154156158160Chapter 9: Defining Relatively Placed MacrosAbout Relatively Placed Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Defining Sets of Design Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Creating an RPM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Assigning Cells to RPM Sets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Assigning Relative Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Assigning a Fixed Location to an RPM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .XDC Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Converting RPMs to XDC Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161161162162165169170183Appendix A: Supported XDC and SDC CommandsValid Commands in an XDC File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186Supported SDC Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187Unsupported SDC Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198Appendix B: Additional Resources and Legal NoticesXilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199Using ConstraintsUG903 (v2021.1) July 15, 2021www.xilinx.comSend Feedback4

Documentation Navigator and Design Hubs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Training Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Using ConstraintsUG903 (v2021.1) July 15, 2021www.xilinx.com199200200201Send Feedback5

Chapter 1IntroductionMigrating From UCF Constraints to XDC ConstraintsThe Xilinx Vivado Integrated Design Environment (IDE) uses Xilinx Design Constraints(XDC), and does not support the legacy User Constraints File (UCF) format.There are key differences between Xilinx Design Constraints (XDC) and User Constraints File(UCF) constraints. XDC constraints are based on the standard Synopsys Design Constraints(SDC) format. SDC has been in use and evolving for more than 20 years, making it the mostpopular and proven format for describing design constraints.VIDEO: For training on migrating UCF constraints to XDC, see the Vivado Design Suite QuickTakeVideo: Migrating UCF Constraints to XDC.If you are familiar with UCF but new to XDC, see the "Differences Between XDC and UCFConstraints" section in the Migrating UCF Constraints to XDC chapter of the ISE to VivadoDesign Suite Migration Guide (UG911) [Ref 1]. That chapter also describes how to convertexisting UCF files to XDC as a starting point for creating XDC constraints.IMPORTANT: XDC has fundamental differences from UCF that must be understood in order to properlyconstrain a design. The UCF to XDC conversion utility is not a replacement for properly understandingand creating XDC constraints. Each XDC constraint is described in this User Guide.Using ConstraintsUG903 (v2021.1) July 15, 2021www.xilinx.comSend Feedback6

Chapter 1: IntroductionNavigating Content by Design ProcessXilinx documentation is organized around a set of standard design processes to help youfind relevant content for your current development task. This document covers thefollowing design processes:Hardware, IP, and Platform DevelopmentCreating the PL IP blocks for the hardware platform, creating PL kernels, subsystemfunctional simulation, and evaluating the Vivado timing, resource use, and power closure.Also involves developing the hardware platform for system integration. Topics in thisdocument that apply to this design process include: Dedicated Hardware Resources IP and Sub-Module Constraining with XDCAbout XDC ConstraintsXDC constraints are a combination of industry standard Synopsys Design Constraints (SDCversion 1.9) and Xilinx proprietary physical constraints.XDC constraints have the following properties: They are not simple strings, but are commands that follow the Tcl semantic. They can be interpreted like any other Tcl command by the Vivado Tcl interpreter. They are read in and parsed sequentially the same as other Tcl commands.You can enter XDC constraints in several ways, at different points in the flow. Store the constraints in one or more XDC files.To load the XDC file in memory, do one of the following: Use the read xdc command.Add it to one of your project constraints sets. XDC files only accept the set, list,and expr built-in Tcl commands. See Appendix A, Supported XDC and SDCCommands for a complete list of supported commands.Generate the constraints with an unmanaged Tcl script.To execute the Tcl script, do one of the following: Run the source command.Using ConstraintsUG903 (v2021.1) July 15, 2021www.xilinx.comSend Feedback7

Chapter 1: Introduction Use the read xdc -unmanaged command. Add the Tcl script to one of your project constraints sets.TIP: Unlike XDC files, unmanaged Tcl scripts can include any common Tcl command for selectingdesign objects and defining design constraints, including conditional and looping control structures.IMPORTANT: The Vivado Design Suite allows you to mix XDC files and Tcl scripts in the sameconstraints set. Modified constraints are saved back to their original location only if they originallycame from an XDC file, and not from an unmanaged Tcl script. A constraint generated by a Tcl script isnot managed by the Vivado Design Suite and cannot be interactively modified. For more information,see Chapter 2, Constraints Methodology.IMPORTANT: For XDC constraints, there is a difference in behavior between the commands sourceand read xdc. The constraints imported with the source command are not saved in the checkpointin the same order as they are imported. The constraints imported with read xdc are saved first andthen those imported with source. To save all the constraints in the same order as they are applied tothe design, use read xdc -unmanaged instead of source.To validate the syntax or impact of a particular constraint after loading your design inmemory, use the Tcl console and the Vivado Design Suite reporting features. This isparticularly powerful for analyzing and debugging timing constraints and physicalconstraints.Using ConstraintsUG903 (v2021.1) July 15, 2021www.xilinx.comSend Feedback8

Chapter 2Constraints MethodologyAbout Constraints MethodologyDesign constraints define the requirements that must be met by the compilation flow inorder for the design to be functional on the board. Not all constraints are used by all stepsin the compilation flow. For example, physical constraints are used only during theimplementation steps (that is, by the placer and the router).Because the Xilinx Vivado Integrated Design Environment (IDE) synthesis andimplementation algorithms are timing-driven, you must create proper timing constraints.Over-constraining or under-constraining your design makes timing closure difficult. Youmust use reasonable constraints that correspond to your application requirements.Organizing Your ConstraintsThe Vivado IDE allows you to use one or many constraint files. While using a singleconstraint file for the entire compilation flow might seem more convenient, it can be achallenge to maintain all the constraints as the design becomes more complex. This isusually the case for designs that use several IP cores or large blocks developed by differentteams.After the timing and physical constraints have been imported, independent of the numberof source files or whether the design is in Project or Non-Project mode, all the constraintscan be exported as a single file with the write xdc command. The constraints are writtento the specified output file in the same order that they were read into the project or design.The command line option write xdc -type can be used to select a subset of constraints(timing, physical, or waiver) to export.RECOMMENDED: Xilinx recommends that you separate timing constraints and physical constraints bysaving them into two distinct files. You can also keep the constraints specific to a certain module in aseparate file.Using ConstraintsUG903 (v2021.1) July 15, 2021www.xilinx.comSend Feedback9

Chapter 2: Constraints MethodologyProject FlowsYou can add your Xilinx Design Constraints (XDC) files to a constraints set during thecreation of a new project, or later, from the Vivado IDE menus.Figure 2-1 shows two constraint sets in a project, which are single- or multi-XDC. The firstconstraint set includes two XDC files. The second constraint set uses only one XDC filecontaining all the constraints.X-Ref Target - Figure 2-1Figure 2-1:Single or Multi XDCIMPORTANT: If your project contains an IP that uses its own constraints, the corresponding constraintfile does not appear in the constraints set. Instead, it is listed along with the IP source files.You can also add Tcl scripts to your constraints set as unmanaged constraints orunmanaged Tcl scripts. The Vivado Design Suite does not write modified constraints backinto an unmanaged Tcl script. Tcl scripts and XDC files are loaded in the same sequence asdisplayed in the Vivado IDE (if they belong to the same PROCESSING ORDER group) or asreported by the command report compile order -constraints.An XDC file or a Tcl script can be used in several constraints sets if needed. For moreinformation on how to create and add constraint files and constraints sets to your project,see Working with Constraints in the Vivado Design Suite User Guide: System-Level DesignEntry (UG895) [Ref 2].Using ConstraintsUG903 (v2021.1) July 15, 2021www.xilinx.comSend Feedback10

Chapter 2: Constraints MethodologyNon-Project FlowsIn Non-Project Mode, you must read each file individually before executing the compilationcommands.The example script below shows how to use one or more XDC files for synthesis andimplementation.Example Script:read verilog [glob src/*.v]read xdc wave gen timing.xdcread xdc wave gen pins.xdcsynth design -top wave gen -part xc7k325tffg900-2opt designplace designroute designOut-of-Context ConstraintsIn designs using Dynamic Function eXchange (DFX), it is common to synthesize parts of thedesign in an Out-of-Context (OOC) approach. When such a flow is used, some constraintscan be specified for the OOC synthesis only. For example, clocks that propagate at the inputboundary of the blocks must be defined when the blocks are synthesized OOC. These clocksare defined inside an OOC XDC file.In Project Mode:add file constraints ooc.xdcset property USED IN {synthesis out of context} [get files constraints ooc.xdc]The Out-of-Context can also be set on the XDC file through the GUI (property on fileconstraints ooc.xdc).In Non-Project Mode:read xdc -mode out of context constraints ooc.xdcSynthesis and Implementation Constraint FilesBy default, all XDC files and Tcl scripts added to a constraint set are used for both synthesisand implementation. Set the USED IN SYNTHESIS and USED IN IMPLEMENTATIONproperties on the XDC file or the Tcl script to change this behavior. This property can takethe value of either TRUE or FALSE.IMPORTANT: The DONT TOUCH attribute does not obey the properties of USED IN SYNTHESIS andUSED IN IMPLEMENTATION. If you use DONT TOUCH properties in the synthesis XDC, it ispropagated to implementation regardless of the value of USED IN IMPLEMENTATION.For more information about the DONT TOUCH attribute, refer to RTL Attributes, page 59.Using ConstraintsUG903 (v2021.1) July 15, 2021www.xilinx.comSend Feedback11

Chapter 2: Constraints MethodologyIMPORTANT: If any module (IP/BD/.) is synthesized in Out-Of-Context (OOC) mode, the top-levelsynthesis run infers a black box for these modules. Hence, the top-level synthesis constraints will not beable to reference objects such as pins, nets, cells, etc., that are internal to the OOC module. If sometop-level constraints refer to objects inside any OOC module, you may need to split the constraints into2 files: one XDC file for Synthesis (USED IN SYNTHESIS TRUE / USED IN IMPLEMENTATION FALSE)and one XDC file for implementation (USED IN SYNTHESIS FALSE /USED IN IMPLEMENTATION TRUE). There is no such limitation during implementation since thenetlists from the OOC module DCPs are linked with the netlist produced when synthesizing thetop-level design files, and the Vivado Design Suite resolves the black boxes. The XDC output productsthat were generated for use during implementation are applied along with any user constraints.For example, to use a constraint file for implementation only:1. Select the constraint file in the Sources window.2. In the Source File Properties window:a. Uncheck Synthesis.b. Check Implementation.X-Ref Target - Figure 2-2Figure 2-2:Source File Properties WindowThe equivalent Tcl commands are:set property USED IN SYNTHESIS false [get files wave gen pins.xdc]set property USED IN IMPLEMENTATION true [get files wave gen pins.xdc]Using ConstraintsUG903 (v2021.1) July 15, 2021www.xilinx.comSend Feedback12

Chapter 2: Constraints MethodologyWhen running Vivado in Non-Project Mode, you can read in the constraints directlybetween any steps of the flow. The properties USED IN SYNTHESIS andUSED IN IMPLEMENTATION do not matter in this mode.The following compilation Tcl script shows how to read two XDC files for different steps ofthe flow:read verilog [glob src/*.v]read xdc wave gen timing.xdcsynth design -top wave gen -part xc7k325tffg900-2read xdc wave gen pins.xdcopt designplace designroute designTable 2-1:Reading XDC Files Before and After SynthesisFile Namewave gen timing.xdcFile PlacementBefore synthesisUsed For Synthesis Implementationwave gen pins.xdcAfter synthesis ImplementationTIP: The constraints read in after synthesis are applied in addition to the constraints read in beforesynthesis.Ordering Your ConstraintsBecause XDC constraints are applied sequentially, and are prioritized based on clearprecedence rules, you must review the order of your constraints carefully. For moreinformation, see Chapter 7, XDC Precedence.Note: If multiple physical constraints are conflicting, the latest constraint wins. For example, if anI/O port gets assigned a different location (LOC) through multiple XDC files, the latest locationassigned to the port takes precedence.The Vivado IDE provides full visibility into your design. To validate your constraints step bystep:1. Run the appropriate report commands.2. Review the messages in the Tcl Console or the Messages window.Using ConstraintsUG903 (v2021.1) July 15, 2021www.xilinx.comSend Feedback13

Chapter 2: Constraints MethodologyRecommended Constraints SequenceRECOMMENDED: Whether you use one or several XDC files for your design, organize your constraintsin the following sequence.## Timing Assertions Section# Primary clocks# Virtual clocks# Generated clocks# Clock Groups# Bus Skew constraints# Input and output delay constraints## Timing Exceptions Section# False Paths# Max Delay / Min Delay# Multicycle Paths# Case Analysis# Disable Timing## Physical Constraints Section# located anywhere in the file, preferably before or after the timing constraints# or stored in a separate constraint fileNote: The case analysis constraints that change the clock relationships or clock propagation shouldbe defined prior to defining the generated clocks. This includes the case analysis defined on clockbuffers that result in the output clock of the buffer to be impacted by the case analysis.Start with the clock definitions. The clocks must be created before they can be used by anysubsequent constraints. Any reference to a clock before it has been declared results in anerror and the corresponding constraint is ignored. This is true within an individualconstraint file, as well as across all the XDC files (or Tcl scripts) in your design.The order of the constraint files matters. You must be sure that the constraints in each filedo not rely on the constraints of another file. If this is the case, you must read the file thatcontains the constraint dependencies last. If two constraint files have interdependencies,you must either merge them manually into one file that contains the proper sequence, ordivide the files into several separate files and order them correctly.Constraints Sequence EditingThe Vivado IDE constraints manager saves any edited constraint back to its original locationin the XDC files, but not in Tcl scripts. Any new constraint is saved at the end of the XDC filemarked as target. In many cases, when your constraints set contains several XDC files, thetarget constraint file is not the last file in the list, and will not be loaded last when openingor reloading your design. As a consequence, the constraints sequence saved to constraintsource files can be different from the one you had previously in memory.IMPORTANT: You must verify that the final sequence stored in the constraint files still works asexpected. If you must modify the sequence, you must modify it by directly editing the constraint files.This is especially important for timing constraints.Using ConstraintsUG903 (v2021.1) July 15, 2021www.xilinx.comSend Feedback14

Chapter 2: Constraints MethodologyConstraint Files OrderIn a project flow without any IP, all the constraints are located in a constraints set. Bydefault, the order of the XDC files (or Tcl scripts) displayed in the Vivado IDE defines theread sequence used by the tool when loading an elaborated or synthesized design intomemory. The file at the top of the list is read in first, and the bottom one is read in last. Youcan change the order by simply selecting the file in the IDE, and moving it to the desiredplace in the list.For example, in Figure 2-3, the file wave gen pin.xdc was moved to before the filewave gen timing.xdc by using drag and drop.X-Ref Target - Figure 2-3Figure 2-3:Changing XDC File Order in the Vivado IDE ExampleThe equivalent Tcl command is:reorder files -fileset constrs 1 -before [get files wave gen timing.xdc] \[get files wave gen pins.xdc]Table 2-2:File Order Before and AfterFileOrder (Before)Order (After)wave gen timing.xdc12wave gen pins.xdc21In Non-Project Mode, the sequence of the read xdc calls determine the order in which theconstraint files are evaluated.Constraint Files Order with IP CoresMany IP cores are delivered with one or more XDC files. When such IP cores are generatedwithin your RTL project, their XDC files are also used during the various design compilationsteps.For example, Figure 2-4 shows that one of the IP cores in the project comes with an XDCfile.Using ConstraintsUG903 (v2021.1) July 15, 2021www.xilinx.comSend Feedback15

Chapter 2: Constraints MethodologyX-Ref Target - Figure 2-4Figure 2-4:XDC Files in the IP SourcesBy default, IP XDC files are read in before the user XDC files. Processing it in this way allowsan IP to create a clock object that can be referenced in the XDC. It also allows you tooverwrite physical constraints set by an IP core because the user constraints are evaluatedafter the IP. There is an exception to this order for the IP cores that have a dependency onclock objects being created by the user or by another IP (for example, get clocks-of objects [get ports clka]). In this case, the IP XDC is read after the user files.This behavior is controlled by the PROCESSING ORDER property, set for each XDC file: EARLY: Files that must be read first NORMAL: Default LATE: Files that must be read lastAn IP XDC will have its PROCESSING ORDER property set to either EARLY or LATE. No IPdelivers XDC files that belong to the NORMAL constraints group. For user XDC (or Tcl) filesthat belong to the same PROCESSING ORDER group, their relative order displayed in theVivado IDE determines their read sequence. The order within the group can be modified bymoving the files in the Vivado IDE constraints set, or by using the reorder filescommand.For IP XDC files that belong to the same PROCESSING ORDER group, the order isdetermined by import or creation sequence of the IP cores. This order cannot be changedafter the project has been created.Using ConstraintsUG903 (v2021.1) July 15, 2021www.xilinx.comSend Feedback16

Chapter 2: Constraints MethodologyFinally, the relative order between user groups and IP XDC PROCESSING ORDER groups areas follows:1. User Constraints marked as EARLY2. IP Constraints marked as EARLY (default)3. User Constraints marked as NORMAL4. IP Constraints marked as LATE (contain clock dependencies)5. User Constraints marked as LATENote: IP XDC files that have their PROCESSING ORDER set to LATE (in order to be processed afterthe user constraints) are named IP NAME clocks.xdc.The following figure shows an example of how to set the PROCESSING ORDER property:X-Ref Target - Figure 2-5Figure 2-5:Setting the XDC File PROCESSING ORDER ExampleThe equivalent Tcl command is:set property PROCESSING ORDER EARLY [get files wave gen pins.xdc]RECOMMENDED: Use the report compile order -constraints command in the Tcl console toreport the XDC files read sequence determined by the tool based the properties mentioned above,including IS ENABLED, USED IN SYNTHESIS, and USED IN IMPLEMENTATION.Note: When an IP is synthesized Out of Context, the IP provides, when needed, an ooc.xdc filewhich contains the default clock definition. The ooc.xdc has the USED IN property set to "synthesisout of context implementation" (order does not matter). During the Out Of Context synthesis, theooc file is always processed before all other constraints.Changing Read OrderTo change the read order of an XDC file or unmanaged Tcl script in a constraints set:1. In the Sources window, select the XDC file or Tcl script you want to move.2. Drag and drop the file to the desired position in the constraints set.For the example shown in Figure 2-3, the equivalent Tcl command is:reorder files -fileset constrs 1 -before [get files wave gen timing.xdc] \[get files wave gen pins.xdc]In Non-Project Mode, the sequence of the read xdc or source commands determinesthe order the constraint files are read.Using ConstraintsUG903 (v2021.1) July 15, 2021www.xilinx.comSend Feedback17

Chapter 2: Constraints MethodologyIf you use an IP core that comes with constraints, two groups of constraints are handledautomatically as follows: Constraints that do not depend on clocks are grouped in an XDC file withPROCESSING ORDER set to EARLY, Constraints that depend on clocks are grouped in an XDC file withPROCESSING ORDER set to LATE.By default, user XDC files belong to the PROCESSING ORDER NORMAL group. They areloaded after EARLY XDC files and before LATE XDC files. For each PROCESSING

There are key differences between Xilinx Design Constraints (XDC) and User Constraints File (UCF) constraints. XDC constraints are based on the standard Synopsys Design Constraints (SDC) format. SDC has been in use and evolving for more than 20 years, making it the most popular and proven f

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For more information about the Vivado IDE and the Vivado Design Suite flow, see: Vivado Design Suite User Guide: Using the Vivado IDE (UG893) [Ref 4] Vivado Design Suite User Guide: Design Flows Overview (UG892) [Ref 12] Simulation Flow Simulation can be applied at several points in the design flow. It is one of the first steps after .

For more information about the Vivado IDE and the Vivado Design Suite flow, see: Vivado Design Suite User Guide: Using the Vivado IDE (UG893) [Ref 3] Vivado Design Suite User Guide: Design Flows Overview (UG892) [Ref 11] Simulation Flow Simulation can be applied at several points in the design flow. It is one of the first steps after .

Vivado Design Suite 2016.2 Release Notes www.xilinx.com 5 UG973 (v2016.2) June 8, 2016 Chapter 1 Release Notes 2016.2 What's New Vivado Design Suite 2016.2 and updated UltraFast Design Methodology Guide for the Vivado Design Suite (UG949) [Ref 1] Available Now. Get Vivado Design Suite 2016.2 with support for Virtex UltraScale and Defense-Grade .

2 Vivado Partial Reconfiguration - Documentation UG909: Vivado Design Suite User Guide - Partial Reconfiguration. UG947: Vivado Design Suite Tutorial - Partial Reconfiguration. You can follow this for the Xilinx-provided ug947-vivado-partial-reconfiguration-tutorial.zip file (this is a Verilog design for

more information on the different design flow modes, see this link in the Vivado Design Suite User Guide: Design Flows Overview (UG892). Note: Installation, licensing, and release information is available in the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973). W o r k i n g w i t h t h e V i v a d o I D E

those objects, in the Xilinx Vivado Design Suite. It consists of the following: Chapter 1, Vivado Design Suite First Class Objects: Describes the various design and device objects used by the Vivado Design Suite to model the FPGA design database. Presents the objects sorted according to specific categories, with links to detailed

See the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973) for a complete list and description of the system and software requirements. Configuring MATLAB to the Vivado Design Suite Before you begin, you should verify that MATLAB is configured to the Vivado Design Suite. Do the following: 1. Configure MATLAB.

Guide (UG911). For more information about XDC, see the Vivado Design Suite User Guide: Using Constraints (UG903). CAUTION! Do not migrate from ISE Design Suite to Vivado Design Suite while in the middle of an in-progress ISE Design Suite project, because design constraints and scripts are not compatible between these environments.