SPICE Model Parameters For RIT MOSFET’s
RIT MOSFET SPICE ParametersROCHESTER INSTITUTE OF TECHNOLOGYMICROELECTRONIC ENGINEERINGSPICE Model Parameters for RITMOSFET’sDr. Lynn FullerMicroelectronic EngineeringRochester Institute of Technology82 Lomb Memorial DriveRochester, NY 14623-5604Tel (585) 475-2035Fax (585) 475-5041Dr. Fuller’s Webpage: http://people.rit.edu/lffeeeEmail: Lynn.Fuller@rit.eduDept Webpage: http://www.microe.rit.eduRochester Institute of TechnologyMicroelectronic Engineering12-10-2013 SPICE MOSFET Models.ppt December 22, 2013 Dr. Lynn FullerPage 1
RIT MOSFET SPICE ParametersOUTLINEIntroductionSPICE Level 1 ModelSPICE Level 3 ModelBSIM3 ModelSPICE Parameter CalculatorSPICE Parameters for RIT MOSFETsWinspiceExamplesParameter Extraction Using UTMOSTATHENA ATLAS UTMOST SPICEReferencesRochester Institute of TechnologyMicroelectronic Engineering December 22, 2013 Dr. Lynn FullerPage 2
RIT MOSFET SPICE ParametersSPICE - SIMULATION PROGRAM FOR INTEGRATEDCIRCUIT ENGINEERINGDevice models used by SPICE (Simulation Program for IntegratedCircuit Engineering) simulators can be divided into three classes:First Generation Models (Level 1, Level 2, Level 3 Models), SecondGeneration Models (BISM, HSPICE Level 28, BSIM2) and ThirdGeneration Models (BSIM3, Level 7, Level 48, etc.) The newergenerations can do a better job with short channel effects, localstress, transistors operating in the sub-threshold region, gate leakage(tunneling), noise calculations, temperature variations and theequations used are better with respect to convergence during circuitsimulation.Rochester Institute of TechnologyMicroelectronic Engineering December 22, 2013 Dr. Lynn FullerPage 3
RIT MOSFET SPICE ParametersSPICE LEVEL-1 SHICHMAN AND HODGESIf we understand the Level 1 model we can better understand theother models. The Level 1 model by Shichman and Hodges usesbasic device physics equations for MOSFET threshold voltage anddrain current in the saturation and non-saturation regions ofoperation. Mobility is assumed to be a function of total dopingconcentration only and a parameter called LAMBDA is used tomodel channel length modulation.David A. HodgesRochester Institute of TechnologyMicroelectronic Engineering December 22, 2013 Dr. Lynn Fullerhodges@EECS.berkeley.eduPage 4
RIT MOSFET SPICE ParametersSPICE LEVEL-1 MOSFET MODELGCGSOCGDOSDCOXp p IDRSRDCBDCBSCGBOBRochester Institute of TechnologyMicroelectronic Engineeringwhere ID is a dependent current sourceusing the equations on the next page December 22, 2013 Dr. Lynn FullerPage 5
RIT MOSFET SPICE ParametersSPICE LEVEL-1 EQUATIONS FOR UO, Vto AND IDMobility:(µmax-µmin)µ µ min {1 (N/Nref) }Threshold Voltage: /nmos/pmosVTO ParameterµminµmaxNrefArsenic52.214179.68X10 160.680Phosphorous68.514149.20X10 160.711Boron44.9470.52.23X10 170.719ms - q NSS/Cox’ / -2[ F] /-2 (q s NSUB [ F])0.5/Cox’F] (KT/q ) ln (NSUB/ni) where ni 1.45E10 and KT/q 0.026Absolute valueDrain Current:Non-SaturationSaturationID µW Cox’ (Vg-Vt-Vd/2)Vd (1 Vds)LIDsat µW Cox’ (Vg-Vt)2 (1 Vds)2LRochester Institute of TechnologyMicroelectronic Engineering December 22, 2013 Dr. Lynn FullerCox’ r o/TOX 3.9 o/TOXPage 6
RIT MOSFET SPICE ParametersBACK-BIASING EFFECTS – GAMMABody Effect coefficient GAMMA orVSB 0 VSB 1VVSB 2VIds:-Vsb Rochester Institute of TechnologyMicroelectronic Engineering December 22, 2013 Dr. Lynn Fuller2F2FV SBr si 11.7 and r ox 3.9o 8.8eE-14F/cmq 1.6E-19Page 7
RIT MOSFET SPICE ParametersCHANNEL LENGTH MODULATION - LAMBDAChannel Length ModulationParameter Slope/ IdsatSpVgNMOS IdsSlopeVdSaturation Region 5 4 Vgs 3 2IdsatnnL- LLVd2Vd1IDsat µW Cox’ (Vg-Vt)2 (1 Vds)2LSaturation RegionVd1Vd2 VdsNMOS TransistorDC Model, is the channel length modulationparameter and is different for each channellength, L. Typical value might be 0.02ID µW Cox’ (Vg-Vt-Vd/2)Vd (1 Vds)LRochester Institute of TechnologyMicroelectronic EngineeringNon Saturation Region December 22, 2013 Dr. Lynn FullerPage 8
RIT MOSFET SPICE ParametersLAMBDA VERSUS CHANNEL LENGTHLAMBDA205715634218.8415137911372715SLOPE IDSAT 224681632LAMBDAPMOSNMOS0.144118 0.1323080.056338 0.0267610.049315 0.0114290.032 0.0138890.028571 0.0055560.021053 0041960.160.14PMOS0.120.1LAMBDAµAUNITNMOSy ENGTHNeed different model for each different length transistorRochester Institute of TechnologyMicroelectronic Engineering December 22, 2013 Dr. Lynn FullerPage 9
RIT MOSFET SPICE ParametersSPICE LEVEL-1 PARAMETERSSPICE LEVEL 1 MODEL FOR MOS TRANSISTORS:1. LEVEL 17. RD13. CGSO19. CJSW25. NFS2. VTO8. RS14. CGDO20. MJSW26. TPG3. KP9. CBD15. CGBO21. JS27. XJ4. GAMMA10. CBS16. RSH22. TOX28. LD5. PHI11. IS17. CJ23. NSUB29. UO6. LAMBDA12. PB18. MJ24. NSS30.-41. PARAMETERS FOR SHORT CHANNEL AND NOISE (Use Defaults)SPICE is not case sensitive.The O in these parameters is “oh” not zero.Rochester Institute of TechnologyMicroelectronic Engineering December 22, 2013 Dr. Lynn FullerPage 10
RIT MOSFET SPICE ParametersSPICE LEVEL-1 PARAMETERS FOR MOSFET (cont.)1. LEVEL 1 Shichman-Hodges Model (If not specified the default is LEVEL 1)2. VTO zero bias threshold voltage (Do not use, let SPICE calculate from Nsub,TOXunless an VT adjust ion implant is used to set VTO at some value) IdVsub 0 Ids-1-2-3 voltsVTO VgSaturation Region 5 Vgs 4 3 2 VTO Vds3. KP transconductance parameter (Do not use, let SPICE calculate from UO, COX’)KP UO COX’ UO r o / TOXRochester Institute of TechnologyMicroelectronic Engineering December 22, 2013 Dr. Lynn FullerPage 11
RIT MOSFET SPICE ParametersSPICE LEVEL-1 PARAMETERS FOR MOSFET (cont.)4. GAMMA bulk threshold parameter (Do not use, let SPICE calculate from NSUB,COX’)GAMMA [2q rsi o NSUB/C’ox2]1/2where si o (11.7)(8.85E-12)and q 1.6E-195. PHI is the surface inversion potential, 2 x Intrinsic Level to Fermi Leveldifference in Volts (Do not use, let SPICE calculate from NSUB)PHI 2[ F] 2 (KT/q) ln (NSUB/ni) where KT/q 0.026ni 1.45E106. LAMBDA is the channel length modulation parameter, Slope in saturationregion divided by Idsat IdsSaturation RegionSlope 5 Slope/ Idsat 4 VgsIdsat 3 2Rochester Institute of TechnologyMicroelectronic EngineeringVd1 December 22, 2013 Dr. Lynn FullerVd2 VdsPage 12
RIT MOSFET SPICE ParametersSPICE LEVEL-1 PARAMETERS FOR MOSFET (cont.)7. RD the series drain resistance can either be given as a resistance value orthrough RSH the drain/source sheet resistance and the number of squares NRS.NRS: Is from the device layout. RSH: Is measured by four point probe or Van DerPauw structures(Do not use, let SPICE calculate from sheet resistance, RSH, and number of squares in drain,NRD)8. RS is the series source resistance can either be given as a resistance value orthrough RSH the drain/source sheet resistance and the number of squares NRS.NRS: Is from the device layout. RSH: Is measured by four point probe or Van DerPauw structures(Do not use, let SPICE calculate from sheet resistance, RSH, and number of squares insource, NRS)Rochester Institute of TechnologyMicroelectronic Engineering December 22, 2013 Dr. Lynn FullerPage 13
RIT MOSFET SPICE ParametersSPICE LEVEL-1 PARAMETERS FOR MOSFET (cont.)9. CBD zero bias bulk to drain junction capacitance (Do not use, let SPICEcalculate from CJ and CJSW and AD (Area of Drain) and PD (Perimeter of Drain)CBD CJ AD CJSW PD10. CBS zero bias bulk to source junction capacitance (Do not use, let SPICEcalculate from CJ and CJSW and AS (Area of Source) and PD (Perimeter of Source)CBS CJ AS CJSW PS11. IS is the bulk junction saturation current in the ideal diode equation.I IS (exp qVA/KT - 1)(Do not use, let SPICE calculate from JS and AD (Area of Drain) and AS (Area of Source)IS JS (AD AS)12. PB is the junction built in voltagePB (KT/q)ln (NSUB/ni) 0.56 or PB (KT/q) ln (Na Nd/ni2)Rochester Institute of TechnologyMicroelectronic Engineering December 22, 2013 Dr. Lynn FullerPage 14
RIT MOSFET SPICE ParametersSPICE LEVEL-1 PARAMETERS FOR MOSFET (cont.)Cox’ r o/TOX 3.9 o/TOX13. CGSO is the gate-to-source overlap capacitance (per meter channel width)CGSO Cox’ (mask overlap in L direction LD) F/m14. CGDO is the gate-to-drain overlap capacitance (per meter channel width)CGDO Cox’ (mask overlap in L direction LD) F/m15. CGBO is the gate-to-bulk overlap capacitance (per meter channel length)CGBO Cfield oxide * mask overlap in W directionF/mCfield oxide r o/XFieldOXRochester Institute of TechnologyMicroelectronic Engineering December 22, 2013 Dr. Lynn FullerPage 15
RIT MOSFET SPICE ParametersSPICE LEVEL-1 PARAMETERS FOR MOSFET (cont.)16. RSH is the drain and source diffusion sheet resistance. Measured from fourpoint probe or Van Der Pauw structures.17. CJ is the zero bias bulk junction bottom capacitance per square meter ofjunction area. CJ r o / W where W is width of space charge layer.CJ r o [2 r o ( o-VA)/qNsub]-mF/m2whereo PB (KT/q) ln (NSUB/ni) 0.56m junction grading coefficient 0.518. MJ is the junction grading coefficient 0.519. CJSW is the zero bias bulk junction sidewall capacitance per meter ofjunction perimeter. CJSW CJ XJ20. MJSW is the junction grading coefficient 0.521. JS is the bulk junction saturation current density in Amperes per squaremeterJS q ni2 (Dp/NdLp Dn/ NaLn) where D (KT/q) µ and L (DRochester Institute of TechnologyMicroelectronic Engineering December 22, 2013 Dr. Lynn FullerPage 16
RIT MOSFET SPICE ParametersSPICE LEVEL-1 PARAMETERS FOR MOSFET (cont.)22. TOX is the gate oxide thickness, measured by ellipsometer or reflectancespectroscopy (Nanospec).23. NSUB the substrate doping is given by the wafer manufacturer or measuredby four point probe technique. In both cases NSUB is given indirectlyby the resistivity, Rho. Rho 1/(qµ(N)N) where q 1.6E-19 coul, Nis the substrate doping NSUB, µ(N) is the mobility, a function of N.0 2109 1108 1107 11065 110 110 14ArsenicBoronPhosphorus1010 1316001400120010008006004002000Emperical Equation:µ µmin µmax-µmin{1 (N/Nref) }Electronsµmin92µmax 1360Nref 1.3E17Rochester Institute of TechnologyMicroelectronic Engineering December 22, 2013 Dr. Lynn FullerPage 17Holes47.74956.3E16
RIT MOSFET SPICE ParametersSPICE LEVEL-1 PARAMETERS FOR MOSFET (cont.)24. NSS: The surface state density is a parameter used in the calculation of the zerobias threshold voltage (ie. Vsource Vsubstrate), VT0 is obtained from transistorcurves.VTO ms - q NSS/Cox’ -2F (KT/q ) ln (NSUB/ni)ms m - ( Eg/2 -F -2 (q s NSUBF) 0.5/Cox’where ni 1.45E10 and KT/q 0.026F) wherem gate work function 4.15 eV, Eg 1.12 eVs r o 11.7 oSince everything is knownCox’ r o/TOX 3.9 o/TOXin equations above, NSScan be calculated25. NFS is the fast surface state density, usually left at zero.Rochester Institute of TechnologyMicroelectronic Engineering December 22, 2013 Dr. Lynn FullerPage 18
RIT MOSFET SPICE ParametersSPICE LEVEL-1 PARAMETERS FOR MOSFET (cont.)26. TPG is the type of gate. for aluminum TPG 0, for n poly TPG 1,for p poly TPG -127. XJ metallurgical junction depth, measured by groove and stain techniques.28. LD lateral diffusion distance, inferred from process knowledge29. UO is the surface mobility taken as 1/2 the bulk mobility orextracted to give correct Id value on measured Id vs Vds characteristicsin the saturation region. For best results make measurements on a transistor withlarge channel length so that is small and the lateral diffusion can be neglected.IDsat µW Cox’ (Vg-Vt)2 (1 Vds)2L30. - 41. Parameters associated with short channel devices and noise inMOSFETsRochester Institute of TechnologyMicroelectronic Engineering December 22, 2013 Dr. Lynn FullerPage 19
RIT MOSFET SPICE ParametersSPICE 2ND GENERATION MODELS AND PARAMETERS2ND generation MOSFET models improve over the Level 1 modelsbecause they model sub-threshold current, mobility as a function ofvertical and lateral electric field strength, threshold voltage reduction asa function drain voltage or drain induced barrier lowering (DIBL).This model has separate equations for drain current for differentregions of operation. The discontinuity at the transition points canmake problems in program convergence during circuit simulation.Note: LEVEL 1 model Idwouldfollow green lineRochester Institute of TechnologyNote: LEVEL 1 model Idwould increase with (Vgs-Vt)2Microelectronic Engineering December 22, 2013 Dr. Lynn FullerPage 20
RIT MOSFET SPICE ParametersTerada-Muta Method for Leff and RdsIn the linear region (VD is small):ID µW Cox’ (Vg-Vt-Vd/2) VDLeffI D 1/Rm VD0Leff Lm - Lwhere L is correction due to processingLm is the mask lengthRm VD/ID measured resistance Lm/ (µW Cox’ (Vg-Vt)) - L/ µW Cox’ (Vg-Vt)Masured Resistance, RmTERADA-MUTA METHOD FOR EXTRACTING Leff and RdsVg -6Vg -8Vg -10RdsLm (mask length)Lso measure Rm for different channel length transistors and plot Rm vs Lmwhere Rm intersect find value for L and RdsThen Leff can be calculated for each different length transistorfrom Leff Lm - LRochester Institute of TechnologyMicroelectronic Engineering December 22, 2013 Dr. Lynn FullerPage 21
RIT MOSFET SPICE Parameters2nd GENERATION MODELS EQUATIONS FOR MOBILITYThe mobility used in the equations for Ids is the effective mobility ,Ueff. Starting with UO from level 1, Ueff is found. The parameterTHETA is introduced to model mobility degradation due to highvertical electric fields (larger values of Vgs - VTO).Ueff* UO(1 THETA (Vgs-VTO))Measure Ids for a wide transistorwith low value of Vds and largevalue of Vgs and using Leff fromTerata-Muta method andLAMBDA from level 1, calculateTHETA from these two equations.Idsat Ueff W Cox’ (Vg-Vt)2 (1 Vds)2LeffRochester Instituteof TechnologyWarning:Curvaturealso due to RDS so Vds is (Vapplied – Rds*Idsat)Microelectronic Engineeringrequires an iterative approach to find THETA December 22, 2013 Dr. Lynn FullerPage 22
RIT MOSFET SPICE Parameters2ND GENERATION EQUATIONS FOR MOBILITY (cont.)The parameter VMAX is introduced to model the decrease in mobilityat higher Vds due to velocity saturation. Ideally, carrier velocity isdirectly proportional to the applied electric field. However, at veryhigh lateral electric fields, Ex, this relationship ceases to be accurate the carrier velocity saturates at VMAX.Velocity (cm/sec)VMAXUOUeff 107(1 THETA (Vgs-VTO)) 1 UO106vdeVMAX LeffWhere, Vde min (Vds, Vdsat) UO Ex105103104105Ex(V/cm)Rochester Institute of TechnologyMicroelectronic EngineeringNote: other models (equations) formobility exist and use parameters such asUCRIT, UEXP, ULTRA, ECRIT, ESAT December 22, 2013 Dr. Lynn FullerPage 23
RIT MOSFET SPICE Parameters2ND GENERATION MODEL EUATIONS FOR THRESHOLD VOLTAGEThe parameter ETA is used to describe DIBL (Drain Induced BarrierLowering) resulting in a modification to the LEVEL 1 equation forthreshold voltage.VTO ms-- q NSS/Cox’ -2F -2 (q s NSUB(- 8.14E-22)*ETA VdsCox’Leff 3Rochester Institute of TechnologyMicroelectronic Engineering December 22, 2013 Dr. Lynn FullerPage 24F)0.5/Cox’
RIT MOSFET SPICE Parameters2ND GENERATION EQUATIONS FOR NARROW WIDTHDELTA is introduced to model narrow channel effects on thresholdvoltage. The parameter WD (channel width reduction from drawnvalue) is used to calculate the effective channel width. DELTA isused in the calculation of threshold voltage.q NSUB Xds2DELTA o si 2 PHINote: a dimensionless number typically 3Rochester Institute of TechnologyMicroelectronic Engineering December 22, 2013 Dr. Lynn FullerPage 25
RIT MOSFET SPICE Parameters2ND GENERATION EQUATIONS FOR CHANNELLENGTH MODULATIONKAPPA is channel length modulation parameter.KAPPA is calculated [(qNsub/(2 o r))((1-Idsat/Id')(L-2LD-Xdso-Xds)) 2)/(Vd2-Vdsat)] 0.5Measure Id’ at large Vds, and Idsat at Vdsat,Kappa has units of 1/V typical value 0.1VsLdVgLd IdsVdnnL- LLVd2VdsatXdsoXdspId’IdsatSaturation Region 5 4 Vgs 3 2 VdsVdsat Vd2Rochester Institute of TechnologyMicroelectronic Engineering December 22, 2013 Dr. Lynn FullerPage 26
RIT MOSFET SPICE ParametersPARAMETERS FOR SPICE LEVEL 3SPICE LEVEL 3 MODEL PARAMETERS FOR MOS TRANSISTORS:ControlLevel 3ProcessTPG 11 if gate is doped opposite of channel, -1 if notProcessTOXGate Oxide ThicknessProcessNSUBChannel doping concentrationProcessXJDrain/Source Junction DepthProcessPBPB is the junction built in voltageW and LLDDrain/Source Lateral DiffusionW and LWDDecrease in Width from Drawn ValueDCUOZero Bias Low Field MobilityDCVTOMeasured threshold voltage, long wide devicesDCTHETAGate Field Induced Mobility ReductionDCDELTANarrow Channel Effect on the Threshold VoltageDCVMAXMaximum Carrier VelocityDCETADIBL CoefficientDCKAPPAChannel Length Modulation Effect on IdsDCNFSSurface State DensityRochesterInstitute of TechnologyMicroelectronic Engineering December 22, 2013 Dr. Lynn FullerPage 27
RIT MOSFET SPICE ParametersPARAMETERS FOR SPICE LEVEL 3Diode & Resistor RSDiode & Resistor RDACCGDOACCGSOACCGBOACCJTemp- moreNoise- moreTunneling-moreSource Series ResistanceDrain Series ResistanceZero Bias Gate-Source CapacitanceZero Bias Gate-Drain CapacitanceZero Bias Gate-Substrate CapacitanceRochester Institute of TechnologyMicroelectronic Engineering December 22, 2013 Dr. Lynn FullerPage 28
RIT MOSFET SPICE ParametersBSIM3 MODELSBerkeley SPICE third generation SPICE models are called BSIM3.Theses models for transistors use equations that are continuousover the entire range of operation (sub-threshold, linear region andsaturation region). The equations for mobility are improved.Equations for temperature variation, stress effects, noise, tunnelinghave been added and/or improved. BSIM3 is presently the industrystandard among all these models. It represents a MOSFET withmany electrical and structural parameters, among which, only Wand L are under the control of a circuit designer. All the rest arefixed for all MOSFETs integrated in a given fabricationtechnology, and are provided to the designer as an “untouchable"deck of device parameters. (There are over 200 parameters insome versions of BISM3 models)Rochester Institute of TechnologyMicroelectronic Engineering December 22, 2013 Dr. Lynn FullerPage 29
RIT MOSFET SPICE ParametersSPICE LEVEL-49 EQUATIONS FOR VTNote: Vth0 is from Level 1 equationRochester Institute of TechnologyMicroelectronic Engineering December 22, 2013 Dr. Lynn FullerUTMOST III Modeling Manual-Vol.1.Ch. 5. from Silvaco International.Page 30
RIT MOSFET SPICE ParametersSPICE LEVEL-49 EQUATIONS FOR UOUA, UB and UC are emperically fit and replace THETA and VMAX used in LEVEL 3n 1 NFACTOR *Cd/COX ((CDSC CDSCD*Vds CDSCB*Vbseff) – (exp(-DVT1*Leff/2lt) 2exp(-DVT1*Leff/lt)))/COX CIT/C0XRochester Institute of TechnologyMicroelectronic Engineering December 22, 2013 Dr. Lynn FullerUTMOST III Modeling Manual-Vol.1.Ch. 5. from Silvaco International.Page 31
RIT MOSFET SPICE ParametersSPICE LEVEL-49 EQUATIONS FOR IDRochester Institute of TechnologyMicroelectronic Engineering December 22, 2013 Dr. Lynn FullerUTMOST III Modeling Manual-Vol.1.Ch. 5. from Silvaco International.Page 32
RIT MOSFET SPICE ParametersSPICE LEVEL-49 EQUATIONS FOR ID (cont)Rochester Institute of TechnologyMicroelectronic Engineering December 22, 2013 Dr. Lynn FullerUTMOST III Modeling Manual-Vol.1.Ch. 5. from Silvaco International.Page 33
RIT MOSFET SPICE ParametersPARAMETERS FOR SPICE BSIM3 LEVEL 49SPICE BSIM3 LEVEL 49 MODEL PARAMETERS FOR MOS TRANSISTORS:ControlLEVEL 49ControlMOBMOD 1Mobility model selector choiceControlCAPMOD 1Capacitor model selector choiceProcessTOXGate Oxide ThicknessProcessXJDrain/Source Junction DepthProcessNCHChannel Surface doping concentrationProcessNSUBChannel doping concentrationProcessXTDistance into the well where NCH is validProcessNSFFast Surface State DensityProcessNGATEGate Doping ConcentrationW and LWINTIsolation Reduction of Channel WidthW and LLINTSource/Drain Underdiffusion of GateRochester Institute of TechnologyMicroelectronic EngineeringNote: only some of the few hundred parameters December 22, 2013 Dr. Lynn FullerPage 34
RIT MOSFET SPICE ParametersPARAMETERS FOR SPICE BSIM3 LEVEL 49DCVTH0DCU0DCPCLMDiode & Resistor RSHDiode & Resistor JSDiode & Resistor JSWDiode & Resistor CJDiode & Resistor MJDiode & Resistor PBDiode & Resistor CJSWDiode & Resistor MJSWACCGSOACCGDOACCGBOThreshold voltage, Long, Wide Device, Zero SubstrateBias VTO in level 3Low Field Mobility, UO in level 3Channel Length Modulation ParameterDrain/Source sheet ResistanceBottom junction saturation current per unit areaSide wall junction saturation current per unit lengthBottom Junction Capacitance per unit area at zero biasBottom Junction Capacitance Grading CoeficientPB is the junction built in voltageSide Wall Junction Capacitance per meter of lengthSide Wall Junction Capacitance Grading CoeficientZero Bias Gate-Source Capacitance per meter of gate WZero Bias Gate-Drain Capacitance per meter of gate WZero Bias Gate-Substrate Capacitance per meter of gate LRochester Institute of TechnologyMicroelectronic EngineeringNote: only some of the few hundred parameters December 22, 2013 Dr. Lynn FullerPage 35
RIT MOSFET SPICE ParametersEXCEL SPREADSHEET SPICE PARAMETERCALCULATORSPICE Parameter Calculator.xlsRochester Institute of TechnologyMicroelectronic Engineering December 22, 2013 Dr. Lynn FullerPage 36
RIT MOSFET SPICE ParametersINPUTS AND RESULTSRochester Institute of TechnologyMicroelectronic Engineering December 22, 2013 Dr. Lynn FullerPage 37
RIT MOSFET SPICE ParametersPARAMETERS FOR SPICE LEVEL 1Rochester Institute of TechnologyMicroelectronic Engineering December 22, 2013 Dr. Lynn FullerPage 38
RIT MOSFET SPICE ParametersPARAMETERS FOR SPICE LEVEL 3Rochester Institute of TechnologyMicroelectronic Engineering December 22, 2013 Dr. Lynn FullerPage 39
RIT MOSFET SPICE ParametersPARAMETERS FOR SPICE LEVEL 49Rochester Institute of TechnologyMicroelectronic Engineering December 22, 2013 Dr. Lynn FullerPage 40
RIT MOSFET SPICE ParametersRESULTS USING SPICE LEVELS 49, 3, 1Rochester Institute of TechnologyMicroelectronic Engineering December 22, 2013 Dr. Lynn FullerPage 41
RIT MOSFET SPICE ParametersSILVACO ATHENA SIMULATIONS OF D/S IMPLANTRochester Institute of TechnologyMicroelectronic Engineering December 22, 2013 Dr. Lynn FullerPage 42
RIT MOSFET SPICE ParametersSILVACO ATHENA (SUPREM)go athena# set gridline x loc 0.0 spac 0.1line x loc 1.0 spac 0.05line x loc 10.0 spac 0.05line x loc 12.0 spac 0.1line y loc 0.0 spac 0.01line y loc 2.2 spac 0.01line y loc 3.5 spac 0.3line y loc 6.0 spac 0.5Starting wafer resistivity 11.3 ohm-cminit silicon phosphor resistivity 11.3 orientation 100 space.mult 5.0# ramp up from 800 to 900 c soak 50 min dry o2, ramp down to 800 n2diff time 10 temp 800 t.final 900 dryo2 press 1.0 hcl.pc 0diff time 50 temp 900 weto2 press 1.0 hcl.pc 0diff time 20 temp 900 t.final 800 nitro press 1.0 hcl.pc 0deposit photoresist thickness 1.0etch phtotoresist left ;1.x 2.0etch photoresist right p1.x 10.00Grow Kooi oxide 1000 ÅIon Implant P-type D/S at Dose 1E15# ion implant drain and sourceimplant boron dose 1e15 energy 70 tilt 0 rotation 0 crysatal lat.ratio1 1.0 lat.ratio2 1.0Etch photoresist allStrip photoresist# ramp up from 800 to 1000 c soak 90 min, ramp down to 800 n2diff time 20 temp 800 t.final 1000 nitro press 1.0 hcl.pc 0diff time 90 temp 1000 nitro press 1.0 hcl.pc 0diff time 40 temp 1000t.final 800nitro press 1.0 hcl.pc 0Rochester Instituteof TechnologyAnneal D/S implantMicroelectronic Engineering December 22, 2013 Dr. Lynn FullerPage 43
RIT MOSFET SPICE ParametersSILVACO ATHENA (SUPREM)Ion Implant P-type channel atDose 0, 4e11, 1e12, 4e12# ion implant channelimplant boron dose 4e12 energy 60 tilt 0 rotation 0 crysatal lat.ratio1 1.0 lat.ratio2 1.0etch oxide all# ramp up from 800 to 1000 c soak 90 min dry o2, ramp down to 800 n2diff time 20 temp 800 t.final 1000 dryo2 press 1.0 hcl.pc 0diff time 90 temp 1000 dryo2 press 1.0 hcl.pc 0diff time 40 temp 1000 t.final 800 nitro press 1.0 hcl.pc 0deposit nitride thick 0.010Deposit 100 Å nitride# ramp up from 800 to 1000 c soak 50 min dry o2, ramp down to 800 n2diff time 10 temp 800 t.final 1000 dryo2 press 1.0 hcl.pc 0diff time 50 temp 1000 dryo2 press 1.0 hcl.pc 0diff time 20 temp 1000 t.final 800 nitro press 1.0 hcl.pc 0deposit oxynitride thick 0.01Grow 700 Å gate oxideTemp cycle for growth ofoxynitrideDeposit 100 Å oxynitridedeposit poly thick 0.60 c.boron 4e20Deposit 6000 Å poly# ramp up from 800 to 1000 c soak 30 min, ramp down to 800 n2diff time 20 temp 800 t.final 1000 nitro press 1.0 hcl.pc 0diff time 30 temp 1000 nitro press 1.0 hcl.pc 0diff time 40 temp 1000 t.final 800 nitro press 1.0 hcl.pc 0Temp cycle for poly dopeRochester Institute of TechnologyMicroelectronic Engineering December 22, 2013 Dr. Lynn FullerPage 44
RIT MOSFET SPICE ParametersSILVACO ATHENA (SUPREM)etch poly left p1.x 1.5etch poly right p1.x 10.5etch oxynitride left p1.x 1.5etch oxynitride right p1.x 10.5etch nitride left p1.x 1.5etch nitride right p1.x 10.5etch oxide left p1.x 1.5etch oxide right p1.x 10.5deposit alumin thick 0.5Deposit 5000 Å aluminumetch alum start x 1.0 y -2.0etch cont x 1.0 y 2.0etch x 11.0 y 2.0etch done x 11.0 y -2.0struct outfile UofH.strtonyplot UofH.strquitRochester Institute of TechnologyMicroelectronic Engineering December 22, 2013 Dr. Lynn FullerTonyplot example OnlyPage 45
RIT MOSFET SPICE ParametersSILVACO ATHENA (SUPREM)Channel Implant Dose 0Crossection of MOSFETChannel Doping Profile 11x2yyRochester Institute of TechnologyMicroelectronic Engineering December 22, 2013 Dr. Lynn FullerPage 46
RIT MOSFET SPICE ParametersSILVACO ATHENA (SUPREM)D/S Doping Profile 2Channel Implant Dose 0Channel Doping Profile 3yyRochester Institute of TechnologyMicroelectronic Engineering December 22, 2013 Dr. Lynn FullerPage 47
RIT MOSFET SPICE ParametersSILVACO ATLAS (DEVICE SIMULATOR)Go athenaInit infile UofH.strRead in structure file created by Athena#name the electrodes Electrode name gate x 6Electrode name source x 0Electrode name drain x 12Electrode name substrate backsideDefine location of gate, source, drain and substrateExtract name “vt” 1dvt ptype qss 1e11 workfunc 5.1 x.val 6Go atlas# define the gate workfunctionContact name gate p.poly# define the Gate qssInterface qf 1e11# use the cvt mobility model for MOSModels cvt srh# set gate biases with Vds 0.0Solve initSolve vgate 0 vsubstrate 0 outf solve temp0Solve vgate -1 vsubstrate 0 outf solve temp1Solve vgate -1 vsubstrate 0 outf solve temp2Solve vgate -3 vsubstrate 0 outf solve temp3Solve vgate -4 vsubstrate 0 outf solve temp4Solve vgate -5 vsubstrate 0 outf solve temp5Do calculations for given gate voltage andsubstrate voltage (Vg 0,-1,-2,-3,-4,-5 andVsub 0, 5, 10 15)# load in temporary file and ramp VdsRochester Institute of TechnologyLoad infile solve temp0Microelectronic EngineeringLog outf Vg 0.logSolve name drain vdrain 0 vfinal -5 vstep -0.5Sweep drain voltage from 0 to –5 voltsIn –0.5 volt steps December 22, 2013 Dr. Lynn FullerPage 48
RIT MOSFET SPICE ParametersSILVACO ATLAS (DEVICE SIMULATOR# load in temporary file and ramp vdsload infile solve temp1log outf vg 1.logsolve name drain vdrain 0 vfinal -5 vstep -0.5# load in temporary file and ramp vdsload infile solve temp2log outf vg 2.logsolve name drain vdrain 0 vfinal -5 vstep -0.5# load in temporary file and ramp vdsload infile solve temp3log outf vg 3.logsolve name drain vdrain 0 vfinal -5 vstep -0.5# load in temporary file and ramp vdsload infile solve temp4log outf vg 4.logsolve name drain vdrain 0 vfinal -5 vstep -0.5Sweep drain voltage from 0 to –5 voltsin -0.5 volt steps# load in temporary file and ramp vdsload infile solve temp5log outf vg 5.logsolve name drain vdrain 0 vfinal -5 vstep -0.5# extract max current and saturation slopeextract name “pidsmax” max(abs(i.”drain”))extract name “p sat slope” slope(minslope(curve(abs(v.”drain”), abs(i.”drain”)))tonyplot –overlay vg 0.log vg 1.log vg 2.log vg 3.log vg 4.log vg 5.log –setmos1ex09 1.setquitRochester Institute of TechnologyMicroelectronic Engineering December 22, 2013 Dr. Lynn FullerPage 49
RIT MOSFET SPICE ParametersATLAS SIMULATED FAMILY OF CURVESChannel ImplantDose noneVsub 0-1-2-3-4Vgs -5Rochester Institute of TechnologyMicroelectronic Engineering December 22, 2013 Dr. Lynn FullerPage 50
RIT MOSFET SPICE ParametersSILVACO ATHENA ATLAS UTMOST SPICEUTMOST GeneratesSPICE model parametersfrom ATLAS output file.Rochester Institute of TechnologyMicroelectronic Engineering December 22, 2013 Dr. Lynn FullerPage 51
RIT MOSFET SPICE ParametersSILVACO ATHENA GENERATED IMPURITY PROFILESRochester Institute of TechnologyMicroelectronic Engineering December 22, 2013 Dr. Lynn FullerPage 52
RIT MOSFET SPICE ParametersATLAS GENERATED DEVICE CHARACTERISTICSRochester Institute of TechnologyMicroelectronic Engineering December 22, 2013 Dr. Lynn FullerPage 53
RIT MOSFET SPICE ParametersUTMOST GENEREATED SPICE PARAMETERSNMOS PARAMETER DECK:*2-27-2007 UTMOST EXTRACTIONS.MODEL CMOSN NMOS (LEVEL 49VERSION 3.1 CAPMOD 2 MOBMOD 1 TOX 328.4E-10 XJ 3.5E-7 NCH 7.0E19VTH0 0.8627 K1 0.5 K2 -0.0186 K3 80 WO 2.5E-6 NLX 1.740E-7 DVT0W 0DVT1W 0 DVT2W -0.032 DVT0 2.2 DVT1 0.53 DVT2 0.1394 U0 670 UA 2.25E-9UB 5.87E-19 UC -4.65E-11 VSAT 80000 A0 1 AGS 0 B0 0 B1 0 KETA -0.047A1 0 A2 1 RDSW 0 PRWG 0 PRWB 0 WR 1 WINT 2.58E-8 LINT 1.86E-8 XL 0XW 0 DWG 0 DWB 0 VOFF -0.06464 NFACTOR 1.3336 CIT 0 CDSC 0.00024CDSCD 0 CDSCB-0 ETA0 0.08 ETAB -0.07 DSUB 0.56 PCLM 1.39267PDIBLC1 0.39 PDIBLC2 0.0086 PDIBLCB 0 DROUT 0.19093 PSCBE1 4.00E8PSCBE2 6E-6 PVAG 0 DEL
Rochester Institute of Technology 12 Microelectronic Engineering ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING SPICE Model Parameters for RIT MOSFET’s Dr. Lynn Fuller Microelectronic Engineering Rochester Institute of Technology 82 Lomb Memorial Drive Roche
RIT MOSFET SPICE Parameters Page 11 Rochester Institute of Technology Microelectronic Engineering SPICE LEVEL-1 PARAMETERS FOR MOSFET (cont.) 1. LEVEL 1 Shichman-Hodges Model (If not specified the default is LEVEL 1) 2. VTO zero bias threshold voltage (Do not use, let SPICE calculate from Nsub,TOX
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components. These are SPICE models of diode, MOSFET, BJT, and JFET. In SPICE manuals more detailed explanations of these models and model card parameters can be found. Nevertheless, there are different versions of SPICE, and we hope this list of model card parameters can be useful to determine which version of SPICE model is implemented in Alecsis.
–common semiconductor devices: diode, BJT, FET Advanced Topics in VLSI Systems 3 . SPICE History . 1976 SPICE 2D New MOS Models 1979 SPICE 2E Device Levels (R. Newton appears) 1980 SPICE 2G Pivoting (ASV appears) Advanced Topics in VLSI Systems . 4 . SPICE History
This is designed for integrated circuit design with special device models. Œ RAD-SPICE Š supplied by Meta-Software. This is for simulating circuits subjected to ionizing radiation. Œ IG-SPICE Œ supplied by A. B. Associates. Œ Cadence-SPICE Š supplied by Cadence Design Œ SPICE-Plus Š supplied by Valid Logic 6 What is SPICE OPUS ?
.lib .sub .mod 1.1.1 Schnelle Lösung mit Spice-Text in Simulationsoberfläche Für die schnelle Anwendung wird einfach die Spice-Datei als Spice-Befehl in die Schema-tic-Oberfläche hineinkopiert, siehe nachfolgende Abbildung Abb. 1.2: Abb. 1.2: Spice-Modelldatei als Spice-Directive hineinkopiert in die Simulationsoberfläche. Man
Bruksanvisning för bilstereo . Bruksanvisning for bilstereo . Instrukcja obsługi samochodowego odtwarzacza stereo . Operating Instructions for Car Stereo . 610-104 . SV . Bruksanvisning i original
UM1575 Spice models - instructions to simulate 24 3 Spice models - instructions to simulate In Spice simulator, user has to upload the device symbol (.OLB file) and the Spice model (.LIB file) to simulate transistors in the schematic. 3.1 Installation In the package model, there are the following files: name.lib text file representing the .
