CPU / GPU TECHNOLOGIES NOW AND FUTURE

CPU / GPU TECHNOLOGIESNOW AND FUTUREAndré HeidekrügerSr. Technical ConsultantPresales EMEA1 HPC Advisory Council Lugano

A CASE FOR SERVER FUSION - EXASCALE Current trajectory puts traditional x86 computing at just over 20Pflops by 2018 A data center that could achieve an exaflop in 2018 using only x86 processors would consume over3TW To achieve exascale capability by 2018, x86 performance would need to increase by 2x each year,starting in 20101.00E 19EXAFLOP1.00E 18500PF100PF1.00E 1750PF20PF1.00E 161.00E 152 HPC Advisory Council LuganoHeterogeneouscompute required tobridge the gapExascale Target@30% upliftHomogeneousx86 computehits a wall

HIGH EFFICIENCY LINPACK IMPLEMENTATIONON AMD MAGNY COURS AMD 5870 GPUSystem GFLOPSDGEMM/nodeLinpack/nodeLinpack/4 nodes05001000 GPU DPFP Peak: 544 GFLOPS GPU DGEMM kernel: 87% of Peak2.5 GFLOPS/W Node DPFP Peak: 745.6 GFLOPS Linpack efficiency: 75.5% of Peak Linpack scaling across 4 nodes: 70% of Peak3 HPC Advisory Council Lugano150020002500HPL code:http://code.compeng.uni-frankfurt.de/

AMD PROCESSOR POWER AND PERFORMANCE OVER TIMEINCREASING PERFORMANCE-PER-WATT EFFICIENCIESAdvanced Platform Management LinkAMD CoolSpeed TechnologyC1E power-stateDDR3 LV MemoryAMD PowerCap ManagerAMD SmartFetch TechnologyAMD CoolCore Technology on L3AMD CoolCore TechnologyDual Dynamic Power ManagementIndependent Dynamic Core EngagementAMD PowerNow! TechnologyIntegrated Memory ControllerSPEC, SPECint, and SPECfp are registered trademarks of the Standard Performance Evaluation Corporation. The comparison presented above is based on the best performing two-socketservers using the specified processor model. For the latest SPECint rate2006 and SPECfp rate2006 results, visit ” performance based on internal AMD estimates4 HPC Advisory Council Lugano

TECHNOLOGY COMPARISONSCompared to how the current architecture handles two threads,“Bulldozer” can deliver more performance in a smaller die space5 HPC Advisory Council Lugano

SHARING RESOURCESHELPING TO MAXIMIZE POWER EFFICIENCY AND COSTThe “Bulldozer” module has shared anddedicated componentsDedicatedComponentsShared at themodule levelShared atthe chip levelFetchThe shared components:DecodeL1 DCacheL1 DCacheShared L2 CacheShared L3 Cache and NB6 HPC Advisory Council LuganoPipelinePipelinePipeline128-bit FMACPipelinePipelinePipelinePipelineCore 2128-bit FMAC“Bulldozer” dynamically switchesbetween shared and dedicatedcomponents to maximize performanceper wattIntSchedulerCore 1The dedicated components: Help increase performance andscalabilityFPSchedulerIntSchedulerPipeline Help reduce power consumption Help reduce die space (cost)

CORE MICROARCHITECTURE – SHARED FPUFetch QueueL2 BTBUcode ROM PRF-based registerrenaming Unified scheduler (forboth threads)7 HPC Advisory Council LuganoLd/ST Unit L1 DTLB L1 DCacheData PrefetcherFP Ld BufferAGenAGenEX, DIVInstrRetireEX, MULIntSchedulerFP Scheduler128-bitFMACAGenAGenEX, DIVInstrRetireEX, MULIntScheduler4 x86 Decoders128-bitFMAC Dual 128-bit FMACpipesMMX Reports completionback to parent core Dual 128-bit packedinteger pipesICacheL1 BTBMMX Co-processororganizationPrediction QueueLd/ST Unit L1 DTLB L1 DCacheShared L2 Cache

THREAD CONTROL AND SELECTION MECHANISMSVertical MTEach core is logical processor from viewpoint of softwareSingle ThreadSMT/ thread agnosticSC tchthreaddomainReq QCorePredQBPThreaddomain8 HPC Advisory Council LuganoFPfrontendSC QFPExecutionRetQsFPbackendL2/CU

POWER EFFICIENCY AND APM Start with inherently powerefficient micro-architectureand implementation:Power consumption varies greatly by workload90%– Dynamic sharing of sharedresources80%– Minimize data movement70%– Extensive clock and power gating– Digitally measure activity toestimate power– Hardware uses higher frequencywhen power limit allows Support for chip-level corepower gatingPercent of TDP Add active managementsupport:60%50%40%30%20%Power Headroom that canbe utilized per core.10%0%* Based on internal AMD modeling using benchmark simulations9 HPC Advisory Council Lugano

BUILDING A “BULLDOZER” PROCESSORServer:“Interlagos” –16 cores (2 dies)“Valencia” –8 cores (1 die)Client:“Zambezi” –8 cores (1 die)10 HPC Advisory Council LuganoMemory ControllerShared L3 CacheEach processor die is composed ofmultiple “Bulldozer” modulesModule divisions are transparent toshared hardware, operating system orapplicationThe modular architecture speeds chipdevelopment and increases productflexibilityNB/HT Links

NEW “BULLDOZER” INSTRUCTIONSRequire a recompileRequire no recompileInstruction11DescriptionSSSE3Supplemental Streaming SIMD Extensions 3 (SSSE3) is a SIMD instruction set. It contains 16discrete instructions; because each can act on 64-bit MMX or 128-bit XMM registers itrepresents a total of 32 instructions.SSE 4.1A set of 47 instructions that execute operations which are not specific to multimediaapplications. It features a number of instructions whose action is determined by a constant fieldand a set of instructions that take XMM0 as an implicit third operand.SSE 4.2An additional 7 instructions that are incremental to SSE 4.1, including 4 very powerful andgeneric string compare operations.AES and PCMULQDQAdvanced Encryption Standard (AES) Instruction Set is an extension to the x86 instruction setarchitecture. It helps improve the speed of applications performing encryption and decryptionusing the Advanced Encryption Standard (AES).AVXThe size of the SIMD vector registers is increased from 128-bits XMM registers to 256-bitsregisters called YMM0 - YMM15. Existing 128-bit instructions use the lower half of the YMMregisters. The AVX instruction set allows all two-operand XMM instructions to be modified intonon-destructive three-operand forms where the destination register is different from both sourceregisters.FMA4The FMA instruction set is a extension to the 128-bit and 256-bit SIMD instructions in the X86microprocessor instruction set to perform fused multiply-add operations.XOPXOP makes the binary coding of new instructions more compatible with Intel's AVX instructionextensions, while the functionality of the instructions is unchanged. HPC Advisory Council Lugano

“BULLDOZER”: FLEX FP OPERATING MODESLegacyCore 1AVXCore 2AVXLegacyAVXAVXCore 1 single precision480Core 1 double precision240Core 2 single precision408Core 2 double precision204FLOPs/Cycle (16 cores)646464Recompiled app?NoYesYesMode12 HPC Advisory Council Lugano

GENERATIONAL COMPARISONSAMD Opteron 4100/6100Series Processors“Valencia” / “Interlagos”Cores4100: 4 or 6 core; 6100: 8 or 12 core4200: 6 or 8 core; 6200: 8, 12 or 16 coreCache (L2 per core / L3 perdie)512KB / 6MB2MB (shared between 2 cores) / 8MBMemory Channels and speed4100: two; 6100: four; up to 1333MHz4200: two; 6200: four; up to 1600MHzFloating point capability128-bit FPU per core (FADD/FMUL)128-bit dedicated FMAC per core or 256-bit AVXshared between 2 coresInteger Issues Per Cycle34Turbo CORE TechnologyNoYes ( 500MHz with all cores active)Power (ACP)65W, 80W, 105WTBD (planned 65W, 80W, 105W)SSSE3, SSE 4.1/4.2, AVX, AES, FMA4, XOP,PCLMULQDQNew Instruction SetsPower GatingAMD CoolCore , C1EAMD CoolCore , C1E, C6Process / Die Size45nm SOI32nm SOI (smaller overall die size)PerformanceExpected up to 50% higher throughputThe above reflect current expectations regarding features and performance and is subject to change13 HPC Advisory Council Lugano

AMD AND GPU COMPUTING: PIONEERING INNOVATIONFirstDevelopmentPlatformFirst with DoublePrecisionFirst to1 TFLOPS,First OpenCL CPUIndustry’s first doubleprecision GPU:AMD FireStream 9170First to 1 TFLOPSFirst single slot:AMD FireStream 9250First onTop 500’sTop TenTianhe-1Top500 #5Second GenerationSingle SlotFireStream 9350ATI Stream SDKFireStream 9370Stream ComputingDevelopment PlatformCTM SDK200614Industry StandardAPI: OpenCLannounced2007 HPC Advisory Council Lugano2008FireStream 927020092010

AMD FIRESTREAM GPU ACCELERATORSSOLUTIONS OPTIMIZED FOR PERFORMANCE, POWER AND DENSITYMaximum Performance- Fastest memory technology- Large memoryDeployable Performance- Highest performance per watt anddensity- Low power- Low profile- Optimal price/performance15 HPC Advisory Council LuganoAMD FireStream 9370- 2.64 TFLOPS- 528 GFLOPS DPFP- 4GB GDDR5- 225W- Passive heat sinkAMD FireStream 9350- 2.0 TFLOPS- 400 GFLOPS DPFP- 2GB GDDR5- Single slot, 150W- Passive heat sink

ATI RADEON HD 5870 (“CYPRESS”) 1600 Stream Processors 20 SIMD engines 2.72 TFLOPs SP 544 GFLOPs DP16 HPC Advisory Council Lugano

OPENCL DEVICE EXAMPLE ATI Radeon HD 5870 GPU1 Compute UnitContains 16 StreamCores1 Stream Core 5Processing Elements17 HPC Advisory Council Lugano

AMD RADEON HD 6900 SERIES Dual graphics engines New VLIW4 core architecture More SIMD engines and textureunits Over 5 Gbps 1536 Stream Processors 2.7 TFLOPs SP 683 GFLOPs DP18 HPC Advisory Council Lugano

NEW CORE DESIGN VLIW4 thread processors– 4-way co-issue– All stream processing units now haveequal capabilities (no more “T-unit”) Special functions (transcendentals) occupy3 of 4 issue slots Allow better utilization than previousVLIW5 design– Similar performance with 10% area reduction– Simplified scheduling and register management– Extensive logic re-use19 HPC Advisory Council LuganoStream Processing UnitsFP ops per clockInteger ops per clock4 32-bit MAD2 64-bit MUL or ADD1 64-bit MAD or FMA1 Special Function4 24-bit MUL, ADD or MAD2 32-bit ADD1 32-bit MUL

GPU COMPUTE ENHANCEMENTS Asynchronous dispatch– Execute multiple compute kernels simultaneously– Each kernel has its own command queue andprotected virtual address domain Dual bidirectional DMA engines forfaster system memory reads & writes Coalescing of shader read ops Fetch direct to LDS Improved flow control Faster double precision ops (1/4 SPrate)20 HPC Advisory Council Lugano

UPCOMING POWER CONTAINMENT FEATURE DRIVES GPUPERFORMANCE EFFICIENCY Clamps GPU TDP to a pre-determined level Integrated power control processor monitorspower draw every clock cycle–Dynamically adjusts clocks for various blocks to enforce TDP No longer need to constrain clocks speedsto allow for outlier applications User controllable via AMD OverDrive Utility2121 HPC Advisory Council LuganoNote: See slide 34 for additional information

POWER CONTAINMENTHigh peak powerUnconstrained powerScaled powerPower containmentPowerLower peak powerFast completionSlower completionTime22 HPC Advisory Council LuganoTheoretical example only

NOW THE AMD FUSION ERA OF COMPUTING BEGINS APU: Fusion of CPU & GPU compute power within one processor High-bandwidth I/O23 HPC Advisory Council Lugano

Fusion APU Based PC24 HPC Advisory Council Lugano