Integrated Circuit Reliability Prediction Based On Physics .
1Integrated Circuit Reliability Prediction Based on Physicsof-Failure Models in Conjunction With Field StudyAvshalom Hava, Edward Wyrwas, Jin Qin, Lloyd Condra, Joseph B. Bernstein Abstract—Reliability models, based on physics-of-failuremechanisms, have been developed for dynamic random accessmemories (DRAM), microcontrollers and microprocessorsusing a new software tool. Field data from a large fleet ofmobile communications products, that were deployed over aperiod of 8 years, were analyzed to validate the tool’saccuracy. Strong correlation of 80% is demonstrated betweenmeasured and predicted values.Index Terms—Failure Rate, Physics-of-Failure, Reliability,SimulationI. INTRODUCTIONTHE continued scaling down of semiconductor feature sizesraises challenges in using and developing electronic circuitreliability predictions. Smaller and faster circuits cause highercurrent densities, lower voltage tolerances and higher electricfields, which make the devices more vulnerable to earlyfailure. Emerging new generations of electronic devicesrequire improved tools for reliability prediction in order toinvestigate new manifestations of existing failure mechanisms,such as Negative Bias Temperature Instability (NBTI),Electromigration (EM), Hot Carrier Injection (HCI) and TimeDependent Dielectric Breakdown (TDDB).Reliability prediction simulations are the most powerfultools developed over the years to cope with these challengingdemands. Simulations may provide a wide range ofpredictions, starting from the lower-level treatment of physicsof-failure (PoF) mechanisms up to high-level simulations ofentire devices [1]-[2]. As with all simulation problems,primary questions need to be answered: “How accurate are thesimulation results in conjunction to the real world? What is theconfidence level achieved by the simulations?” Hence, the Manuscript received xxx x, 2010.Avshalom Hava is with Motorola Solutions, Tel-Aviv 67899, Israel.(Phone: 972-3-6256366; Fax: 972-3-6256396; e-mail: Avshalom@Motorolasolutions.com). "MOTOROLA and the Stylized M Logo areregistered in the US Patent & Trademark Office. All other product or servicenames are the property of their respective owners. Motorola, Inc. 2010"Edward Wyrwas is with DfR Solutions, 9000 Virginia Manor RdBeltsville, MD 20705 (e-mail: ewyrwas@dfrsolutions.com)Jin Qin is a professor at University of Science and Technology of China,Hefei 230026, China (e-mail: qjin@ustc.edu.cn)Lloyd Condra is with Boeing Research and Technology, Seattle,Washington, USA (e-mail: lloyd.w.condra@boeing.com)David Redman is with Aerospace Vehicle Systems Institute (AVSI),College Station, Texas (e-mail: dredman@avsi.aero)Joseph B. Bernstein is a professor at Bar Ilan University, Ramat-Gan52900, Israel. (e-mail: bernstj@macs.biu.ac.il)validation and calibration of the simulation tools becomes amost critical task. Reliability data generated from field failuresbest represents the electronic circuit reliability in the contextof the target system or application. Field failure rates representcompeting failure mechanisms' effects and include actualstresses, in contrast to standard industry accelerated life tests.In this paper, we present a thorough reliability analysis offield failure data recorded from 2002 to 2009 in order togenerate real failure rates for various device processtechnologies and feature sizes (or “technology nodes”). Theresults of this analysis are used to verify PoF models and acompeting failure approach, as implemented in new reliabilityprediction methods - FaRBS (Failure rate based SPICE) andMaCRO (Maryland Circuit Reliability-Oriented) combinedinto one software tool [3]. Comparison of actual and simulatedfailure rates shows a strong correlation of 80%. The validationprocess and its data sources are illustrated in Figure RComparisonModelsValidation &OptimizationFigure 1. The data sources used for IC reliability prediction based PoFmodels and simulation validation. Actual field data is confronted with twoprimary approaches used by industry to predict failure rates.II. RELIABILITY MODELING AND SIMULATIONA. HistoryThere has been steady progress over the years in thedevelopment of a physics-of-failure understanding of theeffects that various stress drivers have on semiconductorstructure performance and wearout. This has resulted in bettermodeling and simulation capabilities. Early investigatorssought correlations between the degradation of single devicedfrsolutions.com (301) 474-0607 9000 Virginia Manor Road, Suite 290, Beltsville, Maryland 20705
2parameters (e.g. Vth, Vdd or Isub) and the degradation ofparameters related to circuit performance such as the delaybetween read and write cycles. It was quickly realized that thedegradation of a broad range of parameters describing deviceperformance had to be considered, rather than just a singleparameter [1]. Most of the simulation tools tend to simulate asingle failure mechanism such as Electromigration (EM) [4][5], Time Dependent Dielectric Breakdown (TDDB) [7],Negative Bias Temperature Instability (NBTI) [7]-[8] and HotCarrier Injection (HCI) [9]. System-level simulatorsattempting to integrate several mechanisms into a single modelhave been developed as well. The latest circuit design tools,such as Cadence Ultrasim and Mentor Graphics Eldo, haveintegrated reliability simulators. These simulators model themost significant physical failure mechanisms and helpdesigners address the lifetime performance requirements.However, inadequacies, such as complexity in the simulationof large-scale circuits and a lack of prediction of wearoutmechanisms, hinder broader adoption of these tools [10].B. Validation ConcernsReliability simulations are commonly based on acombination of PoF models, empirical data and statisticalmodels developed over the years by different research groupsand industries. The inevitable consequence of a wide range ofmodels and approaches is a lack of confidence in the obtainedpredictions for any given model. From the point of view of areal-world end-user, single failure mechanism modeling anddegradation simulations are less meaningful then system levelreliability.Validation and calibration of simulations are bothaccomplished by comparing simulation predictions withempirical data obtained from lab tests or by analyzing fielddata.To evaluate the reliability of their devices,semiconductor manufacturers use lab tests such asenvironment stress screens (ESS), highly accelerated lifetimetesting (HALT), HTOL and other accelerated life tests (ALT).III. FAILURE MECHANISMS MODELSThedominantfailuremechanismsin Si-basedmicroelectronic devices that are most commonly simulated areEM, TDDB, NBTI and HCI. Other degradation models doexist but are less prevalent. These mechanisms can begenerally categorized as Steady State Failure Modes (EM andTDDB) and Wearout Failure Modes (NBTI and HCI) [12].Steady state (random) failure modes are normally consideredto be random cases of "stress-exceeding-strength". The hazardfunctions generated by random failure modes are constant overtime and may produce failures during all bathtub curve stages.On the contrary, the wearout failure modes generate increasinghazard function and are predominated in later stages of thedevice life. Wearout failure modes at sub-micron nodes areexperienced earlier in the anticipated life of a device, withinwhat was once thought to be dominated only by the steadystate failure modes. A brief explanation of each failuremechanism is necessary to understand their contribution to theoverall device failure rate.Electromigration can lead to interconnect failure in anintegrated circuit. It is characterized by the migration of metalatoms in a conductor along the direction of the electron flow.Electromigration causes opens or voids in some portions of theconductor and corresponding hillocks in other portions [4]-[5],[11].Time Dependent Dielectric Breakdown is caused bydefect generation and accumulation that reaches a criticaldensity in the oxide film. The underlying process might bedriven by the applied voltage or the tunneling electrons.Damage caused by the accumulated defects will result inperformance degradation and eventual failure of the transistorswithin a device. The gate dielectric breaks down over a longperiod of time for devices with larger feature sizes ( 90 nm)due to a comparatively low electric field. Core voltages havebeen scaled down proportionally to feature sizes, but sincesupply voltages have remained constant, higher electric fieldsexist at smaller feature sizes. Therefore, field strengths arestill a concern since high fields exacerbate the effects ofTDDB [7], [11].Negative Bias Temperature Instability occurs only inpMOS devices stressed with a negative gate bias voltage whileat elevated temperatures. Degradation occurs in the gate oxideregion allowing electrons and holes to become trapped.Negative bias is driven by smaller electric fields than hotcarrier injection, which makes it a more significant threat atsmaller technology nodes where increased electric fields areused in conjunction with smaller gate lengths. The interfacetrap density generated by NBTI is found to be morepronounced with thinner oxides [7]-[8], [11].Hot Carrier Injection occurs in both nMOS and pMOSdevices stressed with drain bias voltages. High electric fieldsenergize the carriers (electrons or holes), which are theninjected into the gate oxide region. Like NBTI, the degradedgate dielectric can then more readily trap electrons or holes,causing a change in threshold voltage, which in turn results ina shift in the subthreshold leakage current. HCI is acceleratedby an increase in bias voltage and is the predominatemechanism at lower stress temperatures [9], [11]. Therefore,hot carrier damage, unlike the other failure mechanisms, willnot be replicated in HTOL tests, which are commonly used foraccelerated life testing [13].IV. THE SIMULATION TOOLA. Mathematical TheoryThe simulation tool used for this research is a web-basedapplication based on recent PoF circuit reliability predictionmethodologies that were developed by the University ofMaryland (UMD) for 130 nm and 90 nm devices [14]. Thetwo methods developed are referred to by the acronyms ofdfrsolutions.com (301) 474-0607 9000 Virginia Manor Road, Suite 290, Beltsville, Maryland 20705
3FaRBS (Failure-Rate-Based SPICE [spacecraft, planet,instrument, C-matrix, events]) and MaCRO (Maryland CircuitReliability-Oriented). FaRBS is a reliability prediction processthat uses accelerated test data and PoF based die-level failuremechanism models to calculate the failure rate of integratedcircuit components. As its name implies, it uses mathematicaltechniques to determine the failure rate of an integrated circuit.MaCRO contains SPICE (Simulation Program with IntegratedCircuit Emphasis) analyses using several different commercialapplications, wearout models, system reliability models,lifetime qualification, and reliability and performance tradeoffsin order to achieve system and device reliability trends,prediction and analysis.The simulation tool can implement two distinct approachesto compute reliabilities: Independent of Transistor Behavior (ITB); Dependent on Transistor Behavior (DTB).These approaches are used to determine each failuremechanism's contribution to circuit level failure through theanalysis of transistor stress states (bottom-up approach). TheITB approach makes two assumptions:(1) In each integrated circuit, each failure mechanism has anequal opportunity to initiate a failure, and(2) each can be initialized at a random interval during thetime of operation.Conversely, DTB takes place in a SPICE simulation todetermine these contributions based on transistor behavior andcircuit function. In a circuit model of a functional group, auser can develop mechanism weighting factors by examiningthe IV curves of each transistor within the circuit. Each failuremechanism is driven by either current or voltage states such asthe presence of a gate bias for Bias Temperature Instability.Assessing each transistor using guidelines determines itssusceptibility to a particular failure mechanism. After acomplete assessment of the circuit, one can tabulate the resultsby summing the total time that the quantity of transistors isaffected by each mechanism and calculate an overallpercentage for each mechanism based on the quantity ofaffected transistors, the total operating time of the analyzedfunctionality, and the total quantity of transistors within thecircuit.For the validation study presented in Section V of thispaper, the ITB approach was used. DTB analysis plays acritical role when analyzing complex functional groups such asprocessor cores; however, the lower transistor count functionalgroups utilized for the validation study did not clearlydelineate a leader in regards to failure mechanisms during theirDTB SPICE analysis.The software assumes that all the parameters for thesemodels are technology node dependent. It is assumed that thetechnology qualification (process qualification) has beenperformed and at least one screening has occurred before adevice is packaged. This reliability prediction covers thesteady-state random failures and wearout portions of thebathtub curve concept.B. Failure Rate CalculationsEach failure mechanism described above would have adegradation rate, i , driven by a combination of temperature,voltage, current, and frequency. Each one affects the on-diecircuitry in its own unique way; therefore, the relativeacceleration of each one must be defined and averaged underthe applied condition. The failure rate contribution of each canbe normalized by taking into account the effect of the weightedpercentage of that failure rate. We ignore interactions betweenfailure mechanisms for practical reasons although deeperstudies of potential interactions could be made in the future.This assumption simplifies the device wearout modelingprocess and eases the calculation of the overall accelerationfactor. It is based on the fact that each failure mechanism hasits specific degradation region inside the transistor. TDDBcauses damage inside the gate oxide, while HCI/NBTIincreases interface trap density. HCI will precipitate theoccurring of TDDB, but the interrelation is very complex andnormally insignificant and negligible [11]. For pMOS, HCIand NBTI have been reported to be independent [12]-[16].For the four mechanisms of EM, HCI, NBTI and TDDB,the normalized failure rate can be defined as EM , HCI , NBTIand TDDB respectively. In order to achieve more accuracy inthe overall failure rate estimation, it is useful to split the ICinto equivalent function sub-circuits and refer to it as a systemof functional group cells, for example: 1 bit of SRAM, 1 bit ofDRAM, one stage of a ring oscillator, and select moduleswithin Analog-to-Digital circuitry (ADC) etc. For eachfunctional group type, the failure rate can be defined as aweighted summation of each failure rate type multiplied by anormalization constant for the specific failure mechanism. 1F Ki ,F i (1)where 1F is the failure rate of one unit of functional group,F . These failure rates are calculated as proportions of theinput ALT failure rate (assuming it is reasonably accurate) andtechnology node dependent acceleration factors using PoFmodels, technology node parameters, and several electrothermal parameters. K i , F is a constant defined by the weightpercentage of functional group F as it is affected by the ithfailure mechanism and i is the normalized failure rate of anyfailure mechanism. Normalization is used to combine thefailure rate contribution of each failure mechanism pertransistor in a functional group across the entire functionalgroup. The K i , F constants are extracted from SPICEsimulation in the DTB approach. The SPICE analysisexamines the individual transistor stress states (i.e. biasvoltage) within each circuit functional group. For example,dfrsolutions.com (301) 474-0607 9000 Virginia Manor Road, Suite 290, Beltsville, Maryland 20705
4the failure rate of electromigration affecting a DRAM groupwould be K EM ,DRAM EM , where K EM ,DRAM is a constantused when considering any degradation mechanisms. Theprediction process is demonstrated in Figure 2.defining the weight percentage that DRAM has from thenormalized electromigration failure rate. The overall DRAMfailure rate per functional group, 1DRAM , is: 1DRAM K EM ,DRAM EM K HCI ,DRAM HCI(2) K NBTI ,DRAM NBTI KTDDB,DRAM TDDBWhereK EM , DRAM is a constant defined by the weightpercentage that DRAM has from Electromigration,normalized failure rate of Electromigration, EMis theK HCI , DRAM is aconstant defined by the weight percentage that DRAM hasfrom HCI, HCI is the normalized failure rate of HCI,K NBTI , DRAM is a constant defined by the weight percentagethat DRAM has from NBTI,rate of NBTI, NBTIis the normalized failureKTDDB,DRAM is a constant defined by the weightpercentage that DRAM has from TDDB and TDDB is thenormalized failure rate of TDDB. Considering the probabilityof a specific functional group operating during the time whenfailure occurs is a modification to Equation (1): F PF 1F PF Ki ,F i where F(3)Figure 2. The simulation tool process methodology. The simulated IC istreated as a system having several functional groups affected by differentfailure mechanisms. The differences in the two approaches, ITB and DTB,would take place in the "Analysis of Functional Groups" process block.is the failure rate of a functional group as theV. FIELD DATAcontributor to the potential failure of the device under analysisandPF is the probability that that functional group wasaccessed at the time of failure (its degraded operation at anypoint in time would cause immediate failure of the device).This probability factor is either known by the circuit designer,extracted from the DTB SPICE analysis, or are general rulesof how the functional group under analysis operates; i.e.random read-write in memory. The total failure rate of a T ,A. Data SourceAn extensive field study was conducted in order todemonstrate the accuracy of the simulation tool and verify itsprediction capabilities. Reliability predictions were performedbased on field failures of DRAMs, microcontrollers andmicroprocessors, as shown in Table 1.Vendor Part NumberPartDescriptionVendorTech. NodeMT16LSDF3264HG256MB DRAMMicron150 nmM470L6524DU0512MB DRAMSamsung100 nmHYMD512M646BF81GB DRAMHynix110 e90 nmN F is the total number of each function group, N is the totalnumber of all types of function groups and AF is the ratio ofRH80536GC0332MSL7ENPentiumProcessorIntel90 nmthe number of units of the nth functional group type to the totalnumber of functional groups that exist in the component underanalysis. Equations (1)-(4) explain how the multiplemechanism theory is used in the simulation tool. They can beTable 1. The ICs used for the field study. Different types of ICs and the widenode range exemplify the simulation tool flexibility.component,can be defined as being equal to thesummation of the total number of each functional groupmultiplied by the failure rate of each functional group type. T N F F N N F N F N AF Fwhere T(4)is the failure rate of the component under analysis,dfrsolutions.com (301) 474-0607 9000 Virginia Manor Road, Suite 290, Beltsville, Maryland 20705
514400,00010300,00086200,0004100,0002B. Field FR Calculation IllustrationThe microcontroller is used hereafter to illustrate theprocess for acquiring environmental information anddetermining its failure rate based on field data. A similarprocess was performed for the other four ICs.A total of 96 microcontrollers were replaced during acumulative total of 595,412 working months. Figure 3 showsthe failed ICs an
FaRBS (Failure-Rate-Based SPICE [spacecraft, planet, instrument, C-matrix, events]) and MaCRO (Maryland Circuit Reliability-Oriented). FaRBS is a reliability prediction process that uses accelerated test data and PoF based die-level failure mechanism models to calculate the failure rate of integrated circuit components.
Test-Retest Reliability Alternate Form Reliability Criterion-Referenced Reliability Inter-rater reliability 4. Reliability of Composite Scores Reliability of Sum of Scores Reliability of Difference Scores Reliability
Reliability prediction approach depends upon the product development stages and its related reliability metric [4]. Reliability prediction methods address application of mathematical models and component data for the purpose of estimating the field reliability of a system before failure data are available for the system.
Reliability Infrastructure: Supply Chain Mgmt. and Assessment Design for reliability: Virtual Qualification Software Design Tools Test & Qualification for reliability: Accelerated Stress Tests Quality Assurance System level Reliability Forecasting: FMEA/FMECA Reliability aggregation Manufacturing for reliability: Process design Process variability
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Series Circuit A series circuit is a closed circuit in which the current follows one path, as opposed to a parallel circuit where the circuit is divided into two or more paths. In a series circuit, the current through each load is the same and the total voltage across the circuit is the sum of the voltages across each load. NOTE: TinkerCAD has an Autosave system.
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generic performance capability. The comparative analysis imparts the proposed prediction model results improved GHI prediction than the existing models. The proposed model has enriched GHI prediction with better generalization. Keywords: Ensemble, Improved backpropagation neural network, Global horizontal irradiance, and prediction.
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