Synthesis Options - Computer Action Team

Synthesis OptionsFPGA and ASIC TechnologyComparison - 1 2009 Xilinx, Inc. All Rights Reserved

WelcomeIf you are new to FPGA design, thismodule will help you synthesizeyour design properlyThese synthesis techniques promotefast and efficient FPGA designdevelopmentTips for all major FPGA synthesistools are included in this module

After completing thismodule, you will able to:Identify synthesis tool options thatcan be used to increaseperformance and/or reduce yourdesign sizeDescribe an approach to using yoursynthesis tool to obtain higherperformance

Timing ClosureFPGA and ASIC TechnologyComparison - 4 20092007 Xilinx, Inc. All Rights Reserved

Breakthrough PerformanceThree steps to achieve breakthrough performance1. Utilize embedded (dedicated) resources Performance by constructionDSP slice, block RAM, ISERDES, OSERDES, EMAC, andMGT2. Write code for performance Use synchronous design methodologyEnsure the code is written optimally for critical pathsPipeline3. Drive your synthesis and Place & Route tools Try different synthesis optimization techniquesAdd critical timing constraints in synthesisPreserve hierarchyApply full and correct constraintsUse High effortFPGA and ASIC TechnologyComparison - 5 20092007 Xilinx, Inc. All Rights ReservedVirtex -6 FPGAPerformance Meter

Use Dedicated HardwareDedicated hardware block timing iscorrect by constructionNot dependent on programmable routingOffers as much as 3x the performance ofsoft implementationsExamplesXtremeDSP SolutionSliceFIFO at 600 MHzDSP slices at 600 MHzBlock RAM at 600 MHzBlock RAM/FIFOFPGA and ASIC TechnologyComparison - 6 20092007 Xilinx, Inc. All Rights Reserved

Simple Coding TechniquesUse pipeline stages—more bandwidthUse synchronous reset—better system controlUse Finite State Machine (FSM) optimizationsUse inferable resourcesMultiplexerShift Register LUT (SRL)Block RAM, LUT RAMCascade DSPThink about the levels of logic required for the logic you are buildingBe aware of the circuit structures being inferredPay attention to the expected combinatorial complexitySee the Synthesis and Simulation Design Guide:Help Software Manuals Synthesis and Simulation DesigFPGA and ASIC TechnologyComparison - 7 20092007 Xilinx, Inc. All Rights Reserved

Synthesis OptionsThere are many synthesis options that can help you obtainyour performance and area objectivesTiming-driven synthesisFSM extractionRetimingRegister duplicationHierarchy managementResource sharingPhysical optimizationNote that these options are included with Synplify, Precision,and XST synthesis toolsThe notes include instructions for each toolFPGA and ASIC TechnologyComparison - 8 20092007 Xilinx, Inc. All Rights Reserved

Synthesis GuidelinesUse timing constraints to drive the optimization of your designDefine accurate individual clock constraintsCreate clock constraints in the appropriate style Specify related clocks using related constraintsSpecify unrelated clocks using independent constraints– Use different clock groups in SynplicityBased on your performance objectives, the tools will try severalalgorithms to attempt to meet performance while keeping theamount of resources in mindPerformance objectives are provided to the synthesis tool viatiming constraintsDo not over-constrain your design This will disable your synthesis tool from helping youFPGA and ASIC TechnologyComparison - 9 20092007 Xilinx, Inc. All Rights Reserved

Timing ConstraintsApply proper timing constraints to the synthesis tool, but do notpass them to the implementation toolsSynthesis constraints will also be passed (by default) on to the Xilinximplementation tools via a Netlist Constraints File (NCF) when usingSynplify This should be turned offSynthesis constraints can be passed (not by default) on to the Xilinximplementation tools via the Xilinx NGC file when using XSTSynplifySpecify constraints in the SDC file or use the SCOPE GUIXSTSpecify constraints in the XCF file See the Synthesis Constraints section of Chapter 3 in the Constraints Guide– Software Manuals: Help Software Manuals Constraints GuideFPGA and ASIC TechnologyComparison - 10 20092007 Xilinx, Inc. All Rights Reserved

Timing Constraint ExampleUse constraintsSynplify stops optimizing when theconstraints are metOver-constraining clocks can yieldpoorer resultsOver-constraining means specifyinga constraint that is tighter than whatyour system needs(*) Synplicity’s dataUsing the global frequency field can deteriorate resultsFPGA and ASIC TechnologyComparison - 11 20092007 Xilinx, Inc. All Rights Reserved

Impact of Synthesis ConstraintsNon-timing-constrained designs can be optimized for arearather than performanceLUTLUTLUT LUT LUTLUTLUTLUT LUTLUTLUTNon-Timing DrivenTotal LUTs: 5Clock Freq: 423.7 MHzFPGA and ASIC TechnologyComparison - 12Timing Driven(Bigger but Faster!!!)Total LUTs: 6Clock Freq: 591.7 MHz ( 40%) 20092007 Xilinx, Inc. All Rights Reserved

Place & Route GuidelinesTiming constraintsUsing the correct PlaceIt is essential to use accurate& Route options canconstraints for the implementation have a dramatic impacttoolson design performanceImplementation tool optionsThe implementation tools have manyoptions that can affect designperformanceArea ConstraintsEspecially with the use of the PlanAhead toolFPGA and ASIC TechnologyComparison - 13 20092007 Xilinx, Inc. All Rights Reserved

Impact of Constraints in ToolsPerformanceExample Reed-Solomon design2.11.61.01.4No constraints;No constraints Constraints inStandard effortin synthesis; synthesisPlace & Route and Place &with High effort Route (Highand constraint effort)FPGA and ASIC TechnologyComparison - 14 20092007 Xilinx, Inc. All Rights ReservedConstraints insynthesis and Place& Route; retimingin synthesis;High effort in PAR

FSM ExtractionFinite State Machine (FSM) extraction optimizes your statemachine byre-encoding and optimizing your design based on the numberof states and inputsBy default, the tools will use FSM extractionCan be enabled or disabled globally, or using attributes in yourHDL codeSafe state machinesBy default, the synthesis tools will remove all decoding for illegalstates (when FSM extraction is enabled) Even if you include VHDL “when others” or Verilog “default” casesMust be turned ON to use “safe” FSM implementation See Notes for more informationFPGA and ASIC TechnologyComparison - 15 20092007 Xilinx, Inc. All Rights Reserved

RetimingRetiming: The synthesis tool automatically tries to moveregister stages to balance combinatorial delay on each side ofthe registersBefore RetimingDQDQDQAfter RetimingDQFPGA and ASIC TechnologyComparison - 16D 20092007 Xilinx, Inc. All Rights ReservedQDQ

Register DuplicationRegister duplication is used to reduce fanout on registers (toimprove delays)Registered output signals that are used internallyXilinx recommends manual register duplicationNot all high fanout nets will give you a timing problemMost synthesis vendors create signals signal name rep0, rep1,etc. Implementation tools pack logic with related names into the same slice,which can prohibit a register from being moved closer to its destinationWhen manually duplicating registers, do not use a number at the end Example: signal name 0dup, signal name 1dupUse synthesis options to prevent duplicate registers from being remergedFPGA and ASIC TechnologyComparison - 17 20092007 Xilinx, Inc. All Rights Reserved

Hierarchy ManagementThe basic settings areFlatten the design: Allows total combinatorial optimization across allboundaries (XST default)Maintain hierarchy: Preserves hierarchy without allowing optimizationof combinatorial logic across boundaries (Xilinx recommended)If you have followed the synchronous design guidelines, use thesetting-maintain hierarchyIf you have not followed the synchronous design guidelines, usethe setting-flatten the designYour synthesis tool may have additional settingsRefer to your synthesis documentation for details on these settingsFPGA and ASIC TechnologyComparison - 18 20092007 Xilinx, Inc. All Rights Reserved

Hierarchy Preservation BenefitsEasily locate problems in the code based on the hierarchicalinstance names contained within static timing analysis reportsEnables floorplanning and incremental design flowThe primary advantage of flattening is to optimizecombinatorial logic across hierarchical boundariesIf the outputs of leaf-level blocks are registered, there is generallyno need to flatten However, preserving hierarchy can limit register retiming (balancing)and register duplicationFPGA and ASIC TechnologyComparison - 19 20092007 Xilinx, Inc. All Rights Reserved

Resource SharingResource sharing allows arithmetic operator resources to beshared with other functionsBy default, this property is set to True with XSTIf your design has a significant amount of math functions, itcan decrease the size of your designResource sharing is the opposite of logic replicationThis option can increase the net delays for those nets whosefanout increasesFPGA and ASIC TechnologyComparison - 20 20092007 Xilinx, Inc. All Rights Reserved

Schematic ViewersAllows you to view synthesis results graphicallyCheck the number of logic levels between flip-flopsLocate net and instance names quicklyView the design as generic RTL or technology-specificcomponentsWorks best when hierarchy has been preserved duringsynthesisFPGA and ASIC TechnologyComparison - 21 20092007 Xilinx, Inc. All Rights Reserved

Cross-ProbingFrom the Timing Analyzer, click a reported worst-case pathand that path will be highlighted in the synthesis schematicviewerCross-probe to the code Review the code to determine whether or not it can be rewritten toimprove performanceApply timing constraints in your synthesis tool to optimize this pathbetterYou may need to set some environment variables for this to work For more information, see Application Note XAPP406: Cross-Probing toSynplify and ExemplarFPGA and ASIC TechnologyComparison - 22 20092007 Xilinx, Inc. All Rights Reserved

Physical OptimizationSynopsys Synplify Premier or Mentor Precision Physicalsoftware (add-on tools)Based on the critical paths in the design, the tools will attemptto optimize and physically locate the associated logic closelytogether to minimize the routing delaysEssentially, this is a way to provide critical path information tothe synthesis tool so that it can attempt to optimize thosepaths furtherFPGA and ASIC TechnologyComparison - 23 20092007 Xilinx, Inc. All Rights Reserved

SummaryYour HDL coding style can affect synthesis resultsInfer resources whenever possibleMost resources are inferable, either directly or with anattribute and the appropriate coding styleIf you cannot infer the resource you need, instantiate thenecessary component with the aid of the Core GeneratorTake advantage of the synthesis options provided to help youmeet your timing objectivesUse synchronous design techniques and timing-drivensynthesis to achieve higher performanceFPGA and ASIC TechnologyComparison - 24 20092007 Xilinx, Inc. All Rights Reserved

Where Can I Learn More?Software ManualsStart Xilinx ISE Design Suite 12.1 ISE Design Tools Documentation Software ManualsThis includes the Synthesis & Simulation Design Guide This guide has example inferences of many architectural resourcesXST User Guide HDL language constructs, coding recommendations, and synthesis optionsConstraints Guide All Synthesis and Implementation constraintsXilinx Trainingwww.xilinx.com/training Xilinx tools and architecture coursesHardware description language coursesBasic HDL Coding Techniques, Spartan-6 and Virtex-6 Coding Techniques andother Free training videos!FPGA and ASIC TechnologyComparison - 25 20092007 Xilinx, Inc. All Rights Reserved