STM32L15xxD, STM32L15xxC And STM32L15xxC-A Ultra-low-power .
STM32L15xxD/C/C-AErrata sheetSTM32L15xxD, STM32L15xxC and STM32L15xxC-Aultra-low-power device limitationsSilicon identificationThis errata sheet applies to revisions A, Z, Y and X of the STMicroelectronicsSTM32L15xxD, STM32L15xxC and STM32L15xxC-A ultra-low-power products. This familyfeatures an ARM 32-bit Cortex -M3 core, for which an errata notice is also available (seeSection 1 for details). A full list of root part numbers is shown in Table 1.The products can be identified (see Table 2) by: The revision code marked below the sales type on the device package The last three digits of the internal sales type printed on the box labelTable 1. Device summaryReferencePart M32L151QDH6STM32L151QCH6STM32L151RCT6A, STM32L151RCY6, STM32L151RCY6DTRSTM32L151RDT6, 6STM32L152ZDT6:Table 2. Device identification(1)Sales typeSTM32L15xxD, STM32L15xQC, STM32L15xZC,STM32L15xRC-A(3), STM32L15xVC-A(3)Revision code(2)marked on device“A”, “Z”, “Y” or “X”1. The REV ID bits in the DBGMCU IDCODE register show the revision code of the device (see theSTM32L151xx, STM32L152xx and STM32L162xx advanced ARM -based 32-bit MCUs reference manual(RM0038) for details on how to find the revision code).2. Refer to the device datasheets for details on how to identify the revision code on the different packages.3. The silicon limitation for STM32L15xRC/VC products without 'A' letter as the last character of the salestypes are described in STM32L15xxC errata sheet.November 2016DocID025862 Rev 41/33www.st.com1
ContentsSTM32L15xxD/C/C-AContents1ARM 32-bit Cortex -M3 limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.121.1.1Cortex -M3 LDRD with base in list may result in incorrect base registerwhen interrupted or faulted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.1.2Cortex -M3 event register is not set by interrupts and debug . . . . . . . . . 71.1.3Cortex -M3 interrupted loads to the stack-pointer can cause erroneousbehavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71.1.4SVC and BusFault/MemManage may occur out of order . . . . . . . . . . . . 8STM32L15xxD/C/C-A silicon limitations . . . . . . . . . . . . . . . . . . . . . . . . . 92.12.22.32/33Cortex -M3 limitation description for the STM32L1xxxxultra-low-power devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6System limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.1.1AOP RANGE bit is mapped on register COMP CSR(28) instead ofregister AOP CSR(28) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.1.2Missing analog switch on PC10 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . 122.1.3PG0 to PG15 and PF0 to PF5 port sink current when VIN VDD . . . . . . 122.1.4If debugger is connected in JTAG mode and JNTRST (PB4) pinconfiguration is changed, the connection is lost . . . . . . . . . . . . . . . . . . 122.1.5Read protection: a mass erase occurs if the RDP register is written withlevel 0 when level 0 is already set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.1.6In Stop mode, RAMs are not in power down if DMA is enabled . . . . . . 132.1.7Invalid read from data EEPROM after write in program Flash . . . . . . . . 142.1.8Debugging Stop mode with WFE entry . . . . . . . . . . . . . . . . . . . . . . . . . 142.1.9Boot from bank2 limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.1.10Pull-up on PB7 when configured in analog mode . . . . . . . . . . . . . . . . . 152.1.11Range 1 of dynamic voltage scaling has a lower limit of 2.0 V . . . . . . . 152.1.12Wakeup sequence from Standby mode when using more than onewakeup source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162.1.13Flash memory wakeup issue when waking up from Stop or Sleepwith Flash memory in power-down mode . . . . . . . . . . . . . . . . . . . . . . . 162.1.14Unexpected system reset when waking up from Stop mode withregulator in low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17LCD peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172.2.1High drive resistive network total value too low . . . . . . . . . . . . . . . . . . . 172.2.2Injection from LCD SEG2, LCD SEG5, LCD SEG21 pins . . . . . . . . . 17IWDG peripheral limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18DocID025862 Rev 4
STM32L15xxD/C/C-A2.3.12.42.52.62.7ContentsRVU and PVU flags are not reset in Stop mode . . . . . . . . . . . . . . . . . . 18I2C peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182.4.1SMBus standard not fully supported . . . . . . . . . . . . . . . . . . . . . . . . . . . 182.4.2Wrong behavior of I2C peripheral in Master mode aftermisplaced STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182.4.3Violation of I2C “setup time for repeated START condition” parameter . 192.4.4In I2C slave “NOSTRETCH” mode, underrun errors may not be detectedand may generate bus errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192.4.510-bit Master mode: new transfer cannot be launched if firstpart of the address has not been acknowledged by the slave . . . . . . . . 20SPI/I2S peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212.5.1In I2S slave mode, WS level must to be set by the external masterwhen enabling the I2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212.5.2Wrong CRC calculation when the polynomial is even . . . . . . . . . . . . . . 212.5.3BSY bit may stay high at the end of a data transfer in Slave mode . . . . 222.5.4Wrong CRC transmitted in Master mode with delayed SCK feedback . 232.5.5SPI CRC may be corrupted when a peripheral connected to the sameDMA channel of the SPI finishes its DMA transaction . . . . . . . . . . . . . . 232.5.6Corrupted last bit of data and/or CRC, received in Master mode withdelayed SCK feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24USART peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252.6.1Idle frame is not detected if receiver clock speed is deviated . . . . . . . . 252.6.2In full duplex mode, the Parity Error (PE) flag can be cleared bywriting the data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252.6.3Parity Error (PE) flag is not set when receiving in Mute modeusing address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252.6.4Break frame is transmitted regardless of nCTS input line status . . . . . . 252.6.5nRTS signal abnormally driven low after a protocol violation . . . . . . . . 262.6.6Start bit detected too soon when sampling for NACK signalfrom the smartcard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262.6.7Break request can prevent the Transmission Complete flag (TC) frombeing set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272.6.8Guard time is not respected when data are sent on TXE events . . . . . . 272.6.9nRTS is active while RE or UE 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27SDIO peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282.7.1SDIO hardware flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282.7.2Wrong CCRCFAIL status after a response without CRC . . . . . . . . . . . . 282.7.3No underrun detected and wrong data transmission . . . . . . . . . . . . . . . 282.7.4CE-ATA multiple write command and card busy signal management . . 29DocID025862 Rev 43/334
ContentsSTM32L15xxD/C/C-A2.82.9FSMC peripheral limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292.8.1FSMC NOR Flash/PSRAM controller asynchronous access onbank2.4 when bank1 is in synchronous mode (CBURSTRW bit is set) 292.8.2FSMC synchronous mode and disabled NWAIT signal . . . . . . . . . . . . . 302.8.3Dummy read cycles inserted when reading synchronous memories . . . 30DAC peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302.9.12.10RCC peripheral limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312.10.12.1134/33Spurious activation of DAC output buffer (PA4 and PA5) . . . . . . . . . . . 30Delay after an RCC peripheral clock enabling . . . . . . . . . . . . . . . . . . . . 31RTC limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312.11.1Spurious tamper detection when disabling the tamper channel . . . . . . . 312.11.2RTC calendar registers are not locked properly . . . . . . . . . . . . . . . . . . 31Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32DocID025862 Rev 4
STM32L15xxD/C/C-AList of tablesList of tablesTable 1.Table 2.Table 3.Table 4.Table 5.Table 6.Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Device identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Cortex -M3 core limitations and impact on microcontroller behavior . . . . . . . . . . . . . . . . . . 6Summary of silicon limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Maximum allowable APB frequency at 30 pF load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32DocID025862 Rev 45/335
ARM 32-bit Cortex -M3 limitations1STM32L15xxD/C/C-AARM 32-bit Cortex -M3 limitationsAn ARM errata notice of the STM32L1xxxx core is available searching for “Cortex -M3errata at the following web address: www.arm.com.All the described limitations are minor and relate to revision r2p0-00rel0 of the Cortex -M3core. Table 3 summarizes these limitations and their implications on the behavior of theSTM32L1xxxx ultra-low-power devices.Table 3. Cortex -M3 core limitations and impact on microcontroller behavior1.1ARMsummary of errataImpact onSTM32L1xxxx ultralow-power devicesARMIDARMcategory602117Cat 2LDRD with base in list may result in incorrect baseregister when interrupted or faultedMinor563915Cat 2Event register is not set by interrupts and debugMinor752419Cat 2Interrupted loads to SP can cause erroneous behaviorMinor740455Cat 2SVC and BusFault/MemManage may occur out of orderMinorCortex -M3 limitation description for the STM32L1xxxxultra-low-power devicesOnly the limitations described below have an impact, even though minor, on theimplementation of STM32L1xxxx ultra-low-power devices.All other limitations described in the ARM errata notice (and summarized in Table 3 above)have no impact and are not related to the implementation of the STM32L1xxxx ultra-lowpower devices (Cortex-M3 r2p0-00rel0).1.1.1Cortex -M3 LDRD with base in list may result in incorrect base registerwhen interrupted or faultedDescriptionThe Cortex -M3 Core has a limitation when executing an LDRD instruction from thesystem-bus area, with the base register in a list of the form LDRD Ra, Rb, [Ra, #imm]. Theexecution may not complete after loading the first destination register due to an interruptbefore the second loading completes or due to the second loading getting a bus fault.Workaround6/331.This limitation does not impact the STM32L1xxxx code execution when executing fromthe embedded Flash memory, which is the standard use of the microcontroller.2.Use the latest compiler releases. As of today, the compilers no longer generate thisparticular sequence. Moreover, a scanning tool is provided to detect this sequence onprevious releases (refer to your preferred compiler provider).DocID025862 Rev 4
ARM 32-bit Cortex -M3 limitationsSTM32L15xxD/C/C-A1.1.2Cortex -M3 event register is not set by interrupts and debugDescriptionWhen interrupts related to a wake from event (WFE) occur before the WFE is executed, theevent register used for WFE wakeup events is not set and the event is missed. Therefore,when the WFE is executed, the core does not wake up from a WFE if no other event orinterrupt occurs.Workaround1.For the following interrupt sources:–All external interrupts/events lines (EXTI)–PVD output on EXTI line 16 (if VREFINT is enabled only)–RTC alarm on EXTI line 17–USB wakeup on EXTI line 18–RTC tamper and timestamp on EXTI line 19–RTC wakeup on EXTI line 20–Comparator 1 wake-up on EXTI line 21 (if VREFINT is enabled only)–Comparator 2 wake-up on EXTI line 22 (if VREFINT is enabled only)–Channel acquisition on EXTI line 23Use STM32L1xxxx external events instead of interrupts to wake up the core from aWFE by configuring an external or internal EXTI line in event mode.2.1.1.3For all other interrupt sources, a timer must be programmed to provide a timeout eventand wake-up the core if the event is likely to arrive before the WFE instruction isexecuted.Cortex -M3 interrupted loads to the stack-pointer can cause erroneousbehaviorDescriptionIf an interrupt occurs during the data-phase of a single word load to the stack-pointer(SP/R13), an erroneous behavior can occur. In all cases, returning from the interrupt willresult in the load instruction being executed in an additional time. For all instructionsperforming an update to the base register, the base register will be erroneously updated oneach execution, resulting in the stack-pointer being loaded from an incorrect memorylocation.The instructions affected by this limitation are the following: LDR SP, [Rn],#imm LDR SP, [Rn,#imm]! LDR SP, [Rn,#imm] LDR SP, [Rn] LDR SP, [Rn,Rm]WorkaroundAs of today, no compiler generates these particular instructions. This limitation can onlyoccur with hand-written assembly code.DocID025862 Rev 47/3332
ARM 32-bit Cortex -M3 limitationsSTM32L15xxD/C/C-ABoth issues can be solved by replacing the direct load to the stack pointer by anintermediate load to a general-purpose register followed by a move to the stack pointer.Example:Replace LDR SP, [R0] byLDR R2,[R0]MOV SP,R21.1.4SVC and BusFault/MemManage may occur out of orderDescriptionIf an SVC exception is generated by executing the SVC instruction while the followinginstruction fetch is faulted, then the MemManage or BusFault handler may be entered eventhough the faulted instruction which followed the SVC should not have been executed.WorkaroundA workaround is only required if the SVC handler will not return to the return address thathas been stacked for the SVC exception and the instruction access after the SVC will fault.If this is the case then padding can be inserted between the SVC and the faulting area ofcode, for example, by inserting NOP instructions.8/33DocID025862 Rev 4
STM32L15xxD/C/C-A2STM32L15xxD/C/C-A silicon limitationsSTM32L15xxD/C/C-A silicon limitationsTable 4 summarizes the fix status for products listed in Table 2: Device identification.The legend for Table 4 is as follows:A workaround available,N no workaround available,P partial workaround available,‘-’ and grayed fixed.Table 4. Summary of silicon limitationsLinks to silicon limitationsSection 2.1:SystemlimitationsRev ARev ZRev YRev XSection 2.1.1: AOP RANGE bit is mapped on registerCOMP CSR(28) instead of register AOP CSR(28)A---Section 2.1.2: Missing analog switch on PC10 GPIONNNNSection 2.1.3: PG0 to PG15 and PF0 to PF5 port sinkcurrent when VIN VDDA---Section 2.1.4: If debugger is connected in JTAG mode andJNTRST (PB4) pin configuration is changed, theconnection is lostAAAASection 2.1.5: Read protection: a mass erase occurs if theRDP register is written with level 0 when level 0 is alreadysetAAAASection 2.1.6: In Stop mode, RAMs are not in power downif DMA is enabledA---Section 2.1.7: Invalid read from data EEPROM after writein program FlashA---Section 2.1.8: Debugging Stop mode with WFE entryAAAASection 2.1.9: Boot from bank2 limitationAA--Section 2.1.10: Pull-up on PB7 when configured in analogmodeAAAASection 2.1.11: Range 1 of dynamic voltage scaling has alower limit of 2.0 VAANNSection 2.1.12: Wakeup sequence from Standby modewhen using more than one wakeup sourceAAAASection 2.1.13: Flash memory wakeup issue when wakingup from Stop or Sleep with Flash memory in power-downmodeAAA-Section 2.1.14: Unexpected system reset when waking upfrom Stop mode with regulator in low-power modeAAA-N---AAAASection 2.2.1: High drive resistive network total value tooSection 2.2:lowLCD peripheralSection 2.2.2: Injection from LCD SEG2, LCD SEG5,limitationsLCD SEG21 pinsDocID025862 Rev 49/3332
STM32L15xxD/C/C-A silicon limitationsSTM32L15xxD/C/C-ATable 4. Summary of silicon limitations (continued)Links to silicon limitationsSection 2.3:IWDGperipherallimitationRev ARev ZRev YRev XSection 2.3.1: RVU and PVU flags are not reset in StopmodeAAAASection 2.4.1: SMBus standard not fully supportedAAAASection 2.4.2: Wrong behavior of I2C peripheral in Mastermode after misplaced STOPAAAAAAAAAAAASection 2.4.5: 10-bit Master mode: new transfer cannot belaunched if first part of the address has not beenacknowledged by the slaveAAAASection 2.5.1: In I2S slave mode, WS level must to be setby the external master when enabling the I2SAAAASection 2.5.2: Wrong CRC calculation when the polynomialis evenAAAASection 2.5.3: BSY bit may stay high at the end of a datatransfer in Slave modeAAAASection 2.5.4: Wrong CRC transmitted in Master modewith delayed SCK feedbackAAAASection 2.5.5: SPI CRC may be corrupted when aperipheral connected to the same DMA channel of the SPIfinishes its DMA transactionNNNNSection 2.5.6: Corrupted last bit of data and/or CRC,received in Master mode with delayed SCK feedbackAAAASection 2.4.3: Violation of I2C “setup time for repeatedSection 2.4: I2CSTART condition” parameterperipherallimitationsSection 2.4.4: In I2C slave “NOSTRETCH” mode, underrunerrors may not be detected and may generate bus errorsSection 2.5:SPI/I2Speripherallimitations10/33DocID025862 Rev 4
STM32L15xxD/C/C-ASTM32L15xxD/C/C-A silicon limitationsTable 4. Summary of silicon limitations (continued)Links to silicon limitationsRev ARev ZRev YRev XSection 2.6.1: Idle frame is not detected if receiver clockspeed is deviatedNNNNSection 2.6.2: In full duplex mode, the Parity Error (PE) flagcan be cleared by writing the data registerAAAASection 2.6.3: Parity Error (PE) flag is not set whenreceiving in Mute mode using address mark detectionNNNNSection 2.6.4: Break frame is transmitted regardless ofnCTS input line statusNNNNSection 2.6.5: nRTS signal abnormally driven low after aprotocol violationAAAASection 2.6.6: Start bit detected too soon when samplingfor NACK signal from the smartcardNNNNSection 2.6.7: Break request can prevent the TransmissionComplete flag (TC) from being setAAAASection 2.6.8: Guard time is not respected when data aresent on TXE eventsAAAASection 2.6.9: nRTS is active while RE or UE 0AAAASection 2.7.1: SDIO hardware flow controlAAAAAAAAAAAASection 2.7.4: CE-ATA multiple write command and cardbusy signal managementAAAASection 2.8.1: FSMC NOR Flash/PSRAM controllerasynchronous access on bank2.4 when bank1 is insynchronous mode (CBURSTRW bit is set)AAAASection 2.8.2: FSMC synchronous mode
Table 3 summarizes these limitations and their implications on the behavior of the STM32L1xxxx ultra-low-power devices. Table 3. Cortex 1.1 Cortex -M3 limitation description for the STM32L1xxxx ultra-low-power devices Only the limitations described below have an impact, even though minor, on the implementation of STM32L1xxxx ultra-low-power .
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