2-BIT COMPARATOR WITH 8-TRANSISTOR 1-BIT FULL

International Journal of Applied Engineering Research ISSN 0973-4562 Volume 12, Number 1 (2017) Research India Publications. http://www.ripublication.com2-BIT COMPARATOR WITH 8-TRANSISTOR1-BIT FULL ADDER WITH CAPACITORC.CHANDAN KUMAR M.Tech-VLSI,B.GOWTHAMI Assistant ProfessorDepartment of ECE,Department of ECE,Sree vidyanikethan Engineering collegeSree vidyanikethan Engineering collegeA.Rangampet, Tirupati, IndiaA.Rangampet, Tirupati, omAbstract — In modern technology comparator is mostwidely used circuit to convert the analog to digitalsignals and to compare a digital signal with exity is high as per existed system and also thedelay produced by the existed comparator producessame delay in the final response. So we present a new 2Bit comparator system in which 1-Bit full adder and 1Transistor AND gate are present. The 1-Bit full adder isconstructed using 8-Transistor with capacitor todecrease the delay, power dissipation, no of transistor's,circuit complexity and average power consumption.Keywords— comparator ,no of transistor count,1-bit fullFig.1 Block Diagram of Digital Comparatoradder.For example, If we need to add and subtract binaryI. INTRODUCTIONnumbers comparison should be done among theDigital comparators are nothing but binarynumbers and to determine whether the value ofcomparators or logical comparators. By usinginput A is ' ',' ' or ' ' to the value at input B etc.combinational circuit we can test and obtain ' ',' 'Several logic gates are used to construct digitaland ' ' values in digital form. Applications ofcomparator on the basis of Boolean Algebra. Digitalcomparator are CPU and MCUS as CMOS 4063 andComparator's are classified into 2-types.4585 and the TTL 7485 and 74682'89.A simple basic EQUALITY COMPARATOR: As the namecomparatorcircuitisanXORgate.Digitalequality indicates comparator produces outputcomparators as shown in Fig.1 are most widely used.high when both the inputs are equal. MAGNITUDE COMPARATOR: The magnitudecomparator contains three output terminals, onefor A B, A B and other for A B.734

International Journal of Applied Engineering Research ISSN 0973-4562 Volume 12, Number 1 (2017) Research India Publications. http://www.ripublication.coma) EQUALITY COMPARATORThe magnitude comparator circuit containsIn this circuit we use four XNOR gatesan equality comparator which provides output Aconnected to a single AND gate and the inputs ofequal to B when both the inputs are equal. When theXNOR gates are A(A0.A3) and B(B0.B3) as showninput-A is greater than input-B gate 1 is activated andin Fig.2 .An XNOR gate produces output logic-'1'provides output. similarly input-A is less than input-when both the inputs are same.B gate 3 is activated and provides output.APPLICATIONS OF COMPARATORS These are the devices used in computers andmicroprocessors for address decoding circuitry. These are used in control applications such astemperature, position and so on and they arealso used to drive the actuators. Process controllers Servo-motor controlII. EXISTING DESIGNFig.2 Four Bit Equality ComparatorExisting design consist ofSimilarly all the four XNOR gates area)Single transistor AND gate using MOSFETconnected to an AND gate in which if any one of theb) 3-Transistor XOR gateXNOR gate is logic-'0'.Then output of AND gate isc)forced to logic-'0'.d) Full adder design using 2-XOR and 1-MUXb) MAGNITUDE COMPARATORe)2-Transistor MUX design1-bit full adderMagnitude comparator is constructed usingI.8 Transistors Full Adder2-and gates 2-inverters and an XNOR gate as shownII.9 Transistors Full Adderin Fig.3. And the circuit provides 3-outputs.i.A B (A greater than B).ii.A B (A equal to B).iii.A B (A less than B).III.a)8-T 1-bit Full Adder with CapacitorSINGLE TRANSISTOR AND GATE USINGMOSFETThe following and gate is constructed usingMOSFET as shown in Fig.4 in which input A isgiven at Vdd and input B is connected to gateterminal. When input A ( Vdd ) is zero then theoutput is forced to zero. When input A is '1'case1:Input B is '0' then output is '0'.When gate terminal is supplied with '0V' theMOSFET enters in to cut-off region and then outputis '0'.case 2:input B is '1' then output is '1'.Fig.3 One Bit Magnitude Comparator735

International Journal of Applied Engineering Research ISSN 0973-4562 Volume 12, Number 1 (2017) Research India Publications. http://www.ripublication.comwhen gate terminal is supplied with '1V' theMOSFET exceeds the threshold voltage and entersinto saturation in which the device is operated forlinear application so output is '1'.Fig.5 XOR Gate Using 3 TransistorTable1. 3T-XOR Gate Truth TableFig.4 AND Gate Implementation Using SingleMOSFETb) 3-TRANSISTOR XOR GATE3-transistor XOR gate as shown in Fig.5using in this 8T full adder circuit. This a combinationof CMOS inverter & one pass transistor. By usingc)this full adder circuit we can minimize the delay of2-Transistor MUX designcircuit & power dissipation .The XOR [14] gate isLet us see 2 input lines having signals as Xconstructed using a CMOS inverter and a passand Y for selecting one of the 2 inputs signals .Wetransistor when input B '1' the output of XOR gate isrequire addresses which can be a one bit word andinversion to input A. Another condition when B '0'the address line are designated as C.Table 2. Truth Table for 2 1 MultiplexerCMOS inverter output goes to high. The passtransistor is turned ON, output is same as the input A.Which works as XOR gate, when A logic-1 andB logic-0. Both the transistor PMOS-2 & NMOStrying to switched ON because of the W/L ratioPMOS-2 threshold voltage is minimum comparativeNMOS that the reason PMOS-2 is conducted first &This truth table can be expressed by thethe output is same as the A input.following Boolean expression.Output C' X C YMultiplexer circuit also works as select lineC. When C '0' the PMOS transistor is activated and itproduces X input at output terminal. When C '1'NMOS transistor is activated and it produces Y input736

International Journal of Applied Engineering Research ISSN 0973-4562 Volume 12, Number 1 (2017) Research India Publications. http://www.ripublication.comat output terminal. NMOS W/L ratio is 1/1 andadder [17] which is constructed using 8 transistors [8]PMOS W/L ratio 2/1. MUX output is satisfied fullas shown in Fig.8.adder carry output. 2 1 Multiplexer shown in Fig.6.When cin is low problem of threshold lossoccurs at second XOR gate as NOMS (NM1) turnsON. So that current is shorted to ground and due tothis attenuation takes place at output. When the firstXOR gate becomes high the NMOS transistor (NM 2)turns ON and due tothreshold loss [9] completeoutput cannot be obtained.For example when we take input "011" theFig.6 2 1 Multiplexerfirst XOR gate become ON. So that NMOS transistord) Full adder design using 2-XOR and 1-MUXNM2 gets activated and due to this complete outputThe full adder [12] as shown in Fig.7 iswill not be produced as we discussed in earlierconstructed using 2-XOR gates and 1-MUX. Thesection.output of first XOR gate becomes the selection linesfor MUX and A and Cin are given as inputs forsecond XOR gate and the output sum is producedbased on the selection line given by MUX.Fig.7 Full Adder Using 2-XOR and 1-MUXFig.8 Schematic of 8T 1-Bit full adderI. 8 Transistors Full AdderII. 9 Transistors Full AdderThe combination of first 3 transistorsA problem of threshold loss [4] asbecomes an XOR gate[7,8] and the combination ofmentioned earlier in case of 8T adder has beensecond 3 transistors becomes an another XOR gateeliminated by the approach as proposed in [5]. Fig. 9which is driven by previous XOR gate output. Nowrepresents the circuit of adder using 9 transistors. Anthe output of second XOR gate is connected to a 2-additional N-channel metal-oxide semiconductortransistor combinational circuit which forms a(NMOS) transistor (NM1) has been added in the 8Tmultiplexer. The dimensions of the transistors[6] design to achieve full swing at the output. WithPM0,PM1 are constructed to W/L ratio equal to 2u:1uthe input combinations of ABC (i.e. Input Vector) and PM2,PM4 W/L 5u:1u and NM0,NM1,NM2,PM3“000”, “010” and “110”,two transistors turn onW/L 1u:1u. The whole circuit works as a1-Bit fullsimultaneously in 8T based full adder. Thus, a737

International Journal of Applied Engineering Research ISSN 0973-4562 Volume 12, Number 1 (2017) Research India Publications. http://www.ripublication.comcombined parallel resistance effect reduces the outputvoltage as discussed earlier. With the insertion of anadditional transistor (NM1 in Fig.9), this problem hasbeen removed. Now for these input combinations, itgives a complete 1 at the first stage of XOR gate,giving a complete 0 for carry input c IN 0. Thus, theproblem for full swing at the output gets eliminated.Fig.10 8-Transistor with Capacitor 1-Bit FullAdderOUTPUT WAVEFORM :Fig.9 Schematic of 9T 1-Bit full adderIn 9-Transistor 1-Bit full adder similarly as8-Transistor when we take input "011" the first XORgate become ON. So that NMOS transistor NM3 getsactivated and due to this complete output will not beproduced as we discussed in earlier section.III. 8T 1-Bit Full Adder with CapacitorFig.11 Input and output waveforms of 8-TThe 1-Bit full adder [1,2] constructed using9-Transistor[3,5,9] in which the NMOS (NM1) is1-bit Full Adder with Capacitorreplaced by a capacitor in the order of few pf value inIII. PROPOSED DESIGNa)order to produce full output swing and to reduce the2-BITW/L 2u:1u,PM1,PM3W/L 5u:1u,NM0,NM1,NM2,PM4ratiosratiosFULLIn digital systems Comparator is basic andusing 8T 1-bit full adder with capacitor are PM0,PM2areUSINGADDERS:fabrication process. The dimensions of onent.Thearebetween the pair of input signals is done and output isproduced according to the requirement.W/L 1u:1u as shown in Fig.10.738comparison

International Journal of Applied Engineering Research ISSN 0973-4562 Volume 12, Number 1 (2017) Research India Publications. http://www.ripublication.comCALCULATIONS:Boolean equationsderived from k-map by usingtruth tableA B A1B1' A0B0'A1'B1' A0B0'A1B1 A1B1' [A1'B1' A1B1]A0B0' A1B1' X1A0B0'.Assume A1'B1' A1B1 X1A B A1'A0'B1'B0' A1'A0B1'B0 A1A0'B10' A-1A0B1B0 [A1'B1' A1B1] [A0'B0' A0B0]Fig.12 2-Bit Comparator X1X0.The comparison between 2-Bits A0,A1 and. Assume X0 A0'B0' A0B0B0,B1 is done by using 2-Bit Magnitude ComparatorA B[11]. The comparison of A0,A1 with B0,B1 binary A1'B1 A0'B0A1'B1' A0'B0A1B1 A1'B1 A0'B0[A1'B1' A1B1]bit's. To produce the output binary bit's as A B,A B A1'B1 A0'B0X1and A B. The truth table combination is shown inTable-1.b) COMPARISONS AND CALCULATIONS:COMPARISONS:Table 3. Truth Table of 2-Bit ComparatorFig.13 Schematic for 2-bit comparator by using8T with capacitor 1-bit full adder739