CMOS COMPARATOR 1. Comparator Design Specifications
CMOS COMPARATOR1. Comparator Design SpecificationsVoVOH(Vin - Vin-)VOL(a)VOHVIL(Vin - Vin-)VIHVOL(b)VOSVOHVIL(Vin - Vin-)VIHVOL(c)Figure 1. Comparator Transfer Characteristics.A comparator is a circuit that has binary output. Ideally its output shown in Figure 1(a) is definedas follows:1
VOH if Vin Vin - 0VO VOL if Vin Vin - 0This is not realizable because its gain is infinity. Figure 1(b) shows a realizable first order transfercharacteristic of a comparator. Its output is defined as follows:if (Vin - Vin - ) VIH VOH VO A V (Vin - Vin - ) if VIL (Vin - Vin - ) VIH Vif (Vin - Vin - ) VIL OLAnother nonideal characteristic of practical comparator is the present of input offset. That is the output doesnot change until the input difference reached the input offset Vos. Figure 1(c) shows this transfercharacteristic. Its output is defined as follows:if (Vin - Vin - ) VIH VOH VO A V (Vin - Vin - ) - A V VOS if VIL (Vin - Vin - ) VIH Vif (Vin - Vin - ) VIL OLThe input offset can be minimized or ignored by proper layout.If the input step is sufficiently small the output should not slew and the transient response will be alinear response. The settling time is the time needed for the output to reach a final value within apredetermined tolerance, when excited by a small signal. Small-signal settling time is determined by thegain bandwidth product of the amplifier, this will be shown in the opamp circuit section later. If the inputstep magnitude is sufficiently large, the comparator will slew by virtue of not having enough current tocharge or discharge the compensating and/or load capacitances. The slew rate is determined from the slopeof the output waveform during the rise or fall of the output. Slew rate is limited by the currentsourcing/sinking capability in charging the output capacitor.Settling time is important in analog signal processing. It is necessary to wait until the amplifier hassettled to within a few tenths of a percent of its final value in order to avoid errors in the accuracy ofprocessing analog signals. A longer settling time implies that the rate of processing analog signals must bereduced.In the following design, a 10mV signal must be resolved using the comparator in Figure 2 and 3.The power supply rails are VDD 5V and VSS -5V. That is, the output will swing by 10V ( from –5V to5V) when the input signal swing by 10mV( from –5mV to 5mV). The comparator gain must be at least10,000 ( 10V/10mV). The following specifications will be used in designing the comparator in Pwell andNwell processes.VDD 5V, VSS -5V, AV 10000 , -3 CMR 3, -4.5 Vo 4.5, SR 10V/us.2. Designing the Comparator with NMOS Input Drivers2
VDD(3)M3w 7.2ul 6.6uM4w 7.2ul 6.6u(5)ID3M1w 5.4ul 6.6uVG1 (1)ID4ID1I(6) OID2VSSM6w 59.4ul 6.6uVSSM2w 5.4ul 6.6uVG2(2)(8)Rb175K(7) VCVGS1VGS2(9)ISS 5uA M7w 22.2ul 6.6uCL2pFM5w 5.4ul 6.6uM8w 22.2ul 6.6u(4) VSSFigure 2. The CMOS Comparator Implementation with NMOS input drivers.Figure 2 shows the comparator schematic diagram implemented with NMOS input drivers.1.Determine the current drive requirement of M7 to satisfy the SR specification, if C L 2pF dV I D7 C L C L (SR) (2E - 12)(10E6) 20uA dt 2.Determine the size of M6 and M7 to satisfy the output-voltage swing requirement.VDS7(SAT) VO(min) - VSS 4.5 ( 5) 0.5 VGS7 VN0 VVDS7(SAT) ( W/L) 7 2I DS7β7 2I DS7K N ( W/L) 72I DS72(20E - 6) 42K N (VDS7(SAT) )(40E - 6)(0.5) 2Similarly,3Vo-
VSD6(SAT) VDD - VO(max) 5 (4.5) 0.5( W/L) 6 3.2I SD62(20E - 6) 10.6662K P (VSD6(SAT) )(15E - 6)(0.5) 2Calculate the gain of the second stage. g m6A V2 g ds6 g ds74.2K P I SD6 ( W/L) 62(15E - 6)(20E - 6)(10.666) 100I SD6 (λ P λ N )(20E - 6)(0.02 0.02) Calculate the gain of the first stage to satisfy the overall gain.A V A V1 A V2 10000A V1 10000 / A V2 1005.Determine the first stage biasing current using the minimum allowable size of (W/L) 1, and minimumoutput offset.(a) Consider M4 and M6.Using the minimum size for M4, determine the current ISD4 that mirror with M6. That is,I SD4 ( W/L) 41I SD6 (20uA) 1.875uA( W/L) 610.666(b) Consider M5 and M7.Using the minimum size for M5, determine the current IDS5 that mirror with M7. That is,I DS5 ( W/L) 51I DS7 (20uA) 5uA( W/L) 74I SD4 I DS5 /2 2.5uA I SD3I DS2 I DS1 I DS5 /2 2.5uA(c) Select the larger of the two ISD4 and adjust the size of M4(W/L) 4 I SD42 .5 E - 6(10.666) 1.333( W/L) 6 20E - 6I SD64
6.Determine the size of M1 to satisfy the gain requirement.A V1 g m1 g ds2 g ds4( W/L)1 2K N I DS1 ( W/L)1I DS1 (λ N λ P )[A V1 I DS1 (λ N λ P )]2 [(100)(2.5E - 6)(0.02 0.02)]2 0.52K N I DS12(40E - 6)(2.5E - 6)Let (W/L)1 be the minimum size of 1. Then re-calculate the gain of the first stage.A V1 g m1 g ds2 g ds42K N I DS1 ( W/L)1I DS1 (λ N λ P ) 2(40E - 6)(2.5E - 6)(1) 141.42(2.5E - 6)(0.02 0.02)A V A V1 A V2 (141.42)(100) 141427.The minimum size of M5 ( 1) in step 5(b) can be adjusted to satisfy the negative input CMR of –3V.VG1(min) VSS VDS5(SAT) 2I DS1 VT1K N ( W/L)1VDS5(SAT) VG1(min) VSS 2I DS1 VT1K N ( W/L)1 -3 - (-5) VDS5(SAT) ( W/L) 5 2(2.5E - 6) 1 0.65(40E - 6)(1)2I DS5K N ( W/L) 52I DS52(5E - 6) 0.592K N (VDS5(SAT) )(40E - 6)(0.65) 2Select the larger of the two, (W/L)5 1. No adjustment needed, since this is the value used earlier in thecalculation.8.The minimum size of M3( 1) in step 5(a) can be adjusted to meet the positive input CMR of 3V.VG1(max) VDD (W/L) 3 2I SD3- VT3 VT1K P ( W/L) 3K P (VDD2I SD32(2.5E - 6)1 2212- VG1(max) - VT3 VT1 )(15E - 6)(5 - 3- -1 1)5
Select the larger of the two, (W/L)3 1. No further adjustment needed.9.Determine the size of M8 to provide as the main current mirror for the comparator.For VDS5 0.5V and VDS7 0.5V, this voltage corresponds to the value of VG8 -3.5V or VGS8 1.5V. LetISD8 20uA.(W/L)8 2I DS82(20E - 6) 42K N (VGS8 - VTN )(40E - 6)(1.5 - 1) 2The external resistor Rb connected between VG8 and ground must be chosen to provide the required currentfor M8 of 20uA.Rb 0 VG8 0 ( 3.5) 175KI DS820E - 610. Select the width of each Finding the W, L to the nearest multiple of λ 65.6*Adjusted to satisfy the balance condition to minimize the input offset voltage, Vos:( W/L) 6( W/L) 7 2(W/L) 4(W/L) 559.422.2 27.25.48.25 8.226
3. Designing the Comparator with PMOS Input Drivers(3) VDDM8w 60ul 6.6u(9)M5w 30ul 6.6uM7w 60ul 6.6u(7)Rb 175kV(1)VG1VSD5VSD1VGD1M1w 15ul 6.6uV (2)M2w 15ul 6.6u(8)(6)CL2pF(5)M3w 5.4ul-6.6u Vo-M4w 5.4ul-6.6uVGS3M6w 21.6ul 6.6u(4) VSSFigure 3. CMOS Comparator Implementation with PMOS input drivers.Figure 3 shows the comparator schematic diagram implemented with PMOS input dricers.1.Determine the current drive requirement of M7 to satisfy the SR specification, if C L 2pF dV I D7 C L C L (SR) (2E - 12)(10E6) 20uA dt 2.Determine the size of M6 and M7 to satisfy the output-voltage swing requirement.VSD7(SAT) VDD - VO(max) 5 4.5 0.5VSD7(SAT) ( W/L) 7 2I SD7β7 2I SD7K P ( W/L) 72I DS72(20E - 6) 10.6662K P (VDS7(SAT) )(15E - 6)(0.5) 2Similarly,7
VDS6(SAT) VO(min) VSS 4.5 ( 5) 0.5( W/L) 6 3.2I DS62(20E - 6) 42K N (VDS6(SAT) )(40E - 6)(0.5) 2Calculate the gain of the second stage. g m6A V2 g ds6 g ds74.2K N I DS6 ( W/L) 62(40E - 6)(20E - 6)(4) 100I DS6 (λ N λ P )(20E - 6)(0.02 0.02) Calculate the gain of the first stage to satisfy the overall gain.A V A V1 A V2 10000A V1 10000 / A V2 1005.Determine the first stage biasing current using the minimum allowable size of 1, and minimum outputoffset.(a) Consider M4 and M6.Using the minimum size for M4, determine the current ISD4 that mirror with M6. That is,I DS4 ( W/L) 41I DS6 (20uA) 5uA( W/L) 64I SD5 2I DS4 2(5uA) 10uA(b) Consider M5 and M7.Using the minimum size for M5, determine the current IDS5 that mirror with M7. That is,I SD5 ( W/L) 51(20uA) 1.875uAI SD7 10.666( W/L) 7I DS4 I SD5 /2 1.875 / 2 0.937uA I DS3I SD2 I SD1 I SD5 /2 1.875/2 0.937uA(c) Select the larger of the two ISD4 and adjust the size of M4 if necessary.The larger ISD4 5uA from 5(a). No adjustment needed, since this is the value use in calculation.6.Determine the size of M1 to satisfy the gain requirement.8
A V1 g m1 g ds2 g ds42K P I SD1 ( W/L)1I SD1 (λ N λ P )[A V1 I SD1 (λ N λ P )]2 [(100)(5E - 6)(0.02 0.02)]2( W/L)1 2.6662K P I SD12(15E - 6)(5E - 6)7.The minimum size of M5 ( 1) in step 5(b) can be adjusted to satisfy the positive input CMR of 3V.VG1(max) VDD - VSD5(SAT) - VSG1VG1(max) VDD VSD5(SAT) 2I SD1 VT1 K P ( W/L)1VSD5(SAT) VDD - VG1(max) 2I SD1 VT1 K P ( W/L)1 5-3VSD5(SAT) ( W/L) 5 2(5E - 6) 1 0.5(15E - 6)(2.666)2I SD5K P ( W/L) 52I SD52(10E - 6) 5.3332K P (VDS5(SAT) )(15E - 6)(0.5) 2Select the larger of the two, (W/L)5 5.333 and adjust the size of M7 for proper mirroring with M5.(W/L) 7 8.I720( W/L) 5 (5.333) 10.666I510The minimum size of M3 or M4( 1) in step 5(a) can be adjusted to meet the negative input CMR of 3V.VG1(min) VSS (W/L) 3 2I DS3 VT3 VT1 K N ( W/L) 3K P (VG1(min)2I DS32(5E - 6)1 2216- VSS - VT3 VT1 )(40E - 6)[-3 - (-5) - 1 1 ]Select the larger of the two, (W/L)3 1. No further adjustment needed.9
9.Determine the size of M8 to provide as the main current mirror for the comparator.For VSD5 0.5V and VSD7 0.5V, this voltage corresponds to the value of VG8 3.5V or VSG8 1.5V. LetISD8 20uA.(W/L)8 2I SD82(20E - 6) 10.6662K P (VSG8 - VTP )(15E - 6)(5 - 3.5 - 1) 2The external resistor Rb connected between VG8 and ground must be chosen to provide the required currentfor M8 of 20uA.Rb VG8 0 3.5 0 175KI DS820E - 610. Select the width of each 6606.65.6Finding the W, L to the nearest multiple of λ ed to satisfy the balance condition to minimize the input offset voltage, Vos:( W/L) 7( W/L) 6 2(W/L) 5(W/L) 4WW6 2 7W5W421.660 25.4304 410
4. Comparator Simulation4.1. CMOS Comparator Implementation with NMOS Input DriversThe PSpice netlist is given below:* Filename "diffcmp.cir"* MOS Diff Amp with NMOS Input Drivers and Current Mirror Load* Input SignalsVIN 2 0 DC 0VVOS 1 0 DC 0V* Power SuppliesVDD 3 0 DC 5VOLTVSS 4 0 DC -5VOLT* Netlist for CMOS COMPARATOR in PwellM1 5 1 7 4NMOS1 W 5.4UL 6.6UM2 6 2 7 4NMOS1 W 5.4UL 6.6UM3 5 5 3 3PMOS1 W 7.2UL 6.6UM4 6 5 3 3PMOS1 W 7.2UL 6.6UM5 7 9 4 4NMOS1 W 5.4UL 6.6UM6 8 6 3 3PMOS1 W 59.4U L 6.6UM7 8 9 4 4NMOS1 W 22.2U L 6.6UM8 9 9 4 4NMOS1 W 22.2U L 6.6U* External ComponentsCL 8 02pFRB 9 0175K* SPICE Parameters.MODEL NMOS1 NMOS VTO 1 KP 40U GAMMA 1.0 LAMBDA 0.02 PHI 0.6 TOX 0.05U LD 0.5U CJ 5E-4 CJSW 10E-10 U0 550 MJ 0.5 MJSW 0.5 CGSO 0.4E-9 CGDO 0.4E-9.MODEL PMOS1 PMOS VTO -1 KP 15U GAMMA 0.6 LAMBDA 0.02 PHI 0.6 TOX 0.05U LD 0.5U CJ 5E-4 CJSW 10E-10 U0 200 MJ 0.5 MJSW 0.5 CGSO 0.4E-9 CGDO 0.4E-9* Analysis.DC VIN -1mv 1mV 1uV.TF V(8) VIN.PROBE.END11
To eliminate the input offset voltage, the negative of Vos is applied at the negative input of the comparator.That is, the PSpice entry for VOS is modified as follow:VOS 1 0 DC 39.825uv****SMALL-SIGNAL CHARACTERISTICSV(8)/VIN 1.728E 0412
INPUT RESISTANCE AT VIN 1.000E 20OUTPUT RESISTANCE AT V(8) 1.269E 064.1.2Comparator Transient Response Slew Rate Measurement* Filename "diffcmp1.cir"* MOS Diff Amp with NMOS Input and Current Mirror Load* Input SignalVIN 2 0 PWL(0,-5V 10us,-5V 10.01us,5V 30us, 5V 30.01us,-5V 1s, -5V)VOS 1 0 DC -88.501uV*Power SuppliesVDD 3 0 DC 5VOLTVSS 4 0 DC -5VOLT* Netlist for Slew Rate Measurement* Netlist for CMOS COMPARATOR in PwellM1 5 1 7 4NMOS1 W 5.4UL 6.6UM2 6 2 7 4NMOS1 W 5.4UL 6.6UM3 5 5 3 3PMOS1 W 7.2UL 6.6UM4 6 5 3 3PMOS1 W 7.2UL 6.6UM5 7 9 4 4NMOS1 W 5.4UL 6.6UM6 8 6 3 3PMOS1 W 59.4U L 6.6UM7 8 9 4 4NMOS1 W 22.2U L 6.6UM8 9 9 4 4NMOS1 W 22.2U L 6.6U* External ComponentsCL 8 02pFRB 90175K* SPICE Parameters.MODEL NMOS1 NMOS VTO 1 KP 40U GAMMA 1.0 LAMBDA 0.02 PHI 0.6 TOX 0.05U LD 0.5U CJ 5E-4 CJSW 10E-10 U0 550 MJ 0.5 MJSW 0.5 CGSO 0.4E-9 CGDO 0.4E-9.MODEL PMOS1 PMOS VTO -1 KP 15U GAMMA 0.6 LAMBDA 0.02 PHI 0.6 TOX 0.05U LD 0.5U CJ 5E-4 CJSW 10E-10 U0 200 MJ 0.5 MJSW 0.5 CGSO 0.4E-9 CGDO 0.4E-9*Analysis.TRAN .1ns 40us.PROBE.END13
4.1.3Comparator Transient Response Settling Time Measurement* Filename "diffcmp2.cir"* MOS Diff Amp with NMOS Input and Current Mirror Load* Input SignalVIN 2 0 PWL(0,-5mV 10us,-5mV 10.01us,5mV 30us, 5mV 30.01us,-5mV 1s, 5mV)VOS 1 0 DC 0V*Power SuppliesVDD 3 0 DC 5VOLTVSS 4 0 DC -5VOLT* Netlist for CMOS COMPARATOR in PwellM1 5 1 7 4NMOS1 W 5.4UL 6.6UM2 6 2 7 4NMOS1 W 5.4UL 6.6UM3 5 5 3 3PMOS1 W 7.2UL 6.6UM4 6 5 3 3PMOS1 W 7.2UL 6.6UM5 7 9 4 4NMOS1 W 5.4UL 6.6UM6 8 6 3 3PMOS1 W 59.4U L 6.6UM7 8 9 4 4NMOS1 W 22.2U L 6.6UM8 9 9 4 4NMOS1 W 22.2U L 6.6U* External ComponentsCL 8 02pFRB 90175K* SPICE Parameters.MODEL NMOS1 NMOS VTO 1 KP 40U GAMMA 1.0 LAMBDA 0.02 PHI 0.6 TOX 0.05U LD 0.5U CJ 5E-4 CJSW 10E-10 U0 550 MJ 0.5 MJSW 0.5 CGSO 0.4E-9 CGDO 0.4E-9.MODEL PMOS1 PMOS VTO -1 KP 15U14
GAMMA 0.6 LAMBDA 0.02 PHI 0.6 TOX 0.05U LD 0.5U CJ 5E-4 CJSW 10E-10 U0 200 MJ 0.5 MJSW 0.5 CGSO 0.4E-9 CGDO 0.4E-9*Analysis.TRAN .1ns 40us.PROBE.ENDUpper output voltage for 5% settling time, 0.95(Vo(max)) 0.95(4.85) 4.6Lower output voltage for 5% settling time, 0.95(Vo(min)) 0.95(-5) 4.754.1.4 Comparator Open-loop Transfer Function* Filename "diffcmp4.cir"* MOS Diff Amp with NMOS Input and Current Mirror Load* Input SignalVIN 2 0 AC 1V*Power SuppliesVDD 3 0 DC 5VOLTVSS 4 0 DC -5VOLT* Netlist for CMOS COMPARATOR in PwellM1 5 0 7 7NMOS1 W 5.4UL 6.6UM2 6 2 7 7NMOS1 W 5.4UL 6.6UM3 5 5 3 3PMOS1 W 7.2UL 6.6UM4 6 5 3 3PMOS1 W 7.2UL 6.6UM5 7 9 4 4NMOS1 W 5.4UL 6.6UM6 8 6 3 3PMOS1 W 59.4U L 6.6UM7 8 9 4 4NMOS1 W 22.2U L 6.6U15
M899 4 4NMOS1W 22.2UL 6.6U* External ComponentsCL 8 02pFRB 9 0175K* SPICE Parameters.MODEL NMOS1 NMOS VTO 1 KP 40U GAMMA 1.0 LAMBDA 0.02 PHI 0.6 TOX 0.05U LD 0.5U CJ 5E-4 CJSW 10E-10 U0 550 MJ 0.5 MJSW 0.5 CGSO 0.4E-9 CGDO 0.4E-9.MODEL PMOS1 PMOS VTO -1 KP 15U GAMMA 0.6 LAMBDA 0.02 PHI 0.6 TOX 0.05U LD 0.5U CJ 5E-4 CJSW 10E-10 U0 200 MJ 0.5 MJSW 0.5 CGSO 0.4E-9 CGDO 0.4E-9*Analysis.AC DEC 10 0.1HZ 100MegHZ.PROBE.END4.2. CMOS Comparator Implementation with PMOS Input Drivers* Filename "diffcmpp.cir"* CMOS Comparator with PMOS Input Drivers* Input SignalsVIN 2 0 DC 0VVOS 1 0 DC 0V* Power SuppliesVDD 3 0 DC 5VOLTVSS 4 0 DC -5VOLT* Netlist for CMOS Comparator in NwellM1 5 1 7 7PMOS1 W 15UL 6.6U16
S1NMOS1PMOS1NMOS1PMOS1PMOS1W 15UW 5.4UW 5.4UW 30UW 21.6UW 60UW 60UL 6.6UL 6.6UL 6.6UL 6.6UL 6.6UL 6.6UL 6.6U* External ComponentsCL 8 02pFRB 9 0175K* SPICE Parameters.MODEL NMOS1 NMOS VTO 1 KP 40U GAMMA 1.0 LAMBDA 0.02 PHI 0.6 TOX 0.05U LD 0.5U CJ 5E-4 CJSW 10E-10 U0 550 MJ 0.5 MJSW 0.5 CGSO 0.4E-9 CGDO 0.4E-9.MODEL PMOS1 PMOS VTO -1 KP 15U GAMMA 0.6 LAMBDA 0.02 PHI 0.6 TOX 0.05U LD 0.5U CJ 5E-4 CJSW 10E-10 U0 200 MJ 0.5 MJSW 0.5 CGSO 0.4E-9 CGDO 0.4E-9* Analysis.DC VIN -1mv 1mV 1uV.TF V(8) VIN.PROBE.ENDTo eliminate the input offset voltage the negative of Vos is applied V- input.VOS1 0 DC –88.501uV17
****SMALL-SIGNAL CHARACTERISTICSV(8)/VIN 1.196E 04INPUT RESISTANCE AT VIN 1.000E 20OUTPUT RESISTANCE AT V(8) 1.284E 064.2.1 Comparator Transient Response for Slew Rate Measuremnt* Filename "diffcmpp1.cir"* MOS Diff Amp with PMOS Input and Current Mirror Load* Input SignalVIN 2 0 PWL(0,-5V 10us,-5V 10.01us,5V 30us, 5V 30.01us,-5V 1s, -5V)VOS 1 0 DC 0V*Power SuppliesVDD 3 0 DC 5VOLTVSS 4 0 DC -5VOLT* Netlist for CMOS Comparator in NwellM1 5 1 7 7PMOS1 W 15UL 6.6UM2 6 2 7 7PMOS1 W 15UL 6.6UM3 5 5 4 4NMOS1 W 5.4UL 6.6UM4 6 5 4 4NMOS1 W 5.4UL 6.6UM5 7 9 3 3PMOS1 W 30UL 6.6UM6 8 6 4 4NMOS1 W 21.6U L 6.6UM7 8 9 3 3PMOS1 W 60UL 6.6UM8 9 9 3 3PMOS1 W 60UL 6.6U* External ComponentsCL 8 02pFRB 9 0175K18
* SPICE Parameters.MODEL NMOS1 NMOS VTO 1 KP 40U GAMMA 1.0 LAMBDA 0.02 PHI 0.6 TOX 0.05U LD 0.5U CJ 5E-4 CJSW 10E-10 U0 550 MJ 0.5 MJSW 0.5 CGSO 0.4E-9 CGDO 0.4E-9.MODEL PMOS1 PMOS VTO -1 KP 15U GAMMA 0.6 LAMBDA 0.02 PHI 0.6 TOX 0.05U LD 0.5U CJ 5E-4 CJSW 10E-10 U0 200 MJ 0.5 MJSW 0.5 CGSO 0.4E-9 CGDO 0.4E-9*Analysis.TRAN .1ns 40us.PROBE.END4.2.2 Comparator Transient Response for Settling Time Measurement* Filename "diffcmpp2.cir"* MOS Diff Amp with PMOS Input and Current Mirror Load* Input SignalVIN 2 0 PWL(0,-5mV 10us,-5mV 10.01us,5mV 30us, 5mV 30.01us,-5mV 1s, 5mV)VOS 1 0 DC 0V*Power SuppliesVDD 3 0 DC 5VOLTVSS 4 0 DC -5VOLT* Netlist for Slew Rate Measurement* Netlist for CMOS Comparator in NwellM1 5 1 7 7PMOS1 W 15UL 6.6UM2 6 2 7 7PMOS1 W 15UL 6.6UM3 5 5 4 4NMOS1 W 5.4UL 6.6UM4 6 5 4 4NMOS1 W 5.4UL 6.6UM5 7 9 3 3PMOS1 W 30UL 6.6UM6 8 6 4 4NMOS1 W 21.6U L 6.6U19
M7M8899 3 39 3 3PMOS1PMOS1W 60UW 60UL 6.6UL 6.6U* External ComponentsCL 8 02pFRB 9 0175K* SPICE Parameters.MODEL NMOS1 NMOS VTO 1 KP 40U GAMMA 1.0 LAMBDA 0.02 PHI 0.6 TOX 0.05U LD 0.5U CJ 5E-4 CJSW 10E-10 U0 550 MJ 0.5 MJSW 0.5 CGSO 0.4E-9 CGDO 0.4E-9.MODEL PMOS1 PMOS VTO -1 KP 15U GAMMA 0.6 LAMBDA 0.02 PHI 0.6 TOX 0.05U LD 0.5U CJ 5E-4 CJSW 10E-10 U0 200 MJ 0.5 MJSW 0.5 CGSO 0.4E-9 CGDO 0.4E-9*Analysis.TRAN .1ns 40us.PROBE.END4.2.3 Comparator Open-loop Transfer Function* Filename "diffcmpp3.cir"* CMOS Comparator with PMOS Input Drivers* Input SignalsVIN 2 0 AC 1VVOS 1 0 DC -88.501uV* Power Supplies20
VDD 3 0 DC 5VOLTVSS 4 0 DC -5VOLT* Netlist for CMOS Comparator in NwellM1 5 1 7 7PMOS1 W 15UL 6.6UM2 6 2 7 7PMOS1 W 15UL 6.6UM3 5 5 4 4NMOS1 W 5.4UL 6.6UM4 6 5 4 4NMOS1 W 5.4UL 6.6UM5 7 9 3 3PMOS1 W 30UL 6.6UM6 8 6 4 4NMOS1 W 21.6U L 6.6UM7 8 9 3 3PMOS1 W 60UL 6.6UM8 9 9 3 3PMOS1 W 60UL 6.6U* External ComponentsCL 8 02pFRB 9 0175K* SPICE Parameters.MODEL NMOS1 NMOS VTO 1 KP 40U GAMMA 1.0 LAMBDA 0.02 PHI 0.6 TOX 0.05U LD 0.5U CJ 5E-4 CJSW 10E-10 U0 550 MJ 0.5 MJSW 0.5 CGSO 0.4E-9 CGDO 0.4E-9.MODEL PMOS1 PMOS VTO -1 KP 15U GAMMA 0.6 LAMBDA 0.02 PHI 0.6 TOX 0.05U LD 0.5U CJ 5E-4 CJSW 10E-10 U0 200 MJ 0.5 MJSW 0.5 CGSO 0.4E-9 CGDO 0.4E-9* Analysis.AC DEC 10 0.1HZ 100MegHZ.PROBE.END4.2.4 Comparator Adjusted for 0-5V Operation21
* Filename "diffcp5.cir"* CMOS Comparator with PMOS Input Drivers* Input SignalsVIN 2 0 DC 0VVOS 1 0 DC 2.5V* Power SuppliesVDD 3 0 DC 5VOLTVSS 4 0 DC 0VOLT* Netlist for CMOS Comparator in NwellM1 5 1 7 7PMOS1 W 15UL 6.6UM2 6 2 7 7PMOS1 W 15UL 6.6UM3 5 5 4 4NMOS1 W 5.4UL 6.6UM4 6 5 4 4NMOS1 W 5.4UL 6.6UM5 7 9 3 3PMOS1 W 30UL 6.6UM6 8 6 4 4NMOS1 W 21.6U L 6.6UM7 8 9 3 3PMOS1 W 60UL 6.6UM8 9 9 3 3PMOS1 W 60UL 6.6U* External ComponentsCL 8 02pFRB 9 0175K* SPICE Parameters.MODEL NMOS1 NMOS VTO 1 KP 40U GAMMA 1.0 LAMBDA 0.02 PHI 0.6 TOX 0.05U LD 0.5U CJ 5E-4 CJSW 10E-10 U0 550 MJ 0.5 MJSW 0.5 CGSO 0.4E-9 CGDO 0.4E-9.MODEL PMOS1 PMOS VTO -1 KP 15U GAMMA 0.6 LAMBDA 0.02 PHI 0.6 TOX 0.05U LD 0.5U CJ 5E-4 CJSW 10E-10 U0 200 MJ 0.5 MJSW 0.5 CGSO 0.4E-9 CGDO 0.4E-9* Analysis.DC VIN 2.49V 2.51V 1uV.PROBE.END22
4.2.5 Comparator Transient Response for 0-5V Operation* Filename "diffcp5t.cir"* MOS Diff Amp with PMOS Input and Current Mirror Load* Input SignalVIN 2 0 PWL(0,2.495V 10us,2.495V 10.01us,2.505V 30us, 2.505V30.01us,2.495V 1s, 2.495V)VOS 1 0 DC 2.5V*Power SuppliesVDD 3 0 DC 5VOLTVSS 4 0 DC 0VOLT* Netlist for CMOS Comparator in NwellM1 5 1 7 7PMOS1 W 15UL 6.6UM2 6 2 7 7PMOS1 W 15UL 6.6UM3 5 5 4 4NMOS1 W 5.4UL 6.6UM4 6 5 4 4NMOS1 W 5.4UL 6.6UM5 7 9 3 3PMOS1 W 30UL 6.6UM6 8 6 4 4NMOS1 W 21.6U L 6.6UM7 8 9 3 3PMOS1 W 60UL 6.6UM8 9 9 3 3PMOS1 W 60UL 6.6U* External ComponentsCL 8 02pFRB 9 0175K* SPICE Parameters.MODEL NMOS1 NMOS VTO 1 KP 40U GAMMA 1.0 LAMBDA 0.02 PHI 0.6 TOX 0.05U LD 0.5U CJ 5E-4 CJSW 10E-10 U0 550 MJ 0.5 MJSW 0.5 CGSO 0.4E-9 CGDO 0.4E-9.MODEL PMOS1 PMOS VTO -1 KP 15U GAMMA 0.6 LAMBDA 0.02 PHI 0.6 TOX 0.05U LD 0.5U CJ 5E-4 CJSW 10E-10 U0 200 MJ 0.5 MJSW 0.5 CGSO 0.4E-9 CGDO 0.4E-9*Analysis23
.TRAN .1ns 40us.PROBE.END24
CMOS COMPARATOR 1. Comparator Design Specifications Vo (Vin - Vin-) VOH VOL (Vin - Vin-) VOH VOL VIL VIH (Vin - Vin-) VOH VOL VIL VIH VOS (b) (c) (a) Figure 1. Comparator Transfer Characteristics. A comparator is a circuit that has binary output. Ideally
1.2.1 A high-speed CMOS comparator with 8-bit resolution A high-speed CMOS comparator is shown in figure 1.2. The comparator consists of three blocks, an input stage, a flip-flop and SR latch. The architecture uses two non-overlapping clocks ( 1and 2). The circuit operates in two m
V VV. Comparator. X o K Lower-gain Amplifier-Based Comparator. V DD V B1 M 1 M 2 V B2 M 3 M 4 V IN V IN M 9 C L C L V OUT V OUT Amplifier-Based Comparator with Regenerative Feedback. Amplifier-Based Comparator with Regenerative Feedback. At the start of the comparison process, an amplifier-based comparator behaves as a linear amplifier.
CMOS Digital Circuits Types of Digital Circuits Combinational . – Parallel Series – Series Parallel. 15 CMOS Logic NAND. 16 CMOS Logic NOR. 17 CMOS logic gates (a.k.a. Static CMOS) . nMOS and pMOS are not ideal switches – pMOS passes strong 1 , but degraded (weak) 0
8. n-CH Pass Transistors vs. CMOS X-Gates 9. n-CH Pass Transistors vs. CMOS X-Gates 10. Full Swing n-CH X-Gate Logic 11. Leakage Currents 12. Static CMOS Digital Latches 13. Static CMOS Digital Latches 14. Static CMOS Digital Latches 15. Static CMOS Digital Latches . Joseph A. Elias, PhD 2
SOI CMOS technology has been used to integrate analog circuits. In this section, SOI CMOS op amp is discussed. Then, the performance comparison of op amps using bulk and SOI CMOS technologies is presented. 3.1 Analysis on SOI CMOS Op amp Figure 5 shows an SOI CMOS single stage op amp with a symmetrical topology. This circuit has a good .
CMOS Setup Procedure for Dispense System CPU Board PN 2025-0121 CMOS Setup Procedure Use this procedure to set computer CMOS parameters for dispense system CPU board (PN 2025-0121) with CPU, memory, and fan. 1. Activate BIOS/CMOS Setup Utility (pg 1) 2. Preset CPU board (pg 2) 3. Computer CMOS Parameters (pg 2) 4. Save Changes (pg 5) Revision .
Circuits-A CMOS VLSI Design Slide 2 Outline: Circuits Lecture A – Physics 101 – Semiconductors for Dummies – CMOS Transistors for logic designers Lecture B – NMOS Logic – CMOS Inverter and NAND Gate Operation – CMOS Gate Design – Adders – Multipliers Lecture C – P
This manual is the basic textbook for anyone writing an ASTM standard. A study of Parts A, B, C, or E will show the proper form for the principal types of standards including a detailed explanation of how to write each section, from the title to the appendixes. Within Parts A, B, C, and E, the first section lists the preferred sequence of headings and indicates whether these sections are .
