Power MOSFET Avalanche Design Guidelines
VISHAY SILICONIXwww.vishay.comPower MOSFETsApplication Note AN-1005Power MOSFET Avalanche Design GuidelinesTABLE OF CONTENTSPageTable of Figures. 2Introduction . 3Overview. 3Avalanche Mode Defined . 3Avalanche Occurrences in Industry Applications. 3Flyback Converter Example. 3Avalanche Failure Mode. 4Power MOSFET Device Physics. 4Rugged MOSFETs. 5Avalanche Testing Details . 7Single Pulse Unclamped Inductive Switching . 7Decoupled VDD Voltage Source. 7Avalanche Rating . 8EAS Thermal Limit Approach . 8Single Pulse Example . 8Repetitive Pulse. 10Buyer Beware. 12The purpose of this note is to better understand and utilize power MOSFETs, it is important to explore the theory behindavalanche breakdown and to understand the design and rating of rugged MOSFETs. Several different avalanche ratings areexplained and their usefulness and limitations in design is considered.Revision: 06-Dec-111Document Number: 90160THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENTARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000APPLICATION NOTEConclusion . 13
Application Note AN-1005www.vishay.comVishay SiliconixPower MOSFET Avalanche Design GuidelinesTABLE OF FIGURESAPPLICATION NOTEPageFigure 1Flyback Converter Circuit. 3Figure 2Flyback Converter Switch Under Avalanche Waveform . 3Figure 3Flyback Converter Switch Under Avalanche Waveform (Detail) . 3Figure 4Power MOSFET Cross Section .4Figure 5Power MOSFET Circuit Model . 4Figure 6Power MOSFET Cross Section Under Avalanche. 4Figure 7Basic Power MOSFET Cell Structure . 5Figure 8Power MOSFET Random Device Failure Spots . 5Figure 9Good Source Contact vs. Bad Source Contact Illustration . 6Figure 10IA at Failure vs. Test Temperature . 6Figure 11Single Pulse Unclamped Inductive Switching Test Circuit. 7Figure 12Single Pulse Unclamped Inductive Switching Test Circuit Output Waveforms . 7Figure 13Decoupled VDD Voltage Source Test Circuit Model . 7Figure 14Decoupled VDD Voltage Source Test Circuit Waveforms . 7Figure 15Typical Simulated Avalanche Waveforms . 8Figure 16IRFP450, SiHFP450 (500 V Rated) Device Avalanche Waveforms . 8Figure 17IRFP32N50K, SiHFP32N50K Datasheet Excerptions . 8Figure 18Transient Thermal Impedance Plot, Junction-to-Case . 9Figure 19Maximum Avalanche Energy vs. Temperature for Various Drain Currents . 9Figure 20EAR vs. Tstart for Various Duty Cycles, Single ID . 10Figure 21Typical Avalanche Current vs. Pulsewidth for Various Duty Cycles. 11Figure 22Specification of 40 V/14 A MOSFET Datasheet Excerptions . 11Figure 23Typical Effective Transient Thermal Impedance, Junction-to-Ambient . 12Revision: 06-Dec-112Document Number: 90160THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENTARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Application Note AN-1005www.vishay.comVishay SiliconixPower MOSFET Avalanche Design GuidelinesINTRODUCTIONOverviewTo better understand and utilize power MOSFETs, it isimportant to explore the theory behind avalanchebreakdown and to understand the design and rating ofrugged MOSFETs. Several different avalanche ratings areexplained and their usefulness and limitations in design isconsidered.VDSAvalanche Mode DefinedAll semiconductor devices are rated for a certain max.reverse voltage (BVDSS for power MOSFETs). Operationabove this threshold will cause high electric fields inreversed biased p-n junctions. Due to impact ionization, thehigh electric fields create electron-hole pairs that undergo amultiplication effect leading to increased current. Thereverse current flow through the device causes high powerdissipation, associated temperature rise, and potentialdevice destruction.VGSIDFig. 2 - Flyback Converter Switch Under Avalanche WaveformAvalanche Occurrences In Industry ApplicationsFlyback Converter CircuitSome designers do not allow for avalanche operation;instead, a voltage derating is maintained between ratedBVDSS and VDD (typically 90 % or less). In such instances,however, it is not uncommon that greater than planned forvoltage spikes can occur, so even the best designs mayencounter an infrequent avalanche event. One suchexample, a flyback converter, is shown in figures 1 to 3.AvalancheOperationVGSVDSIDL leakageFig. 3 - Flyback Converter Switch Under Avalanche Waveform(Detail)APPLICATION NOTENote Red (VDS), Blue (ID), Black (VGS)In this application, built in avalanche capability is anadditional power MOSFET feature and safeguards againstunexpected voltage over-stresses that may occur at thelimits of circuit operation.Fig. 1 - Flyback Converter CircuitDuring MOSFET operation of the flyback converter, energyis stored in the leakage inductor. If the inductor is notproperly clamped, during MOSFET turnoff the leakageinductance discharges through the primary switch and maycause avalanche operation as shown in the VDS, ID, and VGSvs. time waveforms in figures 2 and 3.Revision: 06-Dec-113Document Number: 90160THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENTARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Application Note AN-1005www.vishay.comVishay SiliconixPower MOSFET Avalanche Design GuidelinesAVALANCHE FAILURE MODEIn avalanche, the p-n junction acting as a diode no longerblocks voltage. With higher applied voltage a critical field isreached where impact ionization tends to infinity and carrierconcentration increases due to avalanche multiplication.Due to the radial field component, the electric field inside thedevice is most intense at the point where the junction bends.This strong electric field causes maximum current flow inclose proximity to the parasitic BJT, as depicted in figure 6below. The power dissipation increases temperature, thusincreasing RB, since silicon resistivity increases withtemperature. From Ohm’s Law we know that increasingresistance at constant current creates an increasing voltagedrop across the resistor. When the voltage drop is sufficientto forward bias the parasitic BJT, it will turn on withpotentially catastrophic results, as control of the switch islost.Some power semiconductor devices are designed towithstand a certain amount of avalanche current for a limitedtime and can, therefore, be avalanche rated. Others will failvery quickly after the onset of avalanche. The difference inperformance stems from particular device physics, design,and manufacturing.Power MOSFET Device PhysicsAll semiconductor devices contain parasitic componentsintrinsic to the physical design of the device. In powerMOSFETs, these components include capacitors due todisplaced charge in the junction between p and n regions,resistors associated with material resistivity, a body diodeformed where the p body diffusion is made into the nepi-layer, and an NPN (bi-polar junction transistorhenceforth called BJT) sequence (BJT) formed where the n source contact is diffused. See figure 4 for power MOSFETcross section that incorporates the parasitic componentslisted above and figure 5 for a complete circuit model of thedevice.Increasing RBParasitic BJTbeing F.B.Max. Current PathE FieldFig. 6 - Power MOSFET Cross Section Under AvalancheTypical modern power MOSFETs have millions of identicaltrenches, cells or many strips in parallel to form one device,as shown in figure 7. For robust designs, then, avalanchecurrent must be shared among many cells/strips evenly.Failure will then occur randomly in a single cell, at a hightemperature. In weak designs, the voltage required to reachbreakdown electric field is lower for one device region(group of cells) than for others, so critical temperature will bereached more easily causing the device to fail in one specificarea.APPLICATION NOTEFig. 4 - Power MOSFET Cross SectionFig. 5 - Power MOSFET Circuit ModelRevision: 06-Dec-114Document Number: 90160THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENTARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Application Note AN-1005www.vishay.comVishay SiliconixPower MOSFET Avalanche Design GuidelinesFig. 7 - Basic Power MOSFET Cell StructureRugged MOSFETsFirst introduced in the middle 1980’s, avalanche ruggedMOSFETs are designed to avoid turning on the parasitic BJTuntil very high temperature and/or very high avalanchecurrent occur. This is achieved by: Reducing the p region resistance with higher dopingdiffusion Optimizing cell/line layout to minimize the “length” of RBThe net effect is a reduction of RB, and thus the voltage dropnecessary to forward bias the parasitic BJT will occur athigher current and temperature.APPLICATION NOTEAvalanche rugged MOSFETs are designed to contain nosingle consistently weak spot, so avalanche occursuniformly across the device surface until failure occursrandomly in the active area. Utilizing the parallel design ofcells, avalanche current is shared among many cells andfailure will occur at higher current than for designs with asingle weak spot. A power MOSFET which is well designedfor ruggedness will only fail when the temperaturesubstantially exceeds rated TJ (max.).Fig. 8 - Power MOSFET Random Device Failure SpotsThe risk of manufacturing process or fabrication induced“weak cell” parts is always present. The SEM cross-sectionmicrograph on the top shows one such example. The sourcemetal contacts the n layer at the near surface, but not thep layer. As a result the BJT base is floating and easilytriggerable. An example of a good contact is shown on thebottom. The source metal contacts and shorts the n layerto the p layer thus supressing the parasitic BJT operation.An analysis of various MOSFET devices tested todestruction indicates that failure spots occur randomly inthe active area. Some samples are shown in the figure 8:Revision: 06-Dec-115Document Number: 90160THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENTARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Application Note AN-1005www.vishay.comVishay SiliconixPower MOSFET Avalanche Design GuidelinesA “three legged” approach is used during design:1. Statistically significant samples of prospective designsare tested to failure at test conditions chosen to reachextremes in temperature and current stress.Representative parts from DOE elements are tested toassure uniform avalanche failure across expectedvariation of critical process steps.2. Each design is tested to failure across temperature andinductor (time in avalanche) to assure that failureextrapolates to zero at a temperature well in excess ofTJ (max.). (See sample figure 10 of “IAS at failure vs. Tstart”below.)3. A sample of final design parts are stressed with repetitiveavalanche pulses of such a value to raise junctiontemperature to TJ (max.).This “three legged” solution helps assure that designs arerugged and can be avalanche rated.The following factors are used to provide rugged avalancheMOSFETs: Improved device design:- To mute the parasitic BJT by reducing RB- To eliminate the effect of weaker cells in particular positions of the layout (i.e. cells along device termination, gatebussing, etc.) Improved manufacturing process:- To guarantee more uniform cells- To reduce incomplete or malformed cell occurrences Improved device characterization:- To assure devices fail uniformly across wide range of ID,temperature- To assure device fails at very high (extrapolated) temperature- To assure device is capable of surviving multiple avalanche cycles at the thermal limit 100 % avalanche stress testingBad Contactn p n-Good Contactn p n-Fig. 9 - Good Source Contact vs. Bad Source Contact IllustrationParts with weak cells such as are shown on the top offigure 9 can be removed from the population by 100 %avalanche (EAS) stress testing during production.IAS at Failure vs. Tstart300Inductor Values S FailAPPLICATION NOTE2501501005000100200300400500600Temperature ( C)Fig. 10 - IAS at Failure vs. Test TemperatureRevision: 06-Dec-116Document Number: 90160THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENTARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Application Note AN-1005www.vishay.comVishay SiliconixPower MOSFET Avalanche Design GuidelinesAVALANCHE TESTING DETAILSDecoupled VDD Voltage SourceVishay performs avalanche stress testing on its powersemiconductor devices to assure conformance of newdesigns with avalanche rating, to validate parts forruggedness, and to screen production for weak devices.To surpass the limitations of the single pulse unclampedinductive switching test circuit, the decoupled VDD voltagesource illustrated in figures 13 and 14 is used.Single Pulse Unclamped Inductive Switching15 VA single pulse unclamped inductive switching test circuit foravalanche testing that is shown below in figures 11 and 12.This circuit is still referenced in older “legacy” productdatasheets.DriverLVDSRgD.U.T. A- VDDIAS20 Vtp0.01 ΩFig. 13 - Decoupled VDD Voltage Source Test Circuit ModelVDStpIASFig. 11 - Single Pulse Unclamped Inductive Switching Test CircuitFig. 14 - Decoupled VDD Voltage Source Test Circuit WaveformsFrom the figure 11 schematic we can calculate the singlepulse avalanche energy (EAS) as:Here a driver FET and recirculation diode are added so thatthe voltage drop across the inductor during avalanche isequal to the avalanche voltage. With this circuit (neglectingthe angular ESR in the inductor) the energy can be simplycalculated as:2L x IAS V DSE AS -------------------------- x --------------------------2V DS - V DD(1)APPLICATION NOTEThe measured energy values depend on the avalanchebreakdown voltage, which tends to vary during thedischarge period due to the temperature increase. Also notethat for low voltage devices VDS - VDD may become quitesmall, limiting the use of this circuit since it introduceshigh-test error.12E AS --- L x I AS (2)2A better and more accurate reading of the avalanche energycan be obtained by measuring instantaneous voltage andcurrent in the device and integrating as described in thefollowing equation:t2E AS V(AV)DSS t x IAS t x dt(3)t1For further reference, figures 15 and 16, depict ideal andactual avalanche waveforms, respectively.Fig. 12 - Single Pulse Unclamped Inductive Switching Test CircuitOutput WaveformsRevision: 06-Dec-117Document Number: 90160THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENTARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Application Note AN-1005www.vishay.comVishay SiliconixPower MOSFET Avalanche Design GuidelinesGate VoltageIRFP450,SiHFP450VDD 50 VL 7 mHIAS 14 ATJ 25 CInductorChargingIpkVAVat 50 μs/div.IDDrainVAVAvalanchePhaseDrain VoltageFig. 15 - Typical Simulated Avalanche WaveformsFig. 16 - IRFP450, SiHFP450 (500 V Rated) Device AvalancheWaveformsNote
Power MOSFET Avalanche Design Guidelines APPLICATION NOTE Application Note AN-1005 www.vishay.com Vishay Siliconix Revision: 06-Dec-11 2 Document Number: 90160 THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE.
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As the power density in SJ MOSFET grows, so does complexity - both of the construction of the MOSFET and the interaction with application. Of particular interest is the non-linearity of the inherent parasitic MOSFET capacitances. Most (all) modern SJ MOSFET Data Sheets are structured in a two-tiered approach; The typical values given
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