RFSoC 2x2 User Manual - RFSoC 2x2 Kit RFSoC 2x2
RFSoC 2x2 User ManualHiTech Global ZYNQ UltraScale RFSoC Development PlatformRFSOC 2x2 User ManualVersion 1.0 January 2021Copyright HiTech Global 2004-20211www.HiTechGlobal.com
RFSoC 2x2 User ManualDisclaimerHiTech Global does not assume any liability arising out of the application or use of any product described orshown herein; nor does it convey any license under its patents, copyrights, or mask work rights or any rights ofothers. HiTech Global reserves the right to make changes, at any time, in order to improve reliability andfunctionality of this product. HiTech Global will not assume responsibility for the use of any circuitry describedherein other than circuitry entirely embodied in its products. HiTech Global provides any design, code, orinformation shown or described herein "as is." By providing the design, code, or information as one possibleimplementation of a feature, application, or standard, HiTech Global makes no representation that suchimplementation is free from any claims of infringement. End users are responsible for obtaining any rights theymay require for their implementation. HiTech Global expressly disclaims any warranty whatsoever with respectto the adequacy of any such implementation, including but not limited to any warranties or representations thatthe implementation is free from claims of infringement, as well as any implied warranties of merchantability orfitness for a particular purpose.HiTech Global will not assume any liability for the accuracy or correctness of any engineering or softwaresupport or assistance provided to a user. HiTech Global products are not intended for use in life supportappliances, devices, or systems. Use of a HiTech Global product in such applications without the writtenconsent of the appropriate HiTech Global officer is prohibited.The contents of this manual are owned and copyrighted by HiTech Global Copyright HiTech Global All RightsReserved. Except as stated herein, none of the material may be copied, reproduced, distributed, republished,downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to,electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of HiTechGlobal. Any unauthorized use of any material contained in this manual may violate copyright laws, trademarklaws, the laws of privacy and publicity, and communications regulations and statutes.Revision Notes
RFSoC 2x2 User ManualTable Of Contents1.0) Overview42.0) RFSOC 2X2Features53.0) Banks Assignment, Block Diagram & Clocks Diagram54.0) Main Clocks95.0) DDR4 Memory116.0) ADC and DAC Ports187.0) USB Ports228.0) SDIO Interface239.0) 10/100/1000 Mbps Ethernet2310.0) Display Port2411.0) 1-PPS Interface2512.0) PMOD Ports2513.0) SYZYGY Port2614.0) LEDs, User Switch & Pushbuttons2715.0) Configuration28TablesTable (1): Summary of supported ZYNQ RFSoC UltraScale FPGA Feature5Table (2): Main Clocks11Table (3): Summary of the Si5340 (U54) Clock Outputs12Table (4): DDR4 FPGA Pin Assignment (PL Side)16Table (5) DDR4 FPGA Pin Assignment (Processor Side)19Table (6): ADC Interface Pin Assignment20Table (7): DAC Interface Pin Assignment20Table (8): USB Interface Pin Assignment25Table (9): SDIO Port’s FPGA Pin Assignment25Table (10): Ethernet Port’s FPGA Pin Assignment26Table (11): Display Port’s FPGA Pin Assignment27Table (12): 1-PPS Port’s FPGA Pin Assignment27Table (13): PMOD Ports’ FPGA Pin Assignment28Table (14): SYZYGY Voltage Configuration28Table (15): SYZYGY Port’s FPGA Pin Assignment29Table (16): User Interface FPGA Pin Assignment3www.HiTechGlobal.com
RFSoC 2x2 User ManualFiguresFigure (1): FPGA I/O Bank Assignment7Figure (2): System Block Diagram8Figure (3): Clock Block Diagram9Figure (4): User Interface Ports/Controls10Figure (5): Si5340 Clock Generator Block Diagram12Figure (6): LMX2594 Block Diagram13Figure (7): ADC Ports – FPGA Interface21Figure (8): DAC Ports – FPGA Interface22Figure (9): ADC/DAC Clock Configuration234www.HiTechGlobal.com
RFSoC 2x2 User Manual 1.0) OverviewPopulated with one Xilinx ZYNQ UltraScale RFSoC ZU28DR FPGA device, the RFSoC 2x2 platformprovides access to large FPGA gate densities, two ADC/DAC ports, DDR4 memory, Gigabit Ethernet, USB ,display port, PMOD and SYZYGY ports for variety of different programmable applications.The RFSoC 2x2 platform is supported by two 12-bit ADC (4GSPS) and two14-bit DAC (6.4GSPS) ports. TheADC and DAC ports are supported through high-performance front panel micro Rf connectors. This boardsupports Multi-Tile Synchronization of the ADC/DAC channels.Table (1) illustrates key features of the supported FPGAs by the RFSoC 2x2 platform.Table (1): Summary of supported ZYNQ RFSoC UltraScale FPGA Features5www.HiTechGlobal.com
RFSoC 2x2 User Manual 2.0) Hardware Features Xilinx Zynq UltraScale RFSoC ZU28DR (-2 speed grade) x2 ADC (12-bit , 4GSPS) ports (SMA connectors) x2 DAC (14-bit, 6.4GSPS) ports (SMA connectors) Support for Multi-Tile Synchronization of ADC/DAC channels Programmable ADC/DAC Clock Generator Independent DDR4 memory for the FPGA and processors (4GB components) x1 10/100/1000 Ethernet (RJ45) port (Processor Side) x1 MicroSD (Processor Side) x2 PMOD Port s(Programmable Logic Side) SYZYGY port (Programmable Logic Side) x1 Display Port (Processor Side) x2 (stacked) USB 3.0 Host (Processor Side) x1 USB 3.0 Slave (Processor Side) x1 USB 2.0 Slave (Processor Side) Programmable clocks x1 1PPS port (Programmable Logic Side) Current monitors Pushbuttons and LEDs FPGA JTAG header External synchronous clock port x2 SMA to SMA cables (12”) x1 wall power adapter (US. plug / 12V) 3.0) Banks Assignment, Block Diagram & Clocks DiagramFigure (1) , (2), (3) and illustrate FPGA I/O bank assignment, system block, clocks and user interfaceports/controls diagrams of the RFSoC 2x2 platform.6www.HiTechGlobal.com
RFSoC 2x2 User ManualFigure (1): FPGA I/O Bank Assignment7www.HiTechGlobal.com
RFSoC 2x2 User ManualFigure (2): System Block Diagram8www.HiTechGlobal.com
RFSoC 2x2 User ManualFigure (3): Clock Block Diagram9www.HiTechGlobal.com
RFSoC 2x2 User ManualFigure (4): User Interface Ports/Controls10www.HiTechGlobal.com
RFSoC 2x2 User Manual 4.0) Main ClocksThe RFSoC 2x2 platform provides combination of fixed, programmable, and adjustable ultra-low-jitter clocksources for different interfaces as summarized by the table (2).SourcePart Number (Manufacturer)LMK04832NKDDefault Value33.3333, 27, 100and 200 MHz /ProgrammableProgrammableU54Si5340AU2Clock FunctionClock Jitter Cleaner (ADC/DAC)U4LMX2594RHAProgrammableDAC 228 & DAC 229U13LMX2594RHAProgrammableADC 224 & ADC 226U72ECS-TXO-5032-122.812.288 MHzClock Jitter Cleaner Reference (ADC/DAC)U1ABLNO-V-122.88MHZ122.88 MHzClock Jitter Cleaner Reference (ADC/DAC)ZQ1FA-238 25.0000MB25 MHzUSB3 HUB ControllerZQ2FA-238 25.0000MB25 MHzEthernetZQ3FA-238 24.0000MB24 MHzUSB2 ULPI Transceiver (U48)ZQ47M4807200248 MHzU54 Clock Generator ReferenceZQ5FA-238 24.0000MB24 MHzUSB2 ULPI Transceiver (U55)ZQ69HT10-32.768KDZF-T32.768 KHzPS PADI/PS PADO RTCZQ7FA-238V 12.0000MB-W312.00 MHzFTDI / USB Reference CLKJ7SMA ConnectorVariableCLK-IN for U2 Clock Cleaner (ADC/DAC)J6SMA ConnectorVariableSYNC-IN for U2 Clock Cleaner (ADC/DAC)PS, GTR505 & DDR4Table (2): Main Clocks Theany-frequency, any-output Si5340 (U54) clock generator combines a wide-band PLL with proprietaryMultiSynth fractional synthesizer technology to offer a versatile and high performance clock generatorplatform. This highly flexible architecture is capable of synthesizing a wide range of integer and no-integerrelated frequencies up to 712.5 MHz on 4 differential clock outputs while delivering sub-100 fs rms phase jitterperformance with 0 ppm error. Each of the clock outputs can be assigned its own format and output voltageenabling the Si5340 to replace multiple clock ICs and oscillators with a single device making it a true “clocktree on a chip”.The Si5340 can be quickly and easily reconfigured using the ClockBuilder Pro software. The device can beprogrammed in circuit via I2C and SPI serial interfaces or using Silicon Labs’ CBPROG dongle and the J19header. The NVM of the Si5340 can be programmed only once on the RFSoC 2x2 iTechGlobal.com
RFSoC 2x2 User ManualFigure (5): Si5340 Clock Generator Block DiagramTable (3) provides summary of clock outputs of the Si5340 (U54) clock generator.Output #OUT0 POUT0 NOUT1 POUT1 NOUT2 POUT2 NOUT3 POUT3 NSignal NamePS CLKGTR 505 REFCLK1 PGTR 505 REFCLK1 NGTR 505 REFCLK2 PGTR 505 REFCLK2 NSYS CLK DDR4 PL PSYS CLK DDR4 PL NCLK ValueDestination33.33333 MHzProcessor CLK27 MHzUSB0, USB1 &Display Port100 MHzUSB0, USB1 &Display Port200 MHzDDR4 CLK (PL)Table (3): Summary of the Si5340 (U54) Clock Outputs12www.HiTechGlobal.comFPGA Pin #AC30AJ34AJ35AG34AG35G13G12
RFSoC 2x2 User Manual TheLMX2594 (U4 & U13) is a high performance wideband synthesizer (PLL with integrated VCO). Theoutput frequency range is from 20 MHz to 5.5 GHz. The VCO core covers an octave from 3.55 to 7.1 GHz. Theoutput channel divider covers the frequency range from 20 MHz to the low bound of the VCO core.The input signal frequency has a wide range from 5 to 1400 MHz. Following the input, there is anprogrammable OSCin doubler, a pre-R divider (previous to multiplier), a multiplier, and then a post-R divider(after multiplier) for flexible frequency planning between the input (OSCin) and the phase detector.The phase detector (PFD) can take frequencies from 5 to 200 MHz, but also has extended modes down to 0.25MHz and up to 400 MHz. The phase-lock loop (PLL) contains a Sigma-Delta modulator (1st to 4th order) forfractional N-divider values. The fractional denominator is programmable to 32-bit long, allowing a very fineresolution of frequency step. There is a phase adjust feature that allows shifting of the output phase in relationto the input (OSCin) by a fraction of the size of the fractional denominator.The output power is programmable and can be designed for high power at a specific frequency by the pullupcomponent at the output pin.The digital logic is a standard 4-wire SPI or uWire interface and is 1.8-V and 3.3-V compatible.The onboard LMX2594 should be programmed using Texas Instruments’ TICS PRO software(http://www.ti.com/tool/TICSPRO-SW)Figure (6): LMX2594 Block Diagram 5.0) DDR4 MemoryThe RFSoC 2x2 platform provides access to 4GB of DDR4 memory for the PS and PL side each. (PartNumber: MT40A512M16LY-075:E).Table (4) and (5) illustrate the FPGA bank assignment for the DDR4 PL and PS sides.DDR4 Signal Name (PL Side)FPGA Pin #DDR4 PL A0H6DDR4 PL A1G7DDR4 PL A10H1113www.HiTechGlobal.com
RFSoC 2x2 User ManualDDR4 PL A11A11DDR4 PL A12E12DDR4 PL A13B14DDR4 PL A14K13DDR4 PL A15D14DDR4 PL A16E13DDR4 PL A2B13DDR4 PL A3F10DDR4 PL A4F11DDR4 PL A5D13DDR4 PL A6J7DDR4 PL A7A15DDR4 PL A8A12DDR4 PL A9A14DDR4 PL ACT NH13DDR4 PL ALERT NG8DDR4 PL BA0E14DDR4 PL BA1H10DDR4 PL BG0H12DDR4 PL CK CJ10DDR4 PL CK TJ11DDR4 PL CKEF12DDR4 PL CS NE11DDR4 PL DM DBI N0J15DDR4 PL DM DBI N1N14DDR4 PL DM DBI N2D18DDR4 PL DM DBI N3G17DDR4 PL DM DBI N4F21DDR4 PL DM DBI N5J23DDR4 PL DM DBI N6C23DDR4 PL DM DBI N7N20DDR4 PL DQ0H17DDR4 PL DQ1J16DDR4 PL DQ10M15DDR4 PL DQ11M12DDR4 PL DQ12M17DDR4 PL DQ13L12DDR4 PL DQ14N15DDR4 PL DQ15N13DDR4 PL DQ16A19DDR4 PL DQ17A1614www.HiTechGlobal.com
RFSoC 2x2 User ManualDDR4 PL DQ18C17DDR4 PL DQ19C16DDR4 PL DQ2H16DDR4 PL DQ20B19DDR4 PL DQ21D16DDR4 PL DQ22A17DDR4 PL DQ23D15DDR4 PL DQ24E18DDR4 PL DQ25F16DDR4 PL DQ26E17DDR4 PL DQ27G15DDR4 PL DQ28G18DDR4 PL DQ29F15DDR4 PL DQ3K16DDR4 PL DQ30E16DDR4 PL DQ31H18DDR4 PL DQ32E24DDR4 PL DQ33D21DDR4 PL DQ34E22DDR4 PL DQ35E21DDR4 PL DQ36F24DDR4 PL DQ37F20DDR4 PL DQ38E23DDR4 PL DQ39G20DDR4 PL DQ4J18DDR4 PL DQ40K24DDR4 PL DQ41G22DDR4 PL DQ42J21DDR4 PL DQ43G23DDR4 PL DQ44L24DDR4 PL DQ45H22DDR4 PL DQ46H23DDR4 PL DQ47H21DDR4 PL DQ48C21DDR4 PL DQ49A24DDR4 PL DQ5K17DDR4 PL DQ50C22DDR4 PL DQ51B24DDR4 PL DQ52B20DDR4 PL DQ53A21DDR4 PL DQ54C2015www.HiTechGlobal.com
RFSoC 2x2 User ManualDDR4 PL DQ55A20DDR4 PL DQ56M20DDR4 PL DQ57L20DDR4 PL DQ58L22DDR4 PL DQ59L21DDR4 PL DQ6J19DDR4 PL DQ60N19DDR4 PL DQ61M19DDR4 PL DQ62L23DDR4 PL DQ63L19DDR4 PL DQ7L17DDR4 PL DQ8N17DDR4 PL DQ9M13DDR4 PL DQS C0K18DDR4 PL DQS C1L14DDR4 PL DQS C2B17DDR4 PL DQS C3F19DDR4 PL DQS C4D24DDR4 PL DQS C5H20DDR4 PL DQS C6A22DDR4 PL DQS C7K22DDR4 PL DQS T0K19DDR4 PL DQS T1L15DDR4 PL DQS T2B18DDR4 PL DQS T3G19DDR4 PL DQS T4D23DDR4 PL DQS T5J20DDR4 PL DQS T6B22DDR4 PL DQS T7K21DDR4 PL ODTF14DDR4 PL PARB12DDR4 PL RST NG6DDR4 PL TENC15SYS CLK DDR4 PL NSYS CLK DDR4 PL PTable (4): DDR4 FPGA Pin Assignment (PL Side)16www.HiTechGlobal.comG12G13
RFSoC 2x2 User ManualDDR4 Signal Name (Processor Side)FPGA Pin #DDR4 PS A0AV31DDR4 PS A1AW28DDR4 PS A10AT31DDR4 PS A11AT32DDR4 PS A12AT30DDR4 PS A13AU32DDR4 PS A14AR28DDR4 PS A15AP30DDR4 PS A16AP28DDR4 PS A2AV28DDR4 PS A3AU29DDR4 PS A4AW31DDR4 PS A5AU28DDR4 PS A6AL29DDR4 PS A7AM30DDR4 PS A8AM29DDR4 PS A9AP29DDR4 PS ACT NAL30DDR4 PS ALERT NAL32DDR4 PS BA0AN30DDR4 PS BA1AM32DDR4 PS BG0AN32DDR4 PS CK CAV30DDR4 PS CK TAU30DDR4 PS CKEAW30DDR4 PS CS NAW29DDR4 PS DM DBI N0AU23DDR4 PS DM DBI N1AT27DDR4 PS DM DBI N2AL24DDR4 PS DM DBI N3AM27DDR4 PS DM DBI N4AV36DDR4 PS DM DBI N5AT35DDR4 PS DM DBI N6AM36DDR4 PS DM DBI N7AJ32DDR4 PS DQ0AW25DDR4 PS DQ1AW24DDR4 PS DQ10AU25DDR4 PS DQ11AR27DDR4 PS DQ12AU27DDR4 PS DQ13AV2617www.HiTechGlobal.com
RFSoC 2x2 User ManualDDR4 PS DQ14AV27DDR4 PS DQ15AW26DDR4 PS DQ16AP25DDR4 PS DQ17AP24DDR4 PS DQ18AP23DDR4 PS DQ19AN25DDR4 PS DQ2AV25DDR4 PS DQ20AM25DDR4 PS DQ21AK24DDR4 PS DQ22AN23DDR4 PS DQ23AK23DDR4 PS DQ24AK26DDR4 PS DQ25AL25DDR4 PS DQ26AK28DDR4 PS DQ27AK27DDR4 PS DQ28AN27DDR4 PS DQ29AN26DDR4 PS DQ3AW23DDR4 PS DQ30AN28DDR4 PS DQ31AM28DDR4 PS DQ32AU39DDR4 PS DQ33AU38DDR4 PS DQ34AU37DDR4 PS DQ35AU35DDR4 PS DQ36AV38DDR4 PS DQ37AW36DDR4 PS DQ38AV35DDR4 PS DQ39AW35DDR4 PS DQ4AV23DDR4 PS DQ40AU33DDR4 PS DQ41AV33DDR4 PS DQ42AW34DDR4 PS DQ43AW33DDR4 PS DQ44AR34DDR4 PS DQ45AR33DDR4 PS DQ46AP33DDR4 PS DQ47AP34DDR4 PS DQ48AL39DDR4 PS DQ49AM38DDR4 PS DQ5AV22DDR4 PS DQ50AM3918www.HiTechGlobal.com
RFSoC 2x2 User ManualDDR4 PS DQ51AN38DDR4 PS DQ52AM35DDR4 PS DQ53AM34DDR4 PS DQ54AN36DDR4 PS DQ55AN35DDR4 PS DQ56AK32DDR4 PS DQ57AK31DDR4 PS DQ58AJ31DDR4 PS DQ59AJ30DDR4 PS DQ6AR24DDR4 PS DQ60AH30DDR4 PS DQ61AG32DDR4 PS DQ62AF32DDR4 PS DQ63AG30DDR4 PS DQ7AR23DDR4 PS DQ8AT25DDR4 PS DQ9AP26DDR4 PS DQS C0AU24DDR4 PS DQS C1AT26DDR4 PS DQS C2AM24DDR4 PS DQS C3AL27DDR4 PS DQS C4AW37DDR4 PS DQS C5AU34DDR4 PS DQS C6AN37DDR4 PS DQS C7AH32DDR4 PS DQS T0AT24DDR4 PS DQS T1AR26DDR4 PS DQS T2AM23DDR4 PS DQS T3AL26DDR4 PS DQS T4AV37DDR4 PS DQS T5AT34DDR4 PS DQS T6AM37DDR4 PS DQS T7AH31DDR4 PS ODTAV32DDR4 PS PARAN31DDR4 PS RST NAM33Table (5) DDR4 FPGA Pin Assignment (Processor Side)19www.HiTechGlobal.com
RFSoC 2x2 User Manual 6.0) ADC and DAC PortsThe RFSoC 2x2 platform provides access to two ADC and two DAC ports through four SMA connectors. Asshowed by figures (7) and (8), the ADC and DAC ports are supported through high-performance frontpanel Mini Circuits TCM1-83X micro Rf transformer with bandwidth ranging from 10 to 8000 MHz. A PiAttenuator circuit is placed between these Rf transformers and the RF MPSoC.Table (6) illustrates FPGA pin assignments for the ADC interfaces.ADC Signal NameFPGA Pin #ADC 224 REFCLK NAF4Connector #-ADC 224 REFCLK PAF5-ADC 226 REFCLK NAB4-ADC 226 REFCLK PAB5-ADC IN01 224 NAP1J5ADC IN01 224 PAP2J5ADC IN01 226 NAF1J4ADC IN01 226 PAF2J4Table (6): ADC Interface Pin AssignmentTable (7) illustrates FPGA pin assignments for the DAC interfaces.DAC Signal NameFPGA Pin #Connector #DAC 228 REFCLK NR4-DAC 228 REFCLK PR5-DAC 228 SYSREF NU4-DAC 228 SYSREF PU5-DAC 229 REFCLK NN4-DAC 229 REFCLK PN5-DAC VOUT0 228 NU1J3DAC VOUT0 228 PU2J3DAC VOUT0 229 NJ1J2DAC VOUT0 229 PJ2J2Table (7): DAC Interface Pin AssignmentFigures (7) and (8) illustrate ADC/DAC interface paths from SMA connectors to the FPGA’s ADC/DAC tiles.20www.HiTechGlobal.com
RFSoC 2x2 User ManualFigure (7): ADC Ports – FPGA Interface21www.HiTechGlobal.com
RFSoC 2x2 User ManualFigure (8): DAC Ports – FPGA Interface6.1) ADC/DAC ClocksThe Texas Instruments components used for the ADC and DAC ports should be programmed using TexasInstruments’ TICS PRO software (http://www.ti.com/tool/TICSPRO-SW) . All LMX2594 components areblank and must be programmed according to the end application.Figure (9) illustrates high level block configuration of the ADC/DAC channels.22www.HiTechGlobal.com
RFSoC 2x2 User ManualFigure (9): ADC/DAC Clock Configuration23www.HiTechGlobal.com
RFSoC 2x2 User Manual 7.0) USBPortsThe RFSoC 2x2 platform provides access to the following USB ports:-Two USB 3.0 Host ports (J14/stacked) accessing GTR transceiver of the FPGA through a USB Hubcontroller.One USB 3.0 Slave port (J13) connected to one GTR transceiver of the FPGA and the processor’s I/Osthrough two USB 2.0 ULPI transceivers.One USB 2.0 Slave port (J11) for UART and JTAG programming of the FPGA.Reference clock for the USB3.0 serial transceivers is provided by the onboard SI5340 clock generator.The USB interfaces are protected by ultra-low capacitance TVS Arrays to protect the circuitry against voltagespikes originated from electro static discharge (ESD) and inductive load switching.Table (8) illustrates FPGA pin assignment for the USB interfaces.USB Signal NameMIO52 USB0 CLKMIO53 USB0 DIRMIO54 USB0 D2MIO55 USB0 NXTMIO56 USB0 D0MIO57 USB0 D1MIO58 USB0 STPMIO59 USB0 D3MIO6 PS USER PBMIO60 USB0 D4MIO61 USB0 D5MIO62 USB0 D6MIO63 USB0 D7MIO64 USB1 CLKMIO65 USB1 DIRMIO66 USB1 D2MIO67 USB1 NXTMIO68 USB1 D0MIO69 USB1 D1MIO7 USB RESET BMIO70 USB1 STPMIO71 USB1 D3MIO72 USB1 D4MIO73 USB1 D5MIO74 USB1 D6MIO75 USB1 D7USB0 US RXNFPGA Pin Global.comUSB FunctionUSB 3.0 SlaveUSB 3.0 SlaveUSB 3.0 SlaveUSB 3.0 SlaveUSB 3.0 SlaveUSB 3.0 SlaveUSB 3.0 SlaveUSB 3.0 SlaveUSB 3.0 SlaveUSB 3.0 SlaveUSB 3.0 SlaveUSB 3.0 SlaveUSB 3.0 SlaveUSB 3.0 HostUSB 3.0 HostUSB 3.0 HostUSB 3.0 HostUSB 3.0 HostUSB 3.0 HostUSB 3.0 HostUSB 3.0 HostUSB 3.0 HostUSB 3.0 HostUSB 3.0 HostUSB 3.0 HostUSB 3.0 Slave
RFSoC 2x2 User ManualUSB0 US RXPUSB0 US TXNUSB0 US TXPUSB1 DS RXNUSB1 DS RXPUSB1 DS TXNUSB1 DS TXPAE38AF37AF36AC39AC38AD37AD36USB 3.0 SlaveUSB 3.0 SlaveUSB 3.0 SlaveMIO18 UART0 RXDY27USB 2.0 Slave (UART/JTAG)MIO19 UART0 TXDW28USB 2.0 Slave (UART/JTAG)USB 3.0 HostUSB 3.0 HostUSB 3.0 HostUSB 3.0 HostTable (8): USB Interface Pin Assignment 8.0) SDIO InterfaceThe RFSoC 2x2 platform supports a secure digital input/output (SDIO) interface providing access to generalpurpose non-volatile SDIO memory cards and peripherals. The SDIO signals are connected to the PS bank 501of the onboard Zynq UltraScale FPGA. A SD 3.0-compliant voltage level-translator (P4856CX25/C ) ispresent between the onboard Zynq UltraScale RFSoC FPGA and the SD card connector (J18). The JP1connector (marked as “Prog Mode on figure 4) has the factory default setting to boot through the SD cardinterface.Table (9) illustrates FPGA pin assignment for the SDIO Interface.FPGA Signal NameFPGA Pin NumberMIO39 SDIO SELB28MIO40 SDIO DIR CMDD26MIO41 SDIO DIR DAT0C28MIO42 SDIO DIR DAT1E28MIO44 SDIO PROTECTF27MIO45 SDIO DETECTG27MIO46 SDIO DAT0A29MIO47 SDIO DAT1C29MIO48 SDIO DAT2D29MIO49 SDIO DAT3B29MIO50 SDIO CMDF29MIO51 SDIO CLKE29Table (9): SDIO Port’s FPGA Pin Assignment 9.0) 10/100/1000 Mbps EthernetThe RFSoC 2x2 platform provides access to one 10/100/1000 Mbps Ethernet port (J16) supported by TexasInstruments DP83867IRPAP PHY chip connected to the processor’s I/Os of the FPGA.25www.HiTechGlobal.com
RFSoC 2x2 User ManualThe DP83867 device is a fully featured Physical Layer transceiver with integrated PMD sublayers to support10BASE-Te, 100BASE-TX and 1000BASE-T Ethernet protocols. This device interfaces directly to the MAClayer through the IEEE 802.3 Standard Media Independent Interface (MII), the IEEE 802.3 Gigabit MediaIndependent Interface (GMII) or Reduced GMII (RGMII). The DP83867 provides precision clocksynchronization, including a synchronous Ethernet clock output. It has low latency and provides IEEE 1588Start of Frame Detection.The Ethernet activities are reported by the following LEDs:- LINK (on the RJ45 connector): By default, this pin indicates that link is established.- ACT: (on the RJ45 connector): By default, this pin indicates receive or transmit activity.- D35: (on the board/next to the RJ45 connector): By default, this pin indicates that 1000BASE-T link isestablished.Table (10) illustrates FPGA pin assignment for the Ethernet interface.FPGA Signal NameFPGA Pin NumberMIO26 ETH TX CLKG25MIO27 ETH TX D0C25MIO28 ETH TX D1F25MIO29 ETH TX D2B25MIO30 ETH TX D3D25MIO31 ETH TX CTRLC26MIO32 ETH RX CLKA26MIO33 ETH RX D0A27MIO34 ETH RX D1B27MIO35 ETH RX D2E26MIO36 ETH RX D3C27MIO37 ETH RX CTRLF26Table (10): Ethernet Port’s FPGA Pin Assignment 10.0) Display PortThe RFSoC 2x2 platform provides access to one Display Port (J12) connected to the processor’s single-endedand serial I/Os of the FPGA.Reference clock for the Display Port GTR serial transceivers is provided by the onboard SI5340 clock generator.Table (11) illustrates FPGA pin assignment for the Display Port interface.FPGA Signal NameFPGA Pin NumberDP TX0 NDP TX0 PDP TX1 NAH37AH36AK3726www.HiTechGlobal.com
RFSoC 2x2 User ManualDP TX1 PMIO22 DP AUX OUTMIO23 DP HPDMIO24 DP OEMIO25 DP AUX INAK36AG18AH18AF20AF19Table (11): Display Port’s FPGA Pin Assignment 11.0) 1-PPS InterfaceThe RFSoC 2x2 platform provides access to one 1-PPS interface through one SMA connector (J1), oneComparator, one 8-bit ADC (3MSPS), and one Schmitt-Trigger Buffer.Table (12) illustrates FPGA pin assignment for the 1-PPS interface.FPGA Signal NameFPGA Pin NumberIRIG ADC CS NAG13IRIG ADC SCLKAG12IRIG ADC SDOAG14IRIG COMP OUTAH13IRIG TRIG OUTAH12Table (12): 1-PPS Port’s FPGA Pin Assignment 12.0) PMOD PortsThe RFSoC 2x2 platform provides access to two 2x6 PMOD ports (J22 and J23) for interfacing to Digilent’sdauther cards tors )Table (13) illustrates FPGA pin assignment for the PMOD interfaces.FPGA Signal NamePMOD0 0 FFPGA Pin NumberAT16PMOD0 1 FAW16PMOD0 2 FAV16PMOD0 3 FAU15PMOD0 4 FAV13PMOD0 5 FAU13PMOD0 6 FAU14PMOD0 7 FAT15PMOD1 0 FAJ15PMOD1 1 FAL15PMOD1 2 FAJ1627www.HiTechGlobal.com
RFSoC 2x2 User ManualPMOD1 3 FAK16PMOD1 4 FAM17PMOD1 5 FAP15PMOD1 6 FAL16PMOD1 7 FAK17Table (13): PMOD Ports’ FPGA Pin Assignment 13.0) SYZYGY PortThe RFSoC 2x2 platform platform provides access to one Standard SYZYGY port (J17) with the followingfeatures:- 40-pin 0.8mm Samtec connector- 5V, 3.3V fixed voltages- Programmable VIO supply- MCU for peripheral personality and VIO setting- 8 differential pairs (or 16 single-ended signals)- 12 additional single-ended signals- Dedicated clock inputs/outputsThe power supply is programmable from 1.2V to 3.3V by using the on-board MCU (U22) and configurationcodes shown by the table (14).Table (14): SYZYGY Voltage ConfigurationThe power status LED (D46) will only turn on when a module is plugged to the SYZYGY connector.Table (15) illustrates FPGA pin assignment for the SYZYGY interface.FPGA Signal NameFPGA Pin NumberSYZYGY C2P CLKNB9SYZYGY C2P CLKPB10SYZYGY P2C CLKNAV5SYZYGY P2C CLKPAV6SYZYGY S0 D0PAT7SYZYGY S1 D1PF6SYZYGY S10 D4NAW328www.HiTechGlobal.com
RFSoC 2x2 User ManualSYZYGY S11 D5NA6SYZYGY S12 D6PAV3SYZYGY S13 D7PC8SYZYGY S14 D6NAV2SYZYGY S15 D7NC7SYZYGY S16AV7SYZYGY S17B8SYZYGY S18AV8SYZYGY S19C5SYZYGY S2 D0NAT6SYZYGY S20AU8SYZYGY S21A5SYZYGY S22AU7SYZYGY S23D6SYZYGY S24AR7SYZYGY S25B5SYZYGY S26AR6SYZYGY S27C6SYZYGY S3 D1NE6SYZYGY S4 D2PAU2SYZYGY S5 D3PE9SYZYGY S6 D2NAU1SYZYGY S7 D3NE8SYZYGY S8 D4PAW4SYZYGY S9 D5PA7SYZYGY VIO ENAR13Table (15): SYZYGY Port’s FPGA Pin Assignment 14.0) LEDs , User Switch & PushbuttonsThe RFSoC 2x2 platform provides user LEDs, XDAC headers, user I/O headers, and Push Buttons.Table (16) illustrates FPGA pin assignment and reference designators for each interface.FPGA Signal NameFPGA Pin NumberPL LEDRGB0 BAW11Reference DesignatorD13PL LEDRGB0 GAT11D13PL LEDRGB0 RAV11D13PL LEDRGB1 BAR11D15PL LEDRGB1 GAN12D15PL LEDRGB1 RAN13D1529www.HiTechGlobal.com
RFSoC 2x2 User ManualPL URSTAP9PB8PL USER LED0 WAR12D16PL USER LED1 WAT12D17PL USER LED2 WAV12D18PL USER LED3 WAU12D19PL USER PB0AM7PB2PL USER PB1AM8PB4PL USER PB2AN8PB6PL USER PB3AP8PB7MIO6 PS PBW26PB9PS PORN NAB29PB1PS SRST NAB28PB5PS PROG NAA27PB3PL USER SW1AT10S1: KEY 1PL USER SW2AU10S1: KEY 2PL USER SW3AV10S1: KEY 3PL USER SW4AW10S1: KEY 4MIO4 PS LED0 GV26D30MIO5 PS LED1 GAA26D32Table (16): User Interface FPGA Pin Assignment 15.0) ConfigurationThe RFSoC 2x2 platform can be configured through its Jtag (J8), USB 2 (J11) or MicroSD (J18) ports. Themode select is controlled through inserting shunt on the JP1 header next to the Jtag connector (J8) withconnection on pins 1-2 for the SD and 2-3 for the Jtag mode. SD cards class 10 are recommended.30www.HiTechGlobal.com
U72 ECS-TXO-5032-122.8 12.288 MHz Clock Jitter Cleaner Reference (ADC/DAC) U1 ABLNO-V-122.88MHZ 122.88 MHz Clock Jitter Cleaner Reference (ADC/DAC) ZQ1 FA-238 25.0000MB 25 MHz USB3 HUB Controller ZQ2 FA-238 25.0000MB 25 MHz Etherne
Linear Programming Duality: Motivation Consider the below linear program z max x1 2x2 x3 s.t. 3x1 2x2 x3 12 x1 x3 3 x1, x2, x3 0 We give upper bounds for the objective function Since variables are nonnegative, the first constraint is immediately an upper bound z x1 2x2 x3 3x1 2x2 x3 12 Since component-wise x1 3x1, 2x2 2x2, and .
Cisco Catalyst 9162 Series Cisco Catalyst 9162I Access Point, WiCW9162I-x -Fi 6E, Internal Antennas, 2x2 2x2 2x2 MIMO, 2.5G mGig with Reg-X. CW9162I-MR Cisco Catalyst 9162I Access Point, Wi-Fi 6E, Internal Antennas, 2x2 2x2 2x2 MIMO, 2.5G mGig with Meraki. Note: Customers ordering 9160 Access Points shipping with Meraki Management Mode (-MR)
*2x1 chroma subsampling (For every 2x2 block of pixels, the Cb and Cr values are taken from one 2x1 column) *2x2 chroma subsampling (For every 2x2 block of pixels, the Cb and Cr values are only taken from one pixel). 2x2 is the most common for JPEG, and it is the one that seems to be used by MS Paint. 2.2 The Discrete Cosine Transform on 8x8 blocks
6 Math 3 VM Part 7 Absolute Value & Inequalities August 7, 2017 Example: 2x2 3 – x Solution: To solve 2x2 G 3 x, we first get 0 on one side of the inequality which yields 2x2 x 3 0. Then find the zeros of f(x) 2x2 x 3
configurable wrapper to allow the RF-DAC and RF-ADC blocks to be used in IP integrator designs. IMPORTANT! In this guide reference is made to the Dual and Quad RF-ADC and RF-DAC tiles; for the actual sampling rate specifications, see the Zynq UltraScale RFSoC Data Sheet: DC and AC Switching Characteristics (DS926).
configurable wrapper to allow the RF-DAC and RF-ADC blocks to be used in IP integrator designs. IMPORTANT! In this guide reference is made to the Dual and Quad RF-ADC and RF-DAC tiles; for the actual sampling rate specifications, see the Zynq UltraScale RFSoC Data Sheet: DC and AC Switching Characteristics (DS926).
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The group work is a valuable part of systematic training and alerts people to other training opportunities. Most have been on training courses provided by a range of early years support groups and charities and to workshops run by individual settings. Some have gained qualifications, such as an NVQ level 3 or a degree in child development and/or in teaching. Previous meetings have focused on .
