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UltraScale ArchitectureConfigurable Logic BlockUser GuideUG574 (v1.5) February 28, 2017

Revision HistoryThe following table shows the revision history for this document.DateVersionRevision02/28/20171.5Changed “Dual-port 32 x (1 to 4)-bit RAM” to “Dual-port 32 x (1 to 8)-bit RAM” and“Quad-port 32 x (1 to 8)-bit RAM” to “Quad-port 32 x (1 to 4)-bit RAM” underDistributed RAM (SLICEM Only). Clarified second paragraph following Figure 5-5.Deleted the word “interposer” preceding “boundaries” and “connections” underSecond Generation 3D IC Interconnect.11/24/20151.4Added UltraScale device information.10/29/20151.3Deleted last bullet under Differences from Previous Generations. Updated Figure 2-1.Updated last paragraph under Multiplexers and first paragraph under 32:1Multiplexer. Updated second paragraph under Distributed RAM (SLICEM Only).02/20/20151.2Changed title of Chapter 1, from “Introduction” to “Overview”. Added last twosentences to CLB Slice Resources. Clarified first paragraph under CLB Resources andchanged “Quad-port 32 x (1 to 4)-bit RAM” to “Quad-port 32 x (1 to 8)-bit RAM andDual-port 128 x 1-bit RAM to Dual-port 128 x 2-bit RAM under Distributed RAM(SLICEM Only) in Chapter 2, CLB Functionality. Made minor editorial changes inChapter 3, Design Entry. Changed title of “Laguna Flip-Flops” to “Second Generation3D IC Interconnect” and clarified use of the term “Laguna” with respect to theinterconnect flip-flops in Chapter 5, Advanced Topics. Deleted Table 5-2, “TotalSynchronizers Available per Device”. Made minor editorial changes in 3D IC Devicesusing Stacked Silicon Interconnect (SSI) Technology and Added Figure 5-5.09/08/20141.1Deleted “Differences in Devices Based on SSI Technology sub-section fromDifferences from Previous Generations and added last paragraph. Combined Table 1-1and Table 1-2. Updated and clarified Initialization. Clarified sixth paragraph underDistributed RAM (SLICEM Only). Added reference to UG949 under Design Checklist.Added Asynchronous Clock Domain Crossing to Chapter 5, Advanced Topics. Updatedreferences in 3D IC Devices using Stacked Silicon Interconnect (SSI) Technology andadded Second Generation 3D IC Interconnect sub-section. Updated references inAppendix A, Additional Resources and Legal Notices.12/10/20131.0Initial Xilinx release.UltraScale Architecture CLB User GuideUG574 (v1.5) February 28, 2017www.xilinx.comSend Feedback2

Table of ContentsRevision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Chapter 1: OverviewIntroduction to UltraScale Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5CLB Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Differences from Previous Generations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Device Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Recommended Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Pin-out Planning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Chapter 2: CLB FunctionalityOverview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .CLB Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Look-Up Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Storage Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Carry Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Distributed RAM (SLICEM Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Shift Registers (SLICEM Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1515161720232531Chapter 3: Design EntryIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Design Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Using the CLB Slice Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35353636Chapter 4: ApplicationsIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Distributed RAM Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Shift Register Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Carry Logic Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .UltraScale Architecture CLB User GuideUG574 (v1.5) February 28, 2017www.xilinx.comSend Feedback464647483

Chapter 5: Advanced TopicsAsynchronous Clock Domain Crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Using the Latch Function as Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Interconnect Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3D IC Devices using Stacked Silicon Interconnect (SSI) Technology . . . . . . . . . . . . . . . . . . . . . . . . .50535455Appendix A: Additional Resources and Legal NoticesXilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .UltraScale Architecture CLB User GuideUG574 (v1.5) February 28, 2017www.xilinx.comSend Feedback585858594

Chapter 1OverviewIntroduction to UltraScale ArchitectureThe Xilinx UltraScale architecture is a revolutionary approach to creating programmabledevices capable of addressing the massive I/O and memory bandwidth requirements ofnext-generation applications while efficiently routing and processing the data brought onchip. UltraScale architecture-based devices address a vast spectrum of high-bandwidth,high-utilization system requirements through industry-leading technical innovations. Thedevices share many building blocks to provide optimized scalability across the productrange, as well as numerous new power reduction features for low total power consumption.Kintex UltraScale FPGAs provide high performance with a focus on optimizedperformance per watt for applications including wireless, wired, and signal or imageprocessing. High digital signal processing and block RAM-to-logic ratios, and nextgeneration transceivers are combined with low-cost packaging to enable an optimum blendof capability for these applications.Kintex UltraScale FPGAs deliver increased performance over the Kintex UltraScale familywith on-chip UltraRAM memory to reduce BOM cost, providing the ideal mix ofhigh-performance peripherals and cost-effective system implementation. In addition,Kintex UltraScale FPGAs have numerous power options that deliver the optimal balancebetween the required system performance and the smallest power envelope.Virtex UltraScale FPGAs provide the highest system capacity, bandwidth, andperformance. Delivering unprecedented logic capacity, serial I/O bandwidth, and on-chipmemory, the Virtex UltraScale family pushes the performance envelope ever higher.Virtex UltraScale FPGAs have the highest transceiver bandwidth, highest DSP count, andhighest on-chip UltraRAM memory available for the ultimate in system performance. Inaddition, Virtex UltraScale FPGAs also provide numerous power options that deliver theoptimal balance between the required system performance and the smallest powerenvelope.Zynq UltraScale MPSoCs combine the ARM v8-based Cortex -A53 high-performanceenergy-efficient 64-bit application processor with the ARM Cortex-R5 real-time processorand the UltraScale architecture to create the industry's first All Programmable MPSoCs.With next-generation programmable engines, security, safety, reliability, and scalabilityfrom 32 to 64 bits, the Zynq UltraScale MPSoCs provide unprecedented power savings,UltraScale Architecture CLB User GuideUG574 (v1.5) February 28, 2017www.xilinx.comSend Feedback5

Chapter 1:Overviewprocessing, programmable acceleration, I/O, and memory bandwidth ideal for applicationsthat require heterogeneous processing.This user guide describes the UltraScale architecture clocking resources and is part of theUltraScale architecture documentation suite available at: www.xilinx.com/documentation.CLB OverviewThe Configurable Logic Block (CLB) is the main resource for implementing general-purposecombinatorial and sequential circuits. Synthesis tools automatically use the highly efficientlogic, arithmetic, and memory features of the UltraScale architecture. These features canalso be directly instantiated for greater control over the implementation. The CLB is madeup of the logic elements themselves, which are grouped together in a slice, along with theinterconnect routing resources to connect the logic elements. Utilization of slices, theirplacement in the device, and routing between them is best left to the automatic tools, butknowing the UltraScale architecture helps you create more optimal designs.This user guide provides the necessary CLB details for designers to produce code that usesall of the CLB capabilities. This overview section introduces the most commonly used CLBresources. Later chapters include further detail for optimizing a design to improve density,performance, or power.The UltraScale architecture CLBs provide advanced, high-performance, low-powerprogrammable logic with: Real 6-input look-up table (LUT) capability. Dual LUT5 (5-input LUT) option. Distributed memory and shift register logic (SRL) ability. Dedicated high-speed carry logic for arithmetic functions. Wide multiplexers for efficient utilization. Dedicated storage elements that can be configured as flip-flops or latches with flexiblecontrol signals.Each UltraScale architecture CLB contains one slice. Each slice provides eight 6-input LUTsand sixteen flip-flops. Slices easily connect to each other to create larger functions. Theslices and their CLBs are arranged in columns throughout the device, with the size andnumber of columns increasing with density.The UltraScale architecture LUTs can be configured as shown in Figure 1-1. A 6-input LUT with one output. Two 5-input LUTs with separate outputs but common addresses or logic inputs.UltraScale Architecture CLB User GuideUG574 (v1.5) February 28, 2017www.xilinx.comSend Feedback6

Chapter 1:OverviewX-Ref Target - Figure 1-1O665O66:15:1O5One Function of 6 InputsTwo Functions of 5 Inputsug574 c1 01 102912Figure 1-1:LUT ConfigurationsEach LUT output can connect to slice outputs, or optionally be registered in a flip-flop orlatch. The storage elements can also be driven by direct inputs to the slice (X and I), or bythe results of the internal carry logic or wide multiplexers. See Figure 1-2. The storageelements have a clock enable input, along with an initialization signal that can beprogrammed as either synchronous or asynchronous, and as set or reset.X-Ref Target - Figure 1-2OO66:1O5MUXNoteQ1XNoteQ2INoteNote: MUX inputs include carry and wide multiplexers (not shown)ug574 c1 02 102912Figure 1-2:A Simplified View of Slice I/O Connecting to a LUT and Storage ElementsDedicated carry logic improves the performance of arithmetic functions such as adders,counters, and multipliers. Carry logic consists of dedicated carry-lookahead gates,multiplexers, and routing that are independent of the general-purpose logic resourceswhile providing both higher density and increased performance. Carry logic is ofteninferred for smaller arithmetic functions. Larger, more complex arithmetic functions can usethe dedicated DSP block. See the UltraScale Architecture DSP48E2 Slice User Guide (UG579)[Ref 1].Each 6-input LUT can implement a 4:1 multiplexer (MUX). Dedicated multiplexers in theslices combine the LUTs together to create even wider functions without having to connectto another slice. All the LUTs in a slice can be combined together as a 32:1 MUX in one levelof logic.UltraScale Architecture CLB User GuideUG574 (v1.5) February 28, 2017www.xilinx.comSend Feedback7

Chapter 1:OverviewEight 6-input LUTs and their sixteen storage elements, as well as the multiplexers andarithmetic carry logic, form a slice, as shown in Figure 1-3. Each 6-input LUT and set ofassociated flip-flops and other logic are labeled A to H from bottom to top.X-Ref Target - Figure 1-3HGFEDCBAug574 c1 03 102912Figure 1-3:UltraScale Architecture CLB User GuideUG574 (v1.5) February 28, 2017LUTs and Storage Elements in One Slicewww.xilinx.comSend Feedback8

Chapter 1:OverviewThere are two types of slices in the UltraScale architecture, with different ratios of the twotypes by device. The SLICEL (logic) has all the LUT and storage element resources shown,along with the carry logic and wide multiplexers. A SLICEM (memory) can also use the LUTsas distributed 64-bit RAM, by adding a separate write address (WA), write enable (WE), andclock signal. The LUT can be configured as either a 64 x 1 or 32 x 2 memory. The directinputs X and I serve as the data inputs. See Figure 1-4.X-Ref Target - Figure 1-4XIO6IWA6:WA1O6WA5:WA1O56:15:1WE64 x 1 Distributed RAMWE32 x 2 Distributed RAMug574 c1 04 102912Figure 1-4:Distributed RAM Using Look-Up TablesThe distributed RAM can be combined across the eight LUTs in the SLICEM to creatememories of up to 512 bits. The SLICEM shares a common write address and write clockacross all 8 LUTs. The SLICEM write enable is also shared but can be used in combinationwith three other slice inputs for more flexibility. Multiple SLICEM can be combined togetherto create memories larger than 512 bits. Dedicated block RAM is also available for largermemories. See the UltraScale Architecture Memory Resources User Guide (UG573) [Ref 2].Each LUT in a SLICEM can also be used as a 32-bit shift register (SRL32). Combining the LUTsallows up to a 256-bit shift register in one SLICEM, compared to the 16 dedicated flip-flopsper slice.More details on each of these features are provided in Chapter 2, CLB Functionality.UltraScale Architecture CLB User GuideUG574 (v1.5) February 28, 2017www.xilinx.comSend Feedback9

Chapter 1:OverviewDifferences from Previous GenerationsThe UltraScale architecture CLB is very similar to that of the 7 series devices, with the samebasic building blocks of 6-input LUTs, flexible storage elements, and abundant routing.Design techniques used for previous generations will continue to work effectively with theUltraScale architecture-based devices. The differences are primarily to provide moreflexibility, which in turn allows for greater automatic optimization of designs. The two independent slices of the 7 series CLB are combined into one cohesiveUltraScale architecture slice for greater logic and routing efficiency. Top and bottomhalves of UltraScale architecture slices are each similar to a 7 series slice. With one sliceper CLB in the UltraScale architecture, the total resources per CLB are similar. More control sets available for flexibility and clock gating: Four clock enables per CLB slice. Optional invert on set/reset signal.More flexibility for distributed RAM control: Dedicated clock for distributed RAM. Write enable independent of flip-flop clock enable. Write enable input can be combined with three direct slice inputs to create up toeight independent write enables within the slice.All flip-flop outputs always available for enhanced packing and routing, with fouroutputs per LUT: Direct LUT output. Multiplexed combinatorial output. Two equivalent flip-flop outputs. Flip-flops can all be edge-triggered D-type flops or level-sensitive latches. Selectableby top or bottom half. Carry logic expanded from 4 to 8 bits per CLB for faster arithmetic. One carry chain perCLB.The common features in the CLB structure simplify design migration from the 7 series to theUltraScale architecture-based devices. For greater control signal flexibility and to benefitfrom the lack of slice-specific restrictions, remove mapping and placement constraintsbefore implementing designs originally targeted to earlier devices.The CLBs are arranged in columns. This columnar architecture enables different devices tohave a mix of varying features that are optimized for different application domains.Through this innovation, Xilinx offers a larger selection of devices and enables designers toUltraScale Architecture CLB User GuideUG574 (v1.5) February 28, 2017www.xilinx.comSend Feedback10

Chapter 1:Overviewchoose a device with the correct features and capabilities needed for a specific designimplementation.The columnar architecture eliminates traditional design barriers by: Eliminating geometric layout constraints such as dependencies between I/O count andlogic array size. Enhancing on-chip power and ground distribution by allowing power and GND to beplaced anywhere on the device. Allowing disparate silicon-based dedicated IP blocks to be scaled independent of eachother and surrounding resources.The architecture is subdivided into segmented clock regions (CRs). CRs differ from previousfamilies because they are arranged in tiles and do not span half the width of a device. A CRcontains CLBs, DSP slices, block RAMs, interconnect, and associated clocking. The height ofa CR is 60 CLBs, 24 DSP slices, and 12 block RAMs with a horizontal clock spine (HCS) at itscenter. The HCS contains the horizontal routing and distribution resources, leaf clockbuffers, clock network interconnections, and the root of the clock network. Clock buffersdrive directly into the HCS. There are 52 I/Os per bank and four gigabit transceivers that arepitch matched to the CRs. A core column contains configuration, System Monitor, andPCIe blocks to complete a basic device.Device ResourcesThe CLB resources are scalable across all UltraScale architecture-based devices, and providea common architecture that improves tool efficiency, IP implementation, and designmigration. Migration between UltraScale architecture-based devices requires no CLB-baseddesign changes.Device capacity is often measured in terms of logic cells, which are the logical equivalent ofa classic four-input LUT and a flip-flop. The U

UltraScale Architecture CLB User Guide www.xilinx.com 5 UG574 (v1.5) February 28, 2017 Chapter 1 Overview Introduction to UltraScale Architecture The Xilinx UltraScale architecture is a revo lutionary approach to creating programmable devices capable of addressing the massive I/O and memory bandwidth requirements of

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