The University of Texas at ArlingtonSequential Logic - IntroCSE 2340/2140 – Introduction to Digital LogicDr. Gergely ZárubaThe Sequential Circuit Modelx1Combinational logic with n inputs andm switching functions:z1Combinationallogicxnzm(a)x1Sequential logic with n inputs, moutputs, r Boolean variables encodingfuture and presents states (each).Th a totalThust t l off m r switchingit hifunctions:z1xnzmCombinationallogicy1 yrYr Y1Memory(b)1
Describing Digital State MachinesInputPresent statexNext stateYx/zInput/outputPresent stateyY/zyNextstate/outputState diagram(a)State table(b)State Machine ExampleConsider a sequential circuit having one input variable x, two state variables y1and y2 (four states), and one output variable z. Inputs:States:x 0, x 1[y1,y2]  A[y1,y2]  COutputs: z 0, z 1[y1,y2]  B[y1,y2]  D0/1APresent StatePresentstateABCD1/1CInput /0BD1/10/1x/zStatediagram(b)2
SR Latches A latch can be seen as rudimentary memory. If it is set itwill remain set (produce an output of 1) and if it is resetthen it will remain reset. Conceptually, there are set-only and reset-only latchesbut practically the SR latch makes sense only.SR0dd0100101(b)5SR LatchesState diagramExcitation tableSR0dd01001K-map of latch outputt Q*01SRQ(b)S00011110000-1Q 110-1R(c)Q* S 1110011001101010101010011 No changeResetSetNot allowed(a)63
SR LatchesState diagramSR0dd01001K-map of latch outputt Q*01(b)SRQS00011110000-1Q 110-1R(c)Characteristic equationQ* S RQ7SR-Latch Timing DiagramsIdeal (zerogate delay)Actual timingwith non-zerodelays84
SR Latch Propagation DelaysStPLH(S to Q)RtPHL(R to Q)tPLH(N 2)QtPHL(N 2)QtPLH(N 1)tPHL(N 1)9Gated SR-Latch Would be nice to restrict when latch can change state. This way wecould determine when output becomes stable.SSSQQRQCCRRQR(b)With NAND SR latch(a)With NOR SR latchSSC*SQQCCQRSRQC*R(c)NAND logic diagramlogic symbol105
Gated SR-Latch CharacteristicsEnable Excitation Present Nextstatepinputs inputsstateCSRQQ*0011111111 0000111100110011010101010101010011 Q* SC RQ CQCharacteristic equationHoldNo changeCSR0dd, 10dReset0dd,, 1d0110Set01101Not allowedState(b) diagram11ExcitationTable(a)D-Latch Delay latch can be used as rudimentary memory, a special SR-latchwhere S D and R !DDSQQRSR latch(b)NANDimplementationLogic SymbolDSQState diagramLogic SymbolExccitation TableCCQRSR latchNOR(c) implementation126
D-Latch TimingDCQEnabledEnabledEnabledHoldHoldD may hold)Ctsuthtsu(setup)QtwMinimum enablepulse widthUnknownstate13Synchronous sequential circuitsFLIP-FLOPS147
Flip-Flops The latch circuits presented thus far are not appropriatefor use in synchronous sequential logic circuits. Thepossibility of two cascaded combinational circuits feedingeach other, generating oscillations and unstabletransient behavior can be controlled by using a specialtiming control signal called a clock. A clock signal can then be used to restrict the times atwhich the states of the memory elements may changethus preventing the unstable behavior just described.15Master-Slave SR Flip-Flops Need to restrict free changes (to clock k)Logic diagramPulse-triggered device logic symbolCMasterSlavegatedholdholdgatedgat edholdholdgatedgatedholdholdgatedgatedholdholdgat edSRQMQ16Flip-flop output canchange8
Master-Slave SR Flip-FlopTiming ConstraintsS and R maynot changeRStsu(setup)Cth(hold)twtwC low pulse width C high pulse width(master enabled)(slave enabled)17Master-Slave SR Flip-FlopCharacteristicsSRQCQ*0000010 No change10011010 Reset01100011 Set1111101 Not allowed Excitation table(a)0d0dSR100101State Diagram(b)Q* S RQCharacteristic function189
Master-Slave D Flip-Flops Synchronous memory can be built fromttwoD-latches.Dl t hMasterDSlaveDQCQQMDQQCQQDQCQC(clock)Logic symbol(b)Logic diagram(a)19Master-Slave D MDStore 01 Store 1SM1 0SMSMSMCDQMQ QS2010
Master-Slave JK Flip-Flops The JK is almost like an SR. However the J K 1 inputcreates an output toggle.JKQ0000111100110011010101010dCQ* JQ KQQ*01001110HoldResetSetTToggleld0JR1d0121d17476 Dual Pulse-Triggered JK LK2K(6)(10)(12)2Q(8)2CLR22(b)11
Edge Triggered Flip-Flops All the pulse-triggered flip-flops discussed previously,require both a rising and falling edge on the clock forproper operation. Another approach is to design the flip-flop circuitry sothat it is sensitive to its excitation inputs only duringrising or falling transitions of the clock. A circuit with this design is called positive edge triggeredif it responds to a 0 to 1 clock transition,transition or negativeedge triggered if it responds to a 1 to 0 clock transition. The edge-sensitive feature eliminates unstabletransients by drastically reducing the period during whichthe input excitation signals are applied to the internal23latches.7474 Dual Positive-Edge-Triggered D Flip-FlopInputsOutputsPRECLRDCLKQQModeLHLHHHHLLHHH HL LHLHHLQ0LHHLHQ0SetClearNot allowedClocked operationClocked operationHold2412
Edge-Triggered Flip-Flop TimingD should bestablethDtsuthtsuCQtPLHtPHL25T Flip-FlopFunctional equivalentLogic symbol A common building block used in sequential logic circuitsthat counts pulses. It has only one input T. It toggles itsstate upon each negative-going transition. Q* !Q2613
Clocked T Flip-FlopC Q*0 Hold11 Toggle0Q* TQ TQFunctional equivalentQ0101Logic symbolT001127Summary of Latch and Flip-FlopCharacteristicsDeviceCharacteristic EquationSR latchGated SR latchQ* S RQD latchQ* DC CQQ* SC QR CQSR flip-flopQ* S RQD flip-flopQ* DJK flip-flopflip flopQ* KQ JQQT flip-flop (edge-triggered)Q* QT flip-flop (clocked)Q* TQ TQ14
Timing Circuits Latches/Flip Flops can be seen as bistabilemultivibrators. (especially T) Another class of frequently used devices that are closelyrelated to flip-flops are one-shots and timer modules. One-shots are monostabile multivibrators, (one stablestate). They are temporarily driven into a transient stateand remain in this transient state for an amount of timespecified by the timing constant of an RC network at thedevice’s package pins. They can be retriggerable.The 555 Timer Module A memory device that is used in a wide variety of applications sinceit can be configured for use as a one-shot or as an astable, oroscillating multivibrator.ResetVCCControlSE DischargeGround15
Astable 555 Operation Astable operation is achieved by making the 555 self-triggeringthrough an RC circuit.f 1.44/[(RA 2RB)C](TH 0.693(RA RB)C TL uare waveOutTHRESTRIGCGND1SE 555Monostable 555 Operation Device should automatically return tooriginali i l value.ltW 1.1R1 1RACVCC0.01 ESTRIGSE 555GND13.3-ms pulse ifRA 3 kOhm and C 1 mF16
RAPID PROTOTYPING OFSEQUENTIAL CIRCUITS USINGPROM/EPROM/FLASH33Rapid Prototyping of SequentialCircuits Recall: the implementation of asequential logic circuit requiresthe design of the combinationallogic and memory blocks of thesequential circuit However, a quick implementation of any sequentialcircuit can be done by using flip-flops to realize thememory block in conjunction with programmable readonly memory (PROM) devices to realize thecombinational logic block.17
What is a PROM? Programmable read only memory. Memory,Mthatth t hash an a-bitbit addressddiinput,t parallelll ldata output of n-bits and at each address thedata can be changed at least once. Thus it stores 2a*n bits. It will output the n-bitsstored that were addressed at the a-bit input. UsuallyUll realizedli d bby a fifixedd AND anddprogrammable OR array, where programmingmeans to burn small fuses. It can be seen as a programmable combinationalcircuit with a inputs and n outputs (n functions). 35Designing Sequential Circuitswith PROMs If we have a state diagram or a truthntable, we can easily design a PROMbased synchronous sequential circuit.rmr We need to assign a binary code tomeach of the s states (thus, r log2s ). If we have n inputs, then we need aPROM with r n address bits (2r n memory locations) If we havehm outputs, thenh we needd theh PROM to storer m bits at every memory location. The power of this type of design is in the programmabilityof the PROM devices. If we want to change the statebehavior, then one or both of the PROMs are simplyerased and reprogrammed.18
Example One input, one output, 4 1B1/00/1C0/01/11/0D0/0xy2 10101100Y2Y1DQCDzCQClock19
The University of Texas at Arlington Sequential Logic - Intro CSE 2340/2140 – Introduction to Digital Logic Dr. Gergely Záruba The Sequential Circuit Model x 1 Combinational z1 x n zm (a) y y Y Y Combinational logic logic x1 z1 x n z m Combinational logic with n inputs and m switching functions: Sequential logic with n inputs, m outputs, r .
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Le genou de Lucy. Odile Jacob. 1999. Coppens Y. Pré-textes. L’homme préhistorique en morceaux. Eds Odile Jacob. 2011. Costentin J., Delaveau P. Café, thé, chocolat, les bons effets sur le cerveau et pour le corps. Editions Odile Jacob. 2010. 3 Crawford M., Marsh D. The driving force : food in human evolution and the future.