CS 6534: Tech Trends / Intro

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CS 6534: Tech Trends / IntroCharles Reiss24 August 20161

Moore’s LawMicroprocessor Transistor Counts 1971-2011 & Moore's Law16-Core SPARC T3Six-Core Core i7Six-Core Xeon 74002,600,000,000Dual-Core Itanium 2AMD K10POWER6Itanium 2 with 9MB cacheAMD K101,000,000,0008-core POWER7Quad-core z196Quad-Core Itanium Tukwila8-Core Xeon Nehalem-EXSix-Core Opteron 2400Core i7 (Quad)Core 2 DuoCellItanium 2100,000,00010-Core Xeon Westmere-EXAMD K8Pentium 4BartonAtomTransistor countAMD K7AMD K6-IIIAMD K6Pentium IIIPentium II10,000,000AMD 06809Z808080MOS 650280082,3004004801868088808680856800RCA 180219711980199020002011Date of introductionWikimedia Commons / Wgsimon2

Good Ol’ Days: Frequency ScalingFigure 1.11 Growth in clock rate of microprocessors in Figure 1.1. Between 1978 and 1986, the clock rate improved less than 15% peryear while performance improved by 25% per year. During the “renaissance period” of 52% performance improvement per year between1986 and 2003, clock rates shot up almost 40% per year. Since then, the clock rate has been nearly flat, growing at less than 1% per year,while single processor performance improved at less than 22% per year.H&P3

The Power WallPower Switching Power Leakage PowerSwitching Power Capacitance Voltage2 Frequency4

Intel x86 # of Cores Per PackageIncreasing Parallelism: 6Date5

vector register size (bits)Increasing Parallelism: Vector width500x86ARM40030020010001995 1997 2000 2003 2005 2008 2011 2014 2016Date6

Increasing Parallelism: ILPx86 Intel 32-bit adds per cycle432101978 1983 1988 1994 1999 2005 2010 20167

Limits: ParallelismAmdahl’s LawSpeedup (1 serial)20155% serial0% serial1010% serial525% serial50% serial1020304050Degree of Parallelism (1 serial)608

Limits: Communication[Balfour et al, “Operand Registers and Explicit Operand Forwarding”, 2009.][Malladi et al, “Towards Energy-Proportional Datacenter Memory with Mobile DRAM”, 2012.]DDR3 DRAM (32-bit read/write)full utilization2 300 000 fJ4300 low utilization7 700 000 fJ15000 9

Increasing Efficiency: SpecializationTask/workload-specific coprocessors or instructionsMaybe reconfigurable?Heterogeneous systemsdifferent parts for different types of computation10

Interlude: LogisticsPaper reviews — approx 2/classHomeworks — programming assignmentsExam — end of semester11

Textbook?Primarily paper readingsClassic some newish papersReference: Hennessy and Patterson,Computer Architecture:A Quantitative Approach12

Paper ReviewsWhat was your most significant insight from thepaper?What evidence does the paper have to support thisinsight?What is the weakest part of the paper or how couldit be approved?What topic from the paper would you like to seediscussed in class (if any)?13

Paper ReviewsWhat was your most significant insight from thepaper?Might not be what the authorsput in their abstract/conclusionWhat evidence does the paper have to support thisinsight?What is the weakest part of the paper or how couldit be approved?What topic from the paper would you like to seediscussed in class (if any)?13

Paper Discussionsand not paper lectures.Requires your cooperation.14

HomeworksIndividual programming writing assignmentsFirst — on memory hierarchy — available now.Second — to be announced — likely on superscalarThird — to be announced — likely GPUprogramming15

Homework 1Description on course website (linked off Collab)Memory system parameters by benchmarking16

Homework 1Description on course website (linked off Collab)Memory system parameters by benchmarkingExample: 32K cache means accessing 32Krepeatedly is faster than 128K repeatedly.16

Homework 1: DisclaimerThis is probably hardModern memory hierarchies are complicatedDocumentation is incompleteMainly looking for: measurement technique that‘should’ workIf it doesn’t, try to come up with good reasons why17

ExamThere will be in final, probably in-class.Cover material from papers, homeworks, discussionsin class18

Exceptions / etc.Need accommodations — please askDisability accommodations — Student DisabilityAccess Center19

Asking QuestionsPiazza (linked of Collab)Office Hours:Instructor Lecturer Charles Reiss TA Luowan WangLoationSoda 205TBATimesMonday 1PM–3PMTuesday 1PM–2PMFriday 10AM–noonEmail: creiss@virginia.edu20

Surveylinked off Collabanonymousplease do it21

Preview of coming topics22

Memory hierarchycaching — review(?) and advanced techniqueshomework 123

Pipeliningdifferent parts of multiple instructions at the sametimemore advanced topics: handling exceptionsImage: Wikimedia commons / Poil24

Increasing Parallelism: ILPx86 Intel 32-bit adds per cycle432101978 1983 1988 1994 1999 2005 2010 201625

Beyond pipelining: Multiple issuestarting multiple instructions at the same timeallows cycles per instruction 126

Beyond pipelining: Out-of-orderrun next instruction despite stall of prior oneslow cacheread-after-write hazard.speculation — guess outcome of branch/load/etc.fix later if wrong27

Intel x86 # of Cores Per PackageIncreasing Parallelism: 6Date28

Multiprocessor/multicoreconnecting processors togethershared memory — multiple threadssynchronization29

vector register size (bits)Increasing Parallelism: Vector width500x86ARM40030020010001995 1997 2000 2003 2005 2008 2011 2014 2016Date30

Vector/SIMD/GPUssingle instruction/multiple datastarted with early supercomputersbasis of GPU programming model31

Specializationusing custom chips (or circuits within chips)reconfigurable processors (e.g. FPGAs)32

Miscellaneous topicshardware securitywarehouse-scale computers. . . depends on timeSuggestions?33

Papers for Next ClassAlan Smith’s review of caching in 1982D. J. Bernstein’s timing attack and suggestions tocomputer architects in 2005Note: We’re not reading this to learn about AES34

8-core POWER7 10-Core Xeon Westmere-EX 16-Core SPARC T3 Six-Core Core i7 Six-Core Xeon 7400 Dual-Core Itanium 2 AMD K10 Microprocessor Transistor Counts 1971-2011 & Moore's Law Transistor count Wikime

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