3D-NAND Equipment Market: A Long-term Growth
Press ReleaseNovember 5th, 2020LYON, France3D-NAND equipment market: along-term growth1OUTLINES: 3D-NAND has become a mainstream technology because of its excellent scalability thatallows increased bit density and lower cost-per-bit via vertical stacking of memory cells.Advances in the field of 3D-NAND manufacturing are enabled by both equipment andmaterial developments.Market figures:3D-NAND market is expected to grow to US 81 billion in 2025 with a 11% CAGR2between 2019 and 2025.The 3D-NAND equipment market including etching, deposition and lithography, will growto US 17.5 billion by 2025, showing a 9% CAGR during the same period.Technology status:3D-NAND memory manufacturers will adopt different strategies to increase the numberof layers and the overall bit density per die.Competitive landscape:The equipment market is dominated by USA, followed by Japan and Netherland.Four companies, ASML, Applied Materials, Tokyo Electron and Lam Research – hold morethan 70% of the overall equipment market.In the 3D NAND business, Samsung is the clear technology leader with fierce competitionfrom WD-Kioxia, followed by SK hynix and Micron-Intel.Leading the NAND memory market in China, YMTC looms on the horizon and threatensto disrupt the status-quo.“The 3D-NAND manufacturing equipment market will keep growing, propelled by robustlong term NAND-bit demand and ever-increasing manufacturing complexity.” asserts SimoneBertolazzi, PhD, Technology & Market analyst with the Semiconductor &Software division at Yole Développement (Yole).1Extracted from: Equipment and Materials for 3D NAND Manufacturing 2020, Yole Développement, 2020 NAND Quarterly Market Monitor, Yole Développement, Q3 2020 YMTC’s 3D-NAND Flash Memory, System Plus Consulting, 20202CAGR : Compound Annual Growth Rate
Press ReleaseThe 3D-NAND equipment market spanning etching, deposition and lithography equipment isexpected to grow from U 11 billion in 2019 to US 17.5 billion by 2025. This industry will bedriven by the etching market segment, with a CAGR around 10%, and deposition, with aCAGR around 9%, between 2019 and 2025. Four companies are leading this market,announces the market research & strategy consulting company Yole Développement: AppliedMaterials, ASML, Tokyo Electron and Lam Research.For the 3D NAND business, market figures are significant: Yole’s analysts announce a 11%CAGR between 2019 and 2025 with a growth from US 44 to US 81 billion at the end of theperiod. “3D NAND does not require advanced lithography, but it is highly demanding in terms ofdeposition and etching, as sophisticated HAR3 dry etching tools are needed for processing deep andnarrow structures in dielectric stacks,” comments Simone Bertolazzi from Yole.In this context, Yole and System Plus Consulting, both part of Yole Group ofCompanies, investigate disruptive memory technologies and related equipment and materialsmarkets in depth. Their aim is to point out the latest innovations and underline the businessopportunities. Both partners announce today with three NAND dedicated analyses: NAND Quarterly Market Monitor, Q3 2020 update that is following the NANDindustry with key market figures and trends, quarter by quarter. This monitor alsoproposes a high added-value focus on the leading NAND players with a relevantanalysis of their market positioning and strategy. Equipment and Materials for 3D-NAND Manufacturing 2020 report proposes anextensive knowledge of the NAND business and related manufacturingequipment/processes. This report is the result of a tight collaboration between Yole’smemory and semiconductor manufacturing teams and System Plus Consulting3HAR: High Aspect Ratio2
Press Releasetechnology & costs analysts, who carried out a detailed analysis of the leading-edge 3DNAND devices by all suppliers. In addition, System Plus Consulting delivers a special focus on the rising memorycompany YMTC, that is leading the Chinese market today, with a dedicated report,YMTC’s 3D-NAND Flash Memory.With those three analyses, System Plus Consulting and Yole present a unique understandingof the NAND and 3D-NAND industry.What are the economic and technical challenges of the 3D-NAND industry? What are theCOVID-19’s impact on this business? Who are the top NAND manufacturers and equipmentsuppliers? What are the key drivers of these industries?Discover today the vision of the 3D-NAND industry from System Plus Consulting and Yole’sanalysts.In the NAND Quarterly Market Monitor, Q3 2020, analysts affirms that NAND’scompetitive landscape remains incredibly dynamic. Samsung is utilizing its massive newPyeongtaek site and expanding its facilities in Xi’an, China; Kioxia and its partner WesternDigital continue to expand their footprint in Japan; Micron and SK Hynix remain competitivedespite smaller manufacturing capacities; and Intel has emerged as a stand-alone supplier withcapacity in China. In addition, it is also important to notice SK Hynix acquisition of Intel’sNAND business that took place on October 20th. This acquisition has been deeply analyzedby Walt Coon, VP of NAND and Memory Research, part of the Semiconductor,Memory & Computing division at Yole, in the article: Yole Développement dissects IntelSK Hynix US 9 billion NAND deal. Discover it on i-Micronews.Meanwhile, a new entrant looms on the horizon: China’s YMTC, which threatens to disruptthe status-quo. Indeed, YMTC is the leading NAND memory maker in China.3
Press ReleaseAccording to Walt Coon, from Yole: “The company is currently shipping 64-layer NAND inlow volumes domestically, including SSDs, with 128-layer production under development (shipmentsexpected in 2021). YMTC’s 2020 ramp has been hampered by COVID-19, with delays in equipmentdeliveries/installations at its Wuhan manufacturing site”.In its YMTC’s 3D-NAND Flash Memory report, System Plus Consulting’s analysts deeplyanalyzes the technical choice made by YMTC. The Chinese memory company developed itsnew 3D-NAND XtackingTM architecture with two wafers for its 64-layer 3D-NAND memory,instead of a single wafer used in conventional 3D NAND memories.Belinda Dube, Technology & Cost Analyst at System Plus Consulting comments:“CMOS periphery and NAND array wafer are manufactured separately. Wafers are connected bycopper to copper hybrid bonding. And the bonding technique needs a high level of accuracy andalignment precision to perfectly join the metal layers from different wafers. YMTC’s Xtacking processallows the company to increase its die density”.YMTC’s memory enters the NAND flash market as a solution to cater for higher I/O4 speedbecause of the use of advanced CMOS that can be manufactured on a different wafer from theNAND array. Consequently, this memory provides the combination of high speed and largedensity characteristics.In the highly competitive 3D-NAND business, there is need for ad hoc tools capableof addressing complex challenges: Etching tools must drill deep channel holes from the top of the device to the bottomsubstrate. Deposition tools must produce high-quality defect-free thin films with nanometerthicknesses.4I/O : Input/Output4
Press Release Metrology/Inspection tools are also becoming essential to monitor the processes andmaintain high yields. Ideally, these challenging tasks need to be accomplished in thefastest possible time and lowest cost.“In this framework, the competition among equipment suppliers to deliver the best solutions is growingfierce,” comments Simone Bertolazzi. “Besides equipment technology development, a great dealof R&D effort has to be focused on finding new material solutions.”In this context, specific technical strategies are needed for next-generation 3D-NANDproducts. Three focus areas have been identified by Yole’s memory team: String-stacking: whereas all players have already adopted a double-stack approach,Samsung, the industry leader, is the only player to develop the 128-layer generationwith a single-string approach and thus enjoys higher margins on NAND than otherchipmakers. For the following generation, Samsung is expected to adopt doublestacking. Cell Architecture: all the manufacturers except Intel have adopted the CT5 solutionfor their 1xx 3D NAND technologies. Intel has recently announced the sale of its 3DNAND business to SK Hynix, and Yole expects they could shift from FG6 to CT as thedeal with SK Hynix moves forward. The transfer of the NAND business is expectedto be completed by 2025. Logic circuit position: besides Micron, with CUA7, SK Hynix, with 4D-NANDTM, andYMTC, with XtackingTM, all players need to implement specific solutions to minimizethe silicon-area consumption of the CMOS logic circuit. Nowadays, all major 3DNAND manufacturers are carrying out R&D activities to explore the use of wafer-towafer stacking approaches based on hybrid bonding. Samsung has not yet disclosed anapproach to minimize the CMOS logic circuit area and a has strong know-how inbonding technologies stemming from its CIS8 and HBM9 businesses. It could be apotential candidate for the adoption of hybrid bonding for 3D-NAND. SK hynix couldfollow Samsung.Both partners, System Plus Consulting and Yole underline the difficult technical challenges intheir latest technical & market analyses. According to the analysts, they should be addressedvia close collaborations between equipment suppliers and memory manufacturers Staytuned on i-Micronews to discover more and more relevant and dynamic analyses of bothcompanies and follow the memory industry.All year long, Yole Développement and System Plus Consulting publish numerous memory, equipmentand materials-related reports and monitors. In addition, experts realize various key presentations and5CT : Charge TrapFG : Floating GateCUA : Circuit-Under-Array8CIS: CMOS image sensor9HBM: High-Bandwidth Memory675
Press Releaseorganize key conferences. In this regard, do not miss the Flash Memory Summit – 2020 conferencein Santa Clara (California) From Tuesday 10, November to Thursday 12, November 2020.Make sure to be aware of the latest news coming from the memory industry and get an overview oftheir activities, including interviews with leading companies, articles, webcasts and more on iMicronews. Stay tuned!Press contactsSandrine Leroy, Director, Public Relations, leroy@yole.frMarion Barrier, Assistant, Public Relations, marion.barrier@yole.frLe Quartz, 75 Cours Emile Zola – 69100 Villeurbanne – Lyon – France – 33472830189www.yole.fr- www.i-micronews.com– LinkedIn – Twitter6
Press ReleaseAbout our analystSimone Bertolazzi, PhD is a Technology & Market analyst at Yole Développement (Yole) working with theSemiconductor & Software division. He is member of the Yole’s memory team and he contributes on a day-today basis to the analysis of nonvolatile memory technologies, their related materials and fabrication processes.Previously, Simone carried out experimental research in the field of nanoscience and nanotechnology, focusingon emerging semiconducting materials and their opto-electronic device applications. He (co-) authored severalpapers in high-impact scientific journals and was awarded the prestigious Marie Curie Intra-European Fellowship.Simone obtained a PhD in physics in 2015 from École Polytechnique Fédérale de Lausanne (Switzerland), wherehe developed novel flash memory cells based on heterostructures of two-dimensional materials and high-κdielectrics. Simone earned a double M. A. Sc. degree from Polytechnique de Montréal (Canada) and Politecnicodi Milano (Italy), graduating cum laude.Walt Coon joins Yole Développement’s memory team as VP of NAND and Memory Research, part of theSemiconductor & Software division. Based in the US, Walt is leading the day-to-day production of both marketupdates and Market Monitors, with a focus on the NAND market and semiconductor industries. In addition, heis deeply involved in the business development of these activities. Walt has significant experience within thememory & semiconductor industry. He spent 16 years at Micron Technology, managing the team responsible forcompetitor benchmarking, and industry supply, demand, and cost modeling. His team also supported bothcorporate strategy and Mergers & Acquisitions analysis. Previously, he spent time in Information Systems,developing engineering applications to support memory process and yield enhancement. Walt Coon earned aMaster of Business Administration from Boise State University (Idaho, United-States) and a Bachelor of Sciencein Computer Science from the University of Utah (United-States).Belinda Dube is working for System Plus Consulting as Analyst in Semiconductor Memories and IntegratedCircuits. She holds a Masters degree in Nano Science and Nanotechnologies from Ecole Central Lyon and INSALyon.Véronique Le Troadec has joined System Plus Consulting as a laboratory engineer. Coming from AtmelNantes, she has extensive knowledge in failure analysis of components and in deprocessing of integrated circuits.About the reportsEquipment and Materials for 3D NAND Manufacturing 2020The 3D-NAND manufacturing equipment market will keep growing, propelled by robust long-term NAND-bit demand andever-increasing manufacturing complexity – Performed by Yole DéveloppementCompanies cited:ACM Research, Adeka, Advantest, AGC, Air Liquide, Air Products, Amec, Applied Materials, ASM International,ASML, Cabot Microelectronics, Canon, Coventor, Cypress, Dow, Dupont, Entegris, Enthone, EugeneTechnology, EVG, Fujifilm, Fusion IO, GigaDevice, GlobalFoundries, Hansol Chemical, Heraeus, Hitachi Chemical,Hitachi High Technologies, Intel, JSR Corporation, Jusung Engineering, Kingston, Kioxia and more NAND Quarterly Market Monitor Q3 2020NAND market poised to emerge from downturn in 2020. – Performed by Yole Développement, 2020YMTC’s 3D-NAND Flash MemoryTechnology and cost analysis of YMTC’s 64-layer 3D NAND with hybrid bonding. – Performed by System PlusConsulting, 2020Related reports:ooooDRAM Quarterly Market MonitorStatus of the Memory Industry 2020 – Focus on KioxiaEmerging Non-Volatile Memory 20203D NAND Memory Comparison 20197
Press ReleaseoLeading-Edge 3D NAND Memory Comparison 2018About Yole DéveloppementFounded in 1998, Yole Développement (Yole) has grown to become a group of companies providing marketing,technology and strategy consulting, media and corporate finance services, reverse engineering and reverse costingservices and well as IP and patent analysis. With a strong focus on emerging applications using silicon and/ormicro manufacturing, the Yole group of companies has expanded to include more than 80 collaboratorsworldwide MoreAbout System Plus ConsultingSystem Plus Consulting specializes in the cost analysis of electronics, from semiconductor devices to electronicsystems. Created more than 20 years ago, System Plus Consulting has developed a complete range of services,costing tools and reports to deliver in-depth production cost studies and estimate the objective selling price ofa product MoreFor more information and images, please visit our website i-Micronews###8
material developments. . 8 CIS: CMOS image sensor . His team also supported both corporate strategy and Mergers & Acquisitions analysis. Previously, he spent time in Information Systems, developing engineering applications to support memory process and yield enhancement. Walt Coon earned a
Context: NAND and NAND driver I Provide an abstraction layer for raw NAND devices I Take care of registering NAND chips to the MTD layer I Expose an interface for NAND controllers to register their NAND chips: struct nand_chip I Implement the glue between NAND and MTD logics I Provide a lot of interfaces for other NAND related stu
An XOR built from four NAND gates.MODEL P PMOS.MODEL N NMOS.SUBCKT NAND A B Y Vdd Vss M1 Y A Vdd Vdd P M2 Y B Vdd Vdd P M3 Y A X Vss N M4 X B Vss Vss N.ENDS X1 A B I1 Vdd 0 NAND X2 A I1 I2 Vdd 0 NAND X3 B I1 I3 Vdd 0 NAND X4 I2 I3 Y Vdd 0 NAND
Universal Gate -NAND I will demonstrate The basic function of the NAND gate. How a NAND gate can be used to replace an AND gate, an OR gate, or an INVERTER gate. How a logic circuit implemented with AOI logic gates can be re-implemented using only NAND gates. That using a single gate type, in this case NAND, will reduce the number of integrated circuits (IC) required to implement a
7 -21 Two-Level NAND-NAND Circuits Procedure for designing a minimum two-level NAND-NAND network: 1. Find a minimum SOP expression
NAND universal gates. Fig.3 Half adder circuit design using CMOS NAND gates on cadence virtuoso [1]. NAND gates were used to create a half adder. To design, any type of digital circuit used a universal gate. Here NAND gate used to design for half adder circuit because NAND gate is a universal gate. It is always simple and
The Micron NAND Flash memory with on-die ECC is specifically designed to work with . Enabling On-Die ECC for OMAP3 on Linux/Android OS Introduction. TN-29-75: Enabling On-Die ECC NAND with JFFS2 MTD and NAND Driver Configuration PDF: 09005aef855bbbce tn-29-75_enabl
years to load the BIOS from the slower ROM into the higher-speed RAM. There is a limit to the number of times NAND Flash blocks can reliably be programmed and erased. Nominally, each NAND block will survive 100,000 PROGRAM/ERASE cycles. A technique known as wear leveling
In order to recover data correctly one must find the correct scheme which was applied to NAND memory. The main reason NAND became such a popular data storage medium is the price of memory itself. When memory controllers got cheap and powerful enough flash NAND memory became one of the fastest growing technologies within the data storage industry.
