Cree’s SiC Power MOSFET Technology: Present Status And .

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Distribution authorized to U.S. GovernmentAgencies for administrative or operational use.Sponsored in part under CooperativeAgreements W911NR-10-2-0038 and W911NF12-2-0064 and Subcontract # 0145-SC-205790285. Includes Cree confidential information.Cree’s SiC Power MOSFET Technology:Present Status and Future PerspectiveLin Cheng and John W. PalmourCree, Inc.August 14, 20149th Annual SiC MOS Workshop, UMD, USA, Aug 14-15, 2014

Outline The last frontier for SiC Power MOSFETs Breakthrough in SiC MOS Stability & Reliability Next-Generation SiC Power MOSFETs Future PerspectiveL. Cheng and J. PalmourCopyright 2014, Cree, Inc.9th Annual SiC MOS Workshop, UMD, USA, August 14-15, 20142

The Last Frontier for SiC - CostPerformance Reliability SiC solution is 60%smaller at 20% lowercost than Si solution.Cost: by optimal chip designSiCSolution by improved Fab yield by robust reliabilityTransformerat 20 kHzL. Cheng and J. PalmourCopyright 2014, Cree, Inc.9th Annual SiC MOS Workshop, UMD, USA, August 14-15, 2014Transformerat 100 kHz3

Long-term ReliabilityTested tofailure atvery highVGS!Extrapolated MTTF of 3 x 107 hours at VDS 800 VTime (Hours)Time (Hours)Extrapolated MTTF of 107 hours at VGS 20VTested to failure atvery high voltagesVg Stress (V)TDDB of Gate Oxide on 1200 V/80 m Gen 2 MOSFETs at 150 CVd Stress (V)Accelerated HTRB Testing at 150 CL. Cheng and J. PalmourCopyright 2014, Cree, Inc.9th Annual SiC MOS Workshop, UMD, USA, August 14-15, 20144

Qualification Data for NBTS at 150 C: 3 Lots x 75 PartsHTGB at 150 C VGS -10 V Lot 1HTGB at 150 C VGS -10 V Lot 3In-Situ Monitored Data5.04.54.0 C2M (1200 V/80 m ) SiC MOSFETs ratedfor Max. VGS of -10 V. Full automotive qualification running todemonstrate 1,000 hours of VTH stabilityat 150 C3.53.0VthHTGB at 150 C VGS -10 V Lot 22.52.01.51.00.50.002004006008001000 New process started shipping intodistribution in April 2014HoursL. Cheng and J. PalmourCopyright 2014, Cree, Inc.9th Annual SiC MOS Workshop, UMD, USA, August 14-15, 20145

Qualification Data for PBTS at 150 C: 3 Lots x 75 PartsHTGB at 150 C VGS 25 V Lot 1HTGB at 150 C VGS 25 V Lot 2In-Situ Monitored Data5.04.54.54.04.03.53.53.03.02.5VthVthIn-Situ Monitored 1000Hours0.002004006008001000HoursHTGB at 150 C VGS 25 V Lot 3 C2M (1200 V/80 m ) SiC MOSFETs ratedfor Max. VGS of 25 V. Full automotive qualification running todemonstrate 1,000 hours of VTH stabilityat 150 C New process started shipping intodistribution in April 2014L. Cheng and J. PalmourCopyright 2014, Cree, Inc.9th Annual SiC MOS Workshop, UMD, USA, August 14-15, 20146

C2M VTH Stability Under BTS Beyond Datasheet SpecsPositive Bias (PBTS) Accelerated at 175 CNegative Bias (NBTS) Accelerated at -15 VVGS -15VT 150 CVGS 20VT 175 C Extremely stable for 1,000 hours under BTS at elevated temp.o Accelerated beyond data sheet to see any measurable changeo Average shift under positive bias: DVTH 0.06 Vo Average shift under negative bias: DVTH 0.01 VL. Cheng and J. PalmourCopyright 2014, Cree, Inc.9th Annual SiC MOS Workshop, UMD, USA, August 14-15, 20147

C2M Body Diode Stress @ 110% Rated IDS(DC), 150 CShift in MOSFET VDSONShift in MOSFET VTH3.5Shift in MOSFET Rev. IDSS50231.6V D S O N (V )V T H (V )1.42.52Body-diode stressing condition:IBDF 22 A (DC), V G -5 V, TJ 150 C.VTH measured at I D 1 mA and V D 10 V.1.51.210.6Body-diode stressingcondition:IBDF 22 A (DC), VG -5 V, TJ 150 C.0.4VDSON measured at I D 20 A and V G 20 V.0.8R e ve rs e I D S S ( A )1.8Body-diode stressing condition:IBDF 22 A (DC), V G -5 V, TJ 150 C.40Reverse I DSS measured at V Ds 1250 V, V G 0V.3020100.21000200400600800Time (Hour)1000020040060080010000Time (Hour)2004006008001000Time (Hour) Negligible shifts in MOSFET VTH, VDSON, IR after 1,000 hrsbody diode stress at IDS 22 A (DC), VGS -5 V, 150 C:oooo20 x C2M0080120D (1200 V/80 m ) SiC MOSFEFTsMax. VTH of MOSFET 0.02 V, average VTH 0.002 V.Max. VDSON of MOSFET 0.09 V, average VDSON 0.01 V.Max. IDSS of MOSFET 5 A, average IDSS 2.8 A.L. Cheng and J. PalmourCopyright 2014, Cree, Inc.9th Annual SiC MOS Workshop, UMD, USA, August 14-15, 20148

Avalanche Ruggedness of C2M SiC MOSFETsUnclamped Inductive Switching (UIS) Testing1mA@1650VL. Cheng and J. PalmourCopyright 2014, Cree, Inc.9th Annual SiC MOS Workshop, UMD, USA, August 14-15, 20149

Further reduction in RON,SP of Cree’s 3rdGeneration SiC Power MOSFETs since last MOSWorkshop in August, 2013

3rd Generation (Gen-3) SiC MOSFETsSmaller pitchSource Contact MetalSource Contact MetalInter-metal DielectricInter-metal DielectricDegenerately doped Poly Si GateN Degenerately doped Poly Si GateSourceGate OxideN SourceGate OxideN N P-WellP-WellOptimized dopingN 4H SiC SubstrateN 4H SiC SubstrateDrain Contact MetalGen-2 DMOSDrain Contact MetalGen-3 DMOSSame high-reliability DMOSFET Structure,but optimized to dramatically reduce die size.L. Cheng and J. PalmourCopyright 2014, Cree, Inc.9th Annual SiC MOS Workshop, UMD, USA, August 14-15, 201411

1200 V/80 m , Gen-3 MOSFETs: 2.7 m .cm2 in R&D, 2014At VG 20 V, ID 15 A: RON,SP (25 C) 2.7 Adie 6.82 mm2 (2.35 x 2.9)m cm2 Active area: 3.41 mm2 RON,SP (150 C) 4.9 m cm25VG 0 V 20 V401620 V @ 4.67 AIncrement 5 VID ( A) at VG 0 V35ID (A)3025201510at VG 0 V432150001234VD (V)56704008001600BVDS (V)L. Cheng and J. PalmourCopyright 2014, Cree, Inc.12009th Annual SiC MOS Workshop, UMD, USA, August 14-15, 201412

Negligible BTS VTH shifts for Gen-3 MOSFET at 175 CPBTS at 175 C, VGS 20VIn-Situ Monitored Data5.04.54.03.53.02.52.01.51.00.50.0VT (V)VT (V)NBTS at 175 C, VGS -10V0100200300400Time (hr)500600In-Situ Monitored 500600Time (hr) Excellent VTH stability is demonstrated repeatedly at 175 C Same excellent gate yield and repeatability as Gen-2 MOSFET involume productionL. Cheng and J. PalmourCopyright 2014, Cree, Inc.9th Annual SiC MOS Workshop, UMD, USA, August 14-15, 201413

Gen-3 MTTF Lifetime Higher Than Gen-2 MOSFETsTime (Hours)MTTF Prediction from Accelerated Field TestingGen 3 with only10% failures at175 CGen 2 Tested tofailure (50%) at150C Gen 2 Extrapolated MTTF of 3E7 hours at VDS 800 V and 150C Gen 3 lifetimes are higher than Gen 2 at 175 CL. Cheng and J. PalmourCopyright 2014, Cree, Inc.9th Annual SiC MOS Workshop, UMD, USA, August 14-15, 201414

Scaling of State-of-Art Gen-3 SiC Power MOSFETs in R&DRON,SP (m cm2) at VG 20 VGen 3, 15 kVGen 3, 10 kV100 RCh/RON becomes largerfor lower-V MOSFETs. For Gen-3 1200V MOSFET,RCh 40% of total RON.Gen 3, 6.5 kVGen 3, 3.3 kV10Gen 1, 1.2 kVFuture ProspectiveGen 2, C2MFamily 1.2 kV Reduce RCh/RON by:Gen 3, 1.2 kVo Improving MOS INVGen 3, 900 Vo Higher packing density11001,000Breakdown Voltage (V)10,000L. Cheng and J. PalmourCopyright 2014, Cree, Inc.9th Annual SiC MOS Workshop, UMD, USA, August 14-15, 201415

Distribution authorized to U.S. GovernmentAgencies for administrative or operational use.Sponsored in part under CooperativeAgreements W911NR-10-2-0038 and W911NF12-2-0064 and Subcontract # 0145-SC-205790285. Includes Cree confidential information.High-mobility 4H-SiC (0001) MOSFETs withChemically Modified MOS-InterfaceDaniel J. Lichtenwalner, Lin Cheng, & John W. PalmourJointly funded by Cree IR&D and Army HEPS ProgramsCree, Inc.August 14, 20149th Annual SiC MOS Workshop, UMD, USA, Aug 14-15, 2014

OUTLINE1. Motivation1. Channel resistance2. MOS interface passivation2. Experimental: interface modification1. Device Fabrication2. Measurements3. MOSFET channel properties (All data reserved to be published later)1. Field-Effect Mobility2. MOS Interface charge4. MOSFET gate oxide properties (All data reserved to be published later)1. Material characterization2. Electrical properties5. SummaryD. J.L.Lichtenwalner,L. Cheng, J. PalmourCheng and J. PalmourCopyright 2014, Cree, Inc.9th Annual SiC MOS Workshop, UMD, USA, August 14-15, 201417

1.1 MOSFET channel resistance For low voltage devices, channelresistance becomes a large % oftotal device resistance.Ways to lower Rchan: Increase channel packing density improve channel mobility1E 02On Resistance (Ohm-cm2) Graph shows resistance limits dueto drift layer.Resistance limitSi1E 001E-02presentlySiC1E-04w/ IncreasedCh. Mobility1E-061E 021E 031E 04Breakdown Voltage (V)e.g., 1700VBD: Rch 25% of Ron600VBD: Rch 40% of RonD. J.L.Lichtenwalner,L. Cheng, J. PalmourCheng and J. PalmourCopyright 2014, Cree, Inc.9th Annual SiC MOS Workshop, UMD, USA, August 14-15, 201418

1.2 MOS interface passivation (Group V)NO, N2O anneal: **FE Mobility 35 cm2/V.s (Si-face) 85 cm2/V.s (A-face) *Interface N 5 1014 cm-2 (Si-face)N 9 1014 cm-2 (A-face) ideal SiO2 oxide qualityData: Yi Xu et al., ARL workshop Aug. 22, 2013.Phosphorous processing: *FE Mobility 85 cm2/V.s (Si-face) 125 cm2/V.s (A-face) *Interface P 1.8 1014 cm-2 (Si-face)P 1.6 1014 cm-2 (A-face) Poor oxide quality/stability; Phostypically throughout oxideS. Kotake et al., Mat. Sci. Forum 679-680 (2011).*,**G. Lui et al., EDL 34 (2013).**Lichtenwalner et al., MRS spring meeting (2013, 2014).D. J.L.Lichtenwalner,L. Cheng, J. PalmourCheng and J. PalmourCopyright 2014, Cree, Inc.9th Annual SiC MOS Workshop, UMD, USA, August 14-15, 201419

1.2 MOS interface passivation (Group I)Sodium effects: *FE Mobility to 220 cm2/V.s (Si-face) **Interface Na 1 1014 cm-2 (Siface) Device m, VT unstable, mobileionsHydrogen anneals: *FE Mobility 5 cm2/V.s (Si-face)to 200 cm2/V.s (A-face) **Interface H 6 1013 cm-2 (A-face) Hydrogen doesn’t benefit Si-face;weakly bonded, MOS instabilityF. Allerstam et al., JAP 101 (2007).T. Endo et al., Mat. Sci. Forum 600-603 (2009).* B. Tuttle et al., JAP 109 (2011).** F. Allerstam et al., JAP 101 (2007).* H. Yano et al., APL 78 (2001).** T. Endo et al., Mat. Sci. Forum 600-603 (2009).D. J.L.Lichtenwalner,L. Cheng, J. PalmourCheng and J. PalmourCopyright 2014, Cree, Inc.9th Annual SiC MOS Workshop, UMD, USA, August 14-15, 201420

1.2 MOS interface passivation: approachThe Ideal Passivation: Interface concentrations 1 1013cm-2 needed to passivate thermaloxide/SiC NIT states. All concentrated at interface. Strongly bonded, stable interface.Our Approach: Investigate effects of Group I &Group II elements. Utilize deposited SiO2 as the gateoxide.Project initiated by A. Agarwal, J. Palmour atCree and initially funded by Cree IR&D in 2010.U.S. Patent applications: 20120326163 Dec 201220120329216 Dec 201220130034941 Feb 2013D. J.L.Lichtenwalner,L. Cheng, J. PalmourCheng and J. PalmourCopyright 2014, Cree, Inc.9th Annual SiC MOS Workshop, UMD, USA, August 14-15, 201421

2. Experimental: Si-face SiC lateral MOSFETsLateral MOSFET Fabrication: Al doped p-type SiC (0001)channel Deposited passivation layer Deposited SiO2 gate oxide Poly-Si gateMeasurements: Lateral MOSFET: ID-VD ID-Vg vs Temp(VT, F.E. mobility) Quasi-static gate C-V(Tox, Vfb, VT, Qf) Gate Ig-Vg(CB, VB F-N barrier height, EBD)ILGateSSiO2DN (All data reserved to be published later)N P-epi SiCD. J.L.Lichtenwalner,L. Cheng, J. PalmourCheng and J. PalmourCopyright 2014, Cree, Inc.9th Annual SiC MOS Workshop, UMD, USA, August 14-15, 201422

Thank you!Question?

Gen 3, 6.5 kV Gen 3, 900 V Gen 2, C2M Family 1.2 kV Gen 1, 1.2 kV Gen 3, 1.2 kV Scaling of State-of-Art Gen-3 SiC Power MOSFETs in R&D RCh/RON becomes larger for lower-V MOSFETs. For Gen-3 1200V MOSFET, RCh 40% of total RON. Future Prospective Reduce RCh/RON by: o Improving MOS INV o Higher packing density

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