Dynamic Logic - Concordia University

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Dynamic Logic Dynamic Circuits will be introduced andtheir performance in terms of power, area,delay, energy and AT2 will be reviewed. We will review the following logic families: Domino logic P-E logic NORA logic 2-phase logic Multiple O/P domino logic Cascode logic11/28/20121

A brief introduction toDynamic logic Dynamic logic Steady-State Behavior of DynamicLogic Performance of Dynamic Logic Noise Considerations in DynamicDesign11/28/20122

Dynamic Latch: ChargeLeakageStored charge leaks away due to reverse-bias current. Stored value is good for about 1 ms. Value must be rewritten to be valid. If not loaded every cycle, otherwise it must be ensured that thelatch is loaded often enough to keep data valid. DXCd Cg X11/28/20123

Dynamic Latch-Operation Usescomplementary transmission gate to ensure that storagenode is always strongly driven. Latch is transparent when transmission gate is closed. Storage capacitance comes primarily from transmission gatediffusion capacitance and inverter gate capacitance. 0: transmission gate is off, inverter output is determined bystorage node. 1: transmission gate is on, inverter output follows D input. Setup and hold times determined by transmission gate—mustensure that value stored on transmission gate is solid.11/28/20124

Dynamic CombinationalLogicPrecharge/ Evaluate NetworksVDD VDD MpOutCLIn1In2In3PDNPUNOut Me n network11/28/2012In1In2In3Mp Me p networkCL5

Example of Dynamic CircuitOUTPUTACBCLKCLKOUTPUT11/28/2012Precharge Evaluation Precharge6

General ConceptPrecharge and EvaluationMp precharge transistorOUTPUTABCCLK фCLKOUTPUTMeEvaluation transistorPrecharge Evaluation Precharge11/28/2012 Exampleof nmos block For OUTPUT (A.B C)’ 7

Charge and dischargeClock, фABCOutput11/28/20128

Overcoming the charge leakage andthe charge sharingMpOUTPUTACBCLK ф11/28/2012Me9

Example continueVDD Mp N 1 TransistorsOut Ratioless No Static Power ConsumptionA Noise Margins small (NMCL) Requires ClockB 11/28/2012Me10

Charge Leakage11/28/201211

Charge Sharing11/28/201212

Clock Feed through11/28/201213

Cascading Dynamic Logic11/28/201214

Transient Response6.0 Vout (Volt)4.0VoutEVALUATIONPRECHARGE2.00.00.00e 0011/28/20122.00e-09t (nsec)4.00e-096.00e-0915

4 Input NANDVDDOutIn1In2In3In4 GND11/28/201216Prentice Hall/Rabaey

Dynamic Flip-Flop XD xYQ XXYQ11/28/201217

P-E logic Instead of using a static invert to ensure that 0 to 1transitions occur during precharge, we can exploit theduality between n- block and p-block . Theprecharge output value of n- block equals 1, which isthe correct value for the input of a p-block duringprecharge. All PMOS transistors of the Pull-Up Network(PUN) are turned off, so, an erroneous discharge at the onset of the evaluation phase is prevented. In a similar way,an n- block can follow a p-block without anyproblem, as the precharge value of inputs equals 0. Tomake the evaluation and precharge times of the p and n-block coincide, one has to clock the p-block with aninverted clock p’.11/28/201218

PE LogicVDD VDD MpOutCLIn1In2In3PDNPUNOut Me n network11/28/2012In1In2In3Mp MeCL p network19

Domino logicA Domino logic module consists of a nblock followed by a static inverter.This ensures that all inputs to thenext logic block are set to 0 after theprecharge periods. Hence, the onlypossibletransitionduringtheevaluation period is 0 to 1 transition,so that formulated rule is obeyed.11/28/201220

The block of Domino logic11/28/201221

One Bit full Adder-Domino11/28/201222

Simulation Results11/28/201223

Multiple O/P DominoLogicThe main concept behind MODL is theutilization of sub-functions available in thelogic tree of domino gates, thus savingreplication of circuitry. The additionalouputs are obtained by adding prechargedevices and static inverters at thecorresponding intermediate nodes of thelogic tree.11/28/201224

Multiple Output Domino CCCC1234 GGGG1234 PPPP1234C0C1C2C3 Expanding the above in terms of C1,C2,C3:C1 G1 P1C0C 2 G 2 P 2 (G 1 P 1 C 0)C 3 G 3 P 3 (G 2 P 2 (G 1 P 1 C 0))C 4 G 4 P 4 (G3 P 3 (G 2 P 2 (G 1 P 1 C 0)))Expanding it fullyC1 G1 P1C0C2 G2 P2G1 P2P1CoC 3 G 3 P 3 G 2 P 3 P 2 G 1 P 3 P 2 P 1 C 0C 4 G 4 P 4 G 3 P 4 P 3 G 2 P 4 P 3 P 2 G 1 P 4 P 3 P 2 P 1 C 011/28/201225

Multiple output Domino11/28/201226

MODL 4-bit Carry BlockC1 G1 P1C0C2 G2 P2G1 P2P1Co11/28/201227C 3 G 3 P 3 G 2 P 3 P 2 G 1 P 3 P 2 P 1 C 0C 4 G 4 P 4 G 3 P 4 P 3 G 2 P 4 P 3 P 2 G 1 P 4 P 3 P 2 P 1 C 0

2-Phase Logic We can use two-phase clock tocontrol logic transition similar to PE.A single clock (phi1 or phi2) is usedto precharge and evaluate the logicblock. The succeeding stage isoperated on the opposite clock phase.A latch is needed between twostages.11/28/201228

tionEvaluation gicFrom ф2stageTo ф1 stageф2ф1Ф1’11/28/2012PrechargeФ2’29

2-Phase Domino logic11/28/201230

NORA Logic Combining C2MOS pipelineregister and P-E CMOS dynamiclogic function block, we getNORA-CMOS (mean NO-Race).The method is suitable for theimplementation of pipelineddatapaths.11/28/201231

The block of NORA logicCMOSINVERTER11/28/201232

Cascode Logic Further refinement leads to a clockedversion of the CVSL gate. This is really justtwo “Domino” gates operating on the trueand complement inputs with a minimizedlogic tree. The advantage of this style oflogic over domino logic is the ability togenerate any logic expression, making it acomplete logic family. This is achieved atthe expense of the extra routing, active area,and complexity associated with dealing-raillogic.11/28/201233

CASCOD Logic11/28/201234

Comparison of 8-bit AddersDesigned with Dynamic LogicSeven circuits using six dynamic logicfunctions are designed and simulated.The performance in terms of power,area, delay, energy and AT2 arecompared.11/28/201235

Dynamic Logic Adders thatare designed and compared Domino logic 8-bit AdderP-E logic 8-bit AdderNORA logic 8-bit Adder2-Phase Logic 8-bit AdderMultiple O/P Domino Logic 8-bit AdderCascode Logic 8-bit Adder11/28/201236






Conclusion Domino Logic: It has minimumarea and number of transistors.The power consumption is low, andthe delay is the longest. The DPand AT2 are average. If the designgoal is minimum area and speed isa secondary concern the Dominologic is the best structure forRipple Carry Adder.11/28/201242

Conclusion .P-E Logic: has a small area and theminimum number of transistors.The power consumption is low,and the delay is short. It has thelower DP and AT2 for Ripple CarryAdder. If the logic has no inherentrace problem, it will be the bestchoice for Ripple Carry Adder.11/28/201243

Conclusion .P-E (race-free) Logic: In order to avoid therace condition of P-E Logic, the P-E (racefree) Logic is introduced. It has a small areaand average of number of the transistors.The area and number of transistors is largerthan P-E logic. The power consumption isaverage. The delay is shortest. It has lowerDP and AT2 for Ripple Carry Adder. Forsynthesis, it is the best choice for RippleCarry Adder.11/28/201244

Conclusion . NORALogic:Thepowerconsumption is higher. The area issmall, and using a few transistorsexcept Domino logic. The delay islonger. The DP is high and AT2 areaverage.11/28/201245

Conclusion . 2-Phase Logic: The area is largerand the number of transistors ismore than others except Cascodelogic. The delay is longer. Thepower consumption, DP and AT2are extremely high. Try to avoidthis logic structure for designingRipple Carry Adder.11/28/201246

Dynamic Circuits: Advantages &DisadvantagesAdvantages: Circuits occupy less area than the static circuitsCircuits Operate at higher speed than static CMOSCircuits are Noise sensitiveDrawbacks: Affected by charge sharing and charge re- distributionAlways require clocksCannot operate at low frequencyDesign is not straight forward11/28/201247

FINAL WORD Thank you for being good students. I hope you have learned something in this class,that it will be useful in your future endeavor. Always go to the root of any problem that you aresolving, whether engineering or social. Be a Good engineer, Never forget yourEngineering ethics. Always keep your mind open to new ideas anddevelopment, and have vision as were the world isheading and try to be there before others. Do NOT forget the “environment”. Be a team player. Always be a dignified Engineer, respect yourselfand other people’s dignity. Be just to yourself and give justice to others. Always11/28/2012 Have good intentions with your thinking,48actions and speaking.THANK YOU

Ф1’ф2’ф1From lockTo ф1 stagesф2ф2’49

2-phase domino logic11/28/201250

Dynamic Logic Dynamic Circuits will be introduced and their performance in terms of power, area, delay, energy and AT2 will be reviewed. We will review the following logic families: Domino logic P-E logic NORA logic 2-phase logic Multiple O/P domino logic Cascode logic

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