Dynamic Logic And Latches II - Stanford University
Dynamic Logic and Latches II:Practical Implementation Methodsand Circuits Examples used on theALPHA 21164Paul GronowskiWilliam BowhillDigital SemiconductorDigital Equipment CorporationHudson, MADynamic Logic and Latches - Part II1996 VLSI Circuits WorkshopOutlineintroduction to ALPHA 21164LatchingClockingllDistributionAnalysisDynamic LogicllSingle-railDual-railCircuit Examples.1996 VLSI Circuits WorkshopDynamic Logic and Latches - Part II
Introduction to ALPHA 21164Second generation designQuad-issue, in-order execution14 gates per cycle including latches0.5Transistor CountDie SizePower SupplyWC Power DissipationTarget Cycle Time1996 VLSI Circuits Workshop1996 VLSI Circuits Workshopprocess9.3 Million16.5 mm x 18.1 mm3.3V external3.3V internal50W @ 300 MHz300 MHz0.35process9.66 Million14.4 mm x 14.5 mm3.3V external2.0V internal25W @ 433 MHz433 MHzDynamic Logic and Latches - Part IIDynamic Logic and Latches - Part II
Latching - OverviewLevel-sensitive designDynamic latcheslllFasterLess areaRequired to function at 1/10th speedGeneral purpose libraryllFully characterizedEmphasis on speedDynamic Logic and Latches - Part II1996 VLSI Circuits WorkshopLatching - Latch Implementation1IIIIIIIIICLKAny Gate C .KMinimum one gate between any two latching points required1996 VLSI Circuits WorkshopDynamic Logic and Latches - Part II
Latching - Embedding LogicLatching costs only 2 pass gates per cycleDynamic Logic and Latches1996 VLSI Circuits Workshop- Part IILatching - Circuit ImplementationCLK-HI VersionCLK-LO Version21064Latches:21164Latches:1996 VLSI Circuits WorkshopDynamic Logic and Latches - Part II
Latching - ComparisonArea1.25Speed1.2RaceCLK edgerate,CLK edge1.25Da1.01.21.3rateCLK bufferdelay1.0-CLKedgerateCLKCLK edgeData1.01.0CLK1996 VLSI Circuits WorkshoprateCLK bufferdelay1.0Dynamic Logic and LatchesIILatching - Verification IssuesRace verificationRace speed analysis (SPICE)Custom race tool specific to design methodologyLatch size checksMinimum/maximum clock edge rateClock buffer not sharedAt least one gate delay between latchesLatch driven by clock or deskewedFunctional verification (for static latches)llDC noise margin analysis (SPICE)DC writeability analysis (SPICE)Full dynamic logic verification1996 VLSI Circuits WorkshopDynamic Logic and Latches - Part II
Clocking - OverviewSingle-wire, two phase clocking schemeSingle global clock gridLimited use of conditional clocksClock statistics (0.5design)Clock load 3.75 nFllllllSize of final clock inverter 58 cmEdge rate 0.5 nsClocking consumes 40% of chip powerDecoupling capacitance near clocks 35 nFdi/dt 50 ADynamic Logic and Latches1996 VLSI Circuits Workshop- Part IIClockinginterconnecty-Total CapacitanceCACHEIiiii3.75 nFGlobal Interconnect1 .OO nFLocal Interconnect0.95 nFGate Capacitance1.20 nFself Loading0.60 nFiiI I IIIIIiII!Dynamic Logic and Latches - Part II
CLOCKFROMGENERATOR OCKDynamic Logic and Latches - Part IIClocking - Analysisgeneration. and driver networkevaluated using SPICEllVSS and VDD supply noiseDevice variations across the chipdelay of global clock interconnectevaluated using extracted R and C datallGlobal clock skew can limit speedLocal clock skew can create race-through1996 VLSI Circuits WorkshopDynamic Logic and Latches - Part II
Clocking - Global Clock Skew90ps60 ps30 ps0ps-1996 VLSI Circuits Workshop- Part IIDynamic Logic and LatchesClocking - Skew Sensitive CircuitCLK-HI LATCHII.IICLK-LO LATCHIIIIIIIIIIIIIIICLKIIRC Delay1996 VLSI Circuits WorkshopDynamic Logic and Latches - Part II
Clocking Local Clock Skew-25.0 ps22.5 ps20.0 ps17.5 ps15.0 ps12.5 pS10.0 pS7.5 ps5.0 ps2.5 pS1996 VLSI Circuits WorkshopDynamic Logic and Latches Part IIDynamic Logic Overview-Dynamic logic requires significantly moreelectrical verification than static logic.lllllCapacitive coupling and charge sharingSubthreshold leakageCharge injection-Minority carrier collection-Latch-upAlpha particle immunityVDD/VSS noise and resistance1996 VLSI Circuits WorkshopWDynamic Logic and Latches - Part II
Dynamic Logic - Circuit DiagramCOUPLING TODYNAMIC NOUTIN LCOUPLlNGTO‘LEAKIvss ATDRIVERRECEIVER1996 VLSI Circuits WorkshopDynamic Logic and Latches - Part IIDynamic Logic - General RulesDynamic logic can only be driven bycomplementary gatesComplementary gates must be close todynamic structurellGlobal nodes received by gates with standardratio (noise margin)Local nodes can be received by gates with askewed ratio (for speed)Precharge controlled by clockllDelayed precharge not typically usedDomino or ripple precharge not typically used1996 VLSI Circuits WorkshopDynamic Logic and Latches - Part II
Dynamic Logic - CouplingCoupling is difficult to analyze preciselylllWhat capacitance should be used?When do “aggressor” signals change?What is the rise/fall time of “aggressor” signals?COUPLING TODYNAMIC NODEPCH4DYNAMIC NODECOUPLINGTO STATIC NODEDynamic Logic and Latches1996 VLSI Circuits Workshop- Part IIDynamic Logic - Coupling Circuit DiagramStatic NodesDynamic NodesNote: High-up coupling on stored “1” nodes and Low-down couplingon stored “0” nodes can be a problem as well.1996 VLSI Circuits WorkshopDynamic Logic and Latches - Part II
Dynamic Logic - Coupling SolutionsSet limits on maximum allowable coupling and inputand output beta ratio ranges to ensure acceptablenoise margin.Account for canceling coupling events - be careful!Shield and/or isolate dynamic nodes where possible.Increase overall “good” (fixed) capacitance to reducethe impact of “bad” coupling capacitance.In datapaths, examine bus ordering (see below).“Twist” lines (as shown at right) totake advantage of power railsRoute dynamic lines betweenmutually exclusive or complementaryVddlinesABCABCllVddDynamic Logic and Latches - Part II1996 VLSI Circuits WorkshopDynamic Logic - Coupling ExampleDYNAMIC NODEDYNAMICNODEITime1996 VLSI Circuits WorkshopDynamic Logic and Latches- Part II
Dynamic Logic - Charge ShareCharge sharing can occur when internal nodes (node X)are not adequately precharged.V dyn 1996 VLSI Circuits WorkshopDynamic Logic and Latches - Part IIDynamic Logic - Charge ShareAnother Example:Solutions:Minimize diffusion capacitanceon charge share nodePrecharge “X” with nmos device less area for precharge faster- buffered clock requiredPrecharge “X” with pmos device1996 VLSI Circuits WorkshopDynamic Logic and Latches - Part II
Dynamic Logic - Subthreshold LeakageSubthreshold leakage may be a problem foris large.dynamic nodes whereDetermine leakage time:leakCircuit solutions:Increase channel lengthAdd weak “leakers”llDifferential Bus1996 VLSI Circuits WorkshopDynamic NodeDynamic Logic and Latches- Part IIDynamic Logic - Charge InjectionLatch-upMinority carrier charge injection/collectionp-epi substrate1996 VLSI Circuits WorkshopDynamic Logic and Latches - Part II
Dynamic Logic - Charge InjectionOriginalLayout:AfterFix:1996 VLSI Circuits WorkshopDynamic Logic and Latches- Part IIDynamic Logic - Dual-rail DesignAdvantagesFast - use sense amp todetect small voltage swing onoutput or skew the beta ratio ofoutput complementary gates.Complex logic functions canbe easily generated as trueand complement of all signalsavailable.Since both outputs (OR Land OR H) start low afterprecharge, can sense whenlogic is complete by detecting01 or 10.1996 VLSI Circuits WorkshopDynamic Logic and Latches- Part II
Dynamic Logic Dual-rail Design-Design IssuesPower dissipation. One side of the logic is always evaluated.Area. Requires roughly twice the area of single-rail design.Coupling may be an issue, especially in datapath structures- Twisted bit lines- Bus ordering- Encode Lines (HP PA8000 Floating Point Unitsee references)Dual-rail inputsInputsEncoded inputsA B A H A L B H B L AB3 AB2 AB1 A B 00011010100111100010110100001001001001000Dynamic Logic and Latches1996 VLSI Circuits Workshop-Circuit Example #1 - E-Box BypassBlock DiagramBypass SelectTo Othernal UnitsFunction Unit(ALU)ResultCLK1996 VLSI Circuits WorkshopDynamic Logic and Latches- Part IIIi
E-box Bypass - Circuit DiagramFunction UnitBus Precharge DelayResultL0GICOperand Bus DriverBypassna eCLKOperand Bus(Distributed Dynamic Bypass MUX)Dynamic Logic and Latches - Part II1996 VLSI Circuits WorkshopBypass Bus O:63 HCircuit Example #2 E-Box ShifterBlock Diagram0Zap ogicBypass Drivers1996 VLSI Circuits WorkshopDynamic Logic and Latches - Part II
llE-box ShifterCircuit SchematicDynamic Logic and Latches1996 VLSI Circuits Workshop- Part IIlReferences“A Dual-Execution Pipelined Floating-Point CMOS Processor”John Kowaieski, et al., 1995 IEEE ISSCC Digest of Technical Papers“A 433 MHz 64b Ctuad-Issue CMOS RISC Microprocessor”Paul Gronowski, et al., 1995 IEEE ISSCC Digest of Technical Papers“A Dual Floating Point Coprocessor with an FMAC Architecture”Craig Heikes and Glenn Colon-Bonet, 1995 IEEE ISSCC Digest of Technical Papers“Dynamic Logic: Clocked and Asynchronous” TutorialTed Williams, 1995 IEEE ISSCC Digest of Technical Papers and Tutorial hand-out“A 300 MHz 54b Quad-issue CMOS RISC MicroprocessorBradley Benschneider, et al., IEEE Journal of SolidState Circuits, Nov. 1995, Vol. 30., No. 11“A 300 MHz 64b Quad-issue CMOS RISC Microprocessor”William Bowhiii, et al., 1995 IEEE ISSCC Digest of Technical Papers“Design and Verification Strategies for Ensuring Long-Term Reliability of a 300 MHz Microprocessor”Ronald Preston, et al., ESSCIRC ‘95 Proceedings“Superscalar instruction Execution in the 21154 Alpha Microprocessor"John Edmondson, et al., IEEE Micro, Vol. 15, No. 2, April 1995“Circuit implementation of a 300-MHz 64-bit Second-generation CMOS Alpha CPUWilliam Bowhiii, et al., Digital Technical Journal, Voi. 7., No. 1, 1995“internal Organization of the Alpha 21154, a 300-MHz 64-bit Quad-issue CMOS RISC Microprocessor”John Edmondson, et al., Digitai Technical Journal, Vol. 7., No. l,l9951996 VLSI Circuits WorkshopDynamic Logic and Latches -Part II
More References“Impact of Clock Slope on True Single Phase Clocked (TSPC) CMOS Circuits”Patrik Larsson and Christer Svensson, IEEE Journal of Solid-State Circuits, June 1994, Vol. 29, No. 6“Noise in Digital Dynamic CMOS Circuits”Patrik Larsson and Christer Svensson, IEEE Journal of Solid-State Circuits, June 1994, Vol. 29, No. 6“A Comparison of CMOS Circuit Techniques: Differential Cascade Voltage Switch Logic VersusConventional Logic”Kan M. Chu and David L. Pulfrey, IEEE Journal of Solid-State Circuits, Aug. 1987, Vol. SC-22, No. 4“Design Procedures for Differential Cascade Voltage Switch Circuits”Kan M. Chu and David L. Pulfrey, IEEE Journal of Solid-State Circuits, Dec. 1986, Vol. SC-21, No. 6‘Clocking Schemes for High-Speed Digital Systems”Stephen H. Unger, Chung-Jen Tan, IEEE Transactions on Computers, Oct. 1986, Vol. C-35, No. 10“Custom and Semi-Custom Design Techniques”Lawrence G. Heller, et al., 1984 IEEE ISSCC Digest of Technical Papers“NORA: A Racefree Dynamic CMOS Technique for Pipelined Logic Structures”Nelson F. Goncalves and Hugo J. De Man, IEEE Journal of Solid-State Circuits, June 1983,Vol. SC-18, No. 3“High-Speed Compact Circuits with CMOS”R. H. Krambeck, et al., IEEE Journal of Solid-State Circuits, June 1982, Vol. SC-1 7, No. 31996 VLSI Circuits WorkshopDynamic Logic and Latches - Part II
1996 VLSI Circuits Workshop Dynamic Logic and Latches -Part II Dynamic Logic - Coupling Circuit Diagram Static Nodes Dynamic Nodes Note: High-up coupling on stored “1” nodes and Low-down coupling on stored “0” nodes can be a problem as well. 1996 VLSI Circuits Workshop Dynamic Logic and Latches -Part II
8. n-CH Pass Transistors vs. CMOS X-Gates 9. n-CH Pass Transistors vs. CMOS X-Gates 10. Full Swing n-CH X-Gate Logic 11. Leakage Currents 12. Static CMOS Digital Latches 13. Static CMOS Digital Latches 14. Static CMOS Digital Latches 15. Static CMOS Digital Latches . Joseph A. Elias, PhD 2
Dynamic Logic Dynamic Circuits will be introduced and their performance in terms of power, area, delay, energy and AT2 will be reviewed. We will review the following logic families: Domino logic P-E logic NORA logic 2-phase logic Multiple O/P domino logic Cascode logic
latches on 2011MY Sorento (XMa) vehicles. Kia has determined that after extended usage over years, the door latches may not function properly when being activated with the outside handle and the door may not open. For Front Door Latches: Vehicles may have previously had one or both front door latches replaced with improved ones.
categorical and hypothetical syllogism, and modal and inductive logic. It is also associated with the Stoics and their propositional logic, and their work on implication. Syllogistic logic and propositional logic led later to the development of predicate logic (or first order logic, i.e. the foundational logic for mathematics)
MOSFET Logic Revised: March 22, 2020 ECE2274 Pre-Lab for MOSFET logic LTspice NAND Logic Gate, NOR Logic Gate, and CMOS Inverter Include CRN # and schematics. 1. NMOS NMOSNAND Logic Gate Use Vdd 10Vdc. For the NMOS NAND LOGIC GATE shown below, use the 2N7000 MOSFET LTspice model that has a gate to source voltage Vgs threshold of 2V (Vto 2.0).File Size: 586KB
Digital Logic Fundamentals Unit 1 – Introduction to the Circuit Board 2 LOGIC STATES The output logic state (level) of a gate depends on the logic state of the input(s). There are two logic states: logic 1, or high, and logic 0, or low. The output of some gates can also be in a high-Z (high impedance) state, which is neither a high
DESIGNING SEQUENTIAL LOGIC CIRCUITS Implementation techniques for flip-flops, latches, oscillators, pulse generators, n and Schmitt triggers n Static versus dynamic realization Choosing clocking strategies 7.1 Introduction 7.2 Timing Metrics for Sequential Circuits 7.3 Classification of Memory Elements 7.4 Static Latches and Registers
Archaeological Investigations and Recording 1994-2011 by David James Etheridge with scientific analysis by Dr David Dungworth Avon Archaeological Unit Limited Avondale Business Centre, Woodland Way, Kingswood, Bristol, BS15 1AW Bristol 2012 Illustration taken from the ‘Annales des Mines” Vol 10, dated 1825 . William Champion’s Warmley Brass and Zinc works, Warmley, South Gloucestershire .
