NORA: A Racefree Dynamic CMOS Technique For Pipelined .

2y ago
45 Views
2 Downloads
934.51 KB
6 Pages
Last View : 2d ago
Last Download : 2m ago
Upload by : Allyson Cromer
Transcription

IEEIE JOURNALOF SOLID-STATECIRCUITS,VOL.SC-18,NO.3, JUNE1983261Heinz Schulte was born in Meschede,Germany,Rupert Kling was born in Bayrischzell,Germany,on December12, 1944.He received the M.S.degree in electricalengineeringfrom the Technical Universityof Munich,Munich,West Germany,on August 17, 1937. He received the diplomain physics from the Technische Hochschule,Aachen, West Germany, in 1968.Since 1968 he has been employed asa Development Engineer at the semiconductor factoryof Siemens Company, Munich, West Germany.of siliHe has been engaged in the developmentin 1973.In 1973 he joinedthe Siemens ComponentDivision,Munich,West Germany.He wasworkingin the field of test program generationfor various MOS-LSIcircuits.At present, he isa member of a design team for NMOS IC’S.con-gatetechnologyfor memorydevices.NORA: A Racefree Dynamic CMOS TechniquePipelined Logic StructuresNELSONF. GONCALVES,STUDENT MEMBER, IEEE, AND HUGO J. DE MAN,A ,@l@-This paper describesa new dywicis fullyracefree,yet has high logic flexibility.free fro]m two clocks@to the criticalIinealclockcircuits,amounttheskew specificationproposedof clock skew.are OSnoiseare also analyzed.willtime.imposesblocksCMOS pipe-of the stheshowdynamicthe feasi-INTRODUCTIONN the conventional CMOS technique there is an inherent redundancy of information.For each n-type device there is acorrespondingp-type device. NMOScircuits.CMOS logic, these transmission gates are generally implementedwith p-n gates in parallel and controlled by clocks o and T, asshown in Fig. 1. The use of single gates (p-or n-type) is to beavoidedIPMOSThe effectsindiscussed.I. Fig. 1, Signal races in CMOS pipe edThis means higherfor the same function.andfunctionsdynamicbe presented.margin,to thetechniqueStatic CMOSis also provided.race-In contrastno restrictionrules to mixSENIOR MEMBER, IEEEwhichoperatein the conventionallogic functions.and less transistorsof the principlestheir overlapcompositioninversionredistribution,CMCK3 blocksbilityThe main buildingconventionaltechnique,chargetechniqueand C2MOScan ;also be employed.C 2MOS,and regardlessofCMOS techniqueThe circuitsforIn fact, a complete logic functionis built with the n devices and repeated with the p devices. Aa ain CMOS due to powerdissipationand low noisemar@ as a result of clock feedthrough and bulk effect. CMOSp-n transmission gates, controlled by clocks o and , sufferfrom signal races. As depicted in Fig. 1, this results from unavoidable overlap of the clock phases during the clock tranDuring the phase overlaps, all the transmission gatessitions.consequence of this approach, substantial amounts of siliconare wasted, especially for complex logic. Also, power dissipa-are switched on, which may cause illegal flow of information,tion and speed are degraded by the extra area and extra tran-skew.This race problemsistors.Anotherimportantproblem of CMOS technique is clock racesdependingnizationon the ratio between the gate delay and the clockis usually bypassed by a careful synchro-of the two clock phases withina small fractionof thein pipelinedgate delay (a few nanoseconds).pipelinedtremely difficult,especially for high speed technologies, forunmatched clock loads or for distributed clock VLSI circuits[1].This leads to highly critical and untestable designs. Apossible solution to the clock race is the use of four clock phaseswhich, however, requires too much siliconl area.To overcome the redundancy of informationin the conven-circuits.To latch the informationbetween twosections, transmission gates are usually employed. InManuscriptreceivedNovember8, 1982; revised JanuaryThis wc,rk was supportedin part by Funda aode Amparodo Estado de S50 Paulo, Brazil.The authors are with the DepartmentElektrotechniek-ESAT,lieke UniversiteitLeuven, B 3030-Heverlee,Belgium.18, 1983.a PesquisaKatho-0018-9200/83/0600-0261 01tionalCMOS, dynamic.00 @ 1983 IEEEcircuitThis skew clock control is ex-schemes have been proposed in

262IEEEJOURNALOF SOLID-STATECIRCUITS,VOL.SC-18,NO.3, JUNE1983VDDVDDFig. 2. An n-type dynamic CMOS logic block.VDDFig. 4.vDDG-’-FNIIn the next section, a new technique called NORAistlIi-I OL-Jn-Fig. 3. Internaln-delay race problem.CMOS limitationsthe literature[2] - [4].ing block.Fig. 2 shows the dynamic CMOS build-The desired logic functiononly n-type devices.groundthroughoperation.is implementedThe logic tree is connectedclockedtransistors.usingThen, for phase @ 1, the path to the high level is turned offby the clock and the path to ground is turned on. Therefore,depending on the state of the inputs, the output node willeither float at the high level or will be pulled down.A clear advantage of this CMOS dynamic block is the reducedsilicon area. Whereas there are 2 n transistors in a conventionalCMOS gate, the dynamic configurationneeds onlyALSOduetothe smaller area and consequently smallerand speed are, in principle,proved by the dynamic approach.A strong limitationof this dynamicim-structure is the impossi-bility of cascading the logic blocks for implementingcomplexlogic. Consider, for instance, the circuit in Fig. 3. During theprecharge phase, nodes 111 and fV2 are setup to the high level“1 .“ In the evaluation phase ( 1), internal delay in block 1,associated with a “1” - “O” transitionan incorrectdischarge of node i?2.the evaluationof node JV1, can causeThis occurs because, duringphase and while node iVlis still “1 ,“ there is adirect path between node N2 and ground. When this path iseliminated by the effective transition of node N1 to “O ,“ theprecharge informationof node N2 could already be gone. Wedefine such a race as the “internal delay problem.”In the Domino technique, Krambeck et al. [4] have solvedthe internal race by placing a static inverter after every dynamicblock, as indicated in Fig. 4. During the precharge phase, theoutputs of all the static inverters are set up to a low level. Consequently,all the n-type transistorsdriven by these inputs areset up to an OFF condition.Now, during the evaluation phase,internal delays cannot incorrectly discharge the dynamic storage nodes since during the entire delay period the path to groundis turned off.A limitationsignals.of the Domino techniqueThe combinationExperimentalare presented in Sections V andVI, respectively.There are two modes ofFirst, for phase @ O the output node is prechargedcapacitances, power dissipationare described in Section IV.results and major conclusionsto VDD andto a high level while the current path to ground is turned off.n-inputn 2.presentedwhich overcomes the above deficiencies,In Section III, theproperties of the NORA CMOS technique are analyzed andproved. Logic composition rules to mix dynamic, static, andC2MOS [5] logic functions are also derived.The dynamic‘ circuit.N2 ‘- 1,LDominoII. NORAThe main buildingCMOS TECHNIQUEblocks of NORA techniqueFig. 5,The logic functionsp-typedynamicCMOSare implementedare shown inusing n-type andand C2MOS blocks.Conventional(static) CMOS function blocks can also be eventually employed.Logic composition rules to combine these functions, preservingthe racefree properties,will furtherin pipelinedbe performedstage).will be presented in Section III.be shown, to guarantee a fullycircuits,bythe storage of informationa C2MOS functionIn a previous paper [6],As itracefree operationblockthe NORAmust always(C2MOSlatch(NO l?xtce) tech-nique was called n-p-CMOS, due to the possible employmentof n- and p-dynamicblocks,We decided to change the namebecause the p-dynamic block is not essential to the racefreeprinciple; it is only used to increase the logic flexibility.The pipelined circuit in Fig. 5 is defined as a @-section. Forphase @ O 1, the -section is in the precharge phase. Theoutputs“1”of all the n- and p-dynamicand “O,” respectively.blocks are precharged toMso during this phase, the @sectioninputs are in a sampling mode, i.e, these inputs are set up.For phase @ 1 O, the @-section is in the evaluation phase.The -sectioninputs are held constant,and the outputs of allthe dynamic blocks are evaluated as a functioninputs and of the internalthose which must be transferredto the next pipelinedare stored in C2MOS latch stages.In the circuit of Fig. 5, notice the following(see Section III).1) Invertedrect icsand noninverted signals are provided.When dibetween dynamic blocks is desired, the logicis implementedIf the inverterof the o-sectioninputs 1. From these outputis required,by alternatinga Dominop- and n-logic blocks.like connectionis em-i.e, sequences of the same block type are used (n-is the lack of invertedof the dynamic block with the staticinverter gives a noninverted signal. This decreases logic flexibility and, therefore, usually requires more transistors for a givenlogic function.Besides this inconvenience,made to overcome the clock race problem.no provisionsare1For convenience,the inputs of a dynamic block have been separatedinto section inputsand internalinputs.The section inputs are set Upduring the precharge phase.The internalinputs are set up during theevaluationphase. For instance, in Fig. 5:lN–sectioninputsN 2, N 3–internalinputs.

GONCALVESANDDE ) During the precharge phase, the internal inputs are setupin such a way they cut off their corresponding transistors.‘fipg --l!i!i2) During the evaluationphase, the internal inputs are glitch-free, i.e, these inputs can make only one transition.toFrom the above linedresults can be de-rived:.‘ - ) Fig.5.the followingstagea) When the number of “static” inversions between twodynamic blocks is even, complementarytype of logic blockscircuit-@-section.must be used for these two blocks (n-p or p-n).in Fig. 5, this correspondsto alternateFor instancep- and n-logic blockswhen the direct coupling between dynamic blocks is desired.b) The same type of dynamic blocks (n-nor p-p) must beused when the number of “static” inversions is odd. In Fig. 5,this corresponds!::::TRANSFEREVALUAT 10N10EVALUATTRANSFEREVALUATION1MEEVALUAT 10Nnique,c) Normally,Pipelinedor p-inverter-p).10Nthis means higher logic ]forNAND,NOR. . . .)can easilybe implemented utomaticcheckingin aof the logicconsistency.and less transistorsfor the same function.B. Clock Racefree Properties2) n-p as well as p-n sequences are possible and the sequencescan be of arbitraryafterthe inverter and in some cases thesystem.Compared with the Dominon-inverter-nThis should be done because in general “static”functionsdriven by dynamic blocks are not glitch-free. (Exceptions MOS, the circuit should be kept static up to the C2MOS latchstage. Static functions can also be used after the C2MOS stage.(PRECHARGE)TRANSFERto ECHARGE)logical depth.Therefore,many logic levelscan be operated in only half a clock period.As indicatedin Fig. 6, to have a worjcing pipelined system theresults generatedduringthe evaluationphase must be heldconstant until the end of the transfer phase. The latched information should not be ziltered by the precharge signal or by-- By interchanging o and 7 in the circuit of Fig. 5, a -sectionis obtained.A sequence of @ and -sections makes a pipelined system, as shown in Fig. 6. For phase @ O 1, theinput variations.@sections are precharged while the -sections are in the evaluation phase. The @-section outputs are held constant by thespite of high-high or low-low clock overlaps (clock skew).For simplicity, let us initially consider that all the circuits inC2MOS latchstages.Then,for phase @‘ 1 O, the @-sections are in the evaluationprecharged.phase and the -sectionsNow, the -sectionoutputs,areevaluated in the pre-vious phase, are held constant in such a way that the @sectionsIt will now be proven that after the evaluationphase a NORAthe pipelinedpipelinedsection keeps its outputsection are builttwo exceptionsonly withresults indynarnjc blocks; thebeing the C2 MOS latch stage and the static in-verter for connectingcomplementarydynamic blocks.For thiscircuit, two possible cases should be analyzed.can use this informationto compute the corresponding results.In this way, there is a complete flow of information;with theinformation traveling from one -section to the next -section,from this to the next F-section, and so on.Case I–PrechargeDuringRacefreethe evaluationphase, the dynamicblock which pre-cedes the C2MOS latch stage has its precharge signal modifiedIII.NORARACEFREEPROPERTIESAND LOGICCOMPOSITION RULESIn this section the racefree properties of the NORA techniquewill be carefullybine dynamic,analyzed.conventional,L@ccompositionrules to com-and C2MOS functionblocks willalso be derived.A. InternalDe.Lzy Racefree PropertyThe internal delay racefree property is defined as the capability of the dynamic block to keep its preckarge signal duringby the inputs.Such a situationis indicatedtype and a p-type dynamic block.As indicated in Fig, 7, the alterationis controlledoutputsin Fig. 7 for an n-of the output informationby only one of the phases or . Therefore, theseare not influencedby the other phase.The outputsare, for instance, completely immune to the overlap of thephases. This kind of output latch ontrolby only one phase ( or ) is completely different from the conventional case withtransmission gates, where the output latch is controlled simultaneously by the two phases and . In contrast to thethe delay time of the previous blocks to set up the internalcriticalinputs.internaloccur ;sion gates (few nanoseconds), the NORA techniqueno restriction to the amount of clock skew.It is easy to prove that a dynamic block will have thedelay racefree property if the followingconditionsNote:clock skew specificationAlthoughof the conventionaltransmisimposesthe NORA circuit is immune to the overlap

IEEE264 -SECTION\VDDN2 – ‘i1 -SECTIONOF IVOL.\ONSC-18,NO.13-s cT,oN\3, JUNE*-sccT,oN1983\VDDr - N, ,10 ,1,‘1, , . @’-@Q &4 Fig. 7. Prechargeracefree–precharge‘2signal alteredn-typeFig. 9. Inputby the inputs:variationracefree–sequenceof dynamiccharge signals kept by the inputs:o 1-- impossible*bN2:withpre-p-typen-typeNl: 1– 0blocksNl:O–-1T@.(j0– 1N2:T 11– 0NX.1O ro l impossible*hNY:\VDDVDDI\ -SECTIONVDDI NXT-SECTION’VDD@by theximpossible*.hNY:1– 0T 1\SECTIONVDDvDDEVENFig. 8, Input variation racefree–precharge signal keptg o0– ’1T@.o0– 1.[@SECTIONp-type@ O-impossible”.INVERSIONSinputs,Fig.10. Inputvariationracefree–eveninversionslatch stages:betweentwo C 2MOSof the clock phases, there could still be signal races for clocksignals withvery slow rise and fall times (1 O to 20 times thegate delay).In contrast to the clock overlap race this kind ofrace is easily eliminatedsince it does not require control“ 1“ modificationN1:1– Oof theVariation RacefieeThe other possible case, i.e, when the dynamicthe precharge signal, is illustrated in Fig. 8.If the dynamiccontrolledshould be driven off.by an internalerates this inputblock keepsIf this transistor isinput, the dynamic block which gen-has also kept its precharge signal. This occursbecause the internalinputs are precharged in such a way thatthe corresponding driven transistors’ are off. Therefore, theremust be at least one sequence of dynamic blocks with prechargesignals preserved.impossible*Consider a NORAblock keeps the precharge signal, at least oneof the logic transistor@ 1- Fig. 9 depicts this sequence. Again, as shownin Fig. 9, the alteration of the output informationis controlledby only one of the phases r#Ior T. Therefore, they are not influenced by the overlap of the phases.For the case being analyzed, the racefree property has beenI Nl:O- modification1 r O impossible*.rNx:O-”l[@’r’Nx:’-clock skew and, also, the available time margin is much larger.Case II–Inputr“O”ventional,pipelinedsection, built with dynamic,and C2MOS functionof functionblocksC2MOS inputof thisblocks.pipelinedcon-Consider all the chainssection,startingin astage (C2 MOS latch stage of the previous pipe-lined section) and ending in a C2MOS output latch stage. TheNORApipelinedthe followingsection is clock racefree if, for every chain,conditionsare satisfied:1) Precharge racefree:a) There is an even number of inversions between theC2 MOS output stage and the last dynamic block (see Fig. 11).2) Input variation racefree:bl ) There is a dynamic block in such a way that there isderived from the interelationbetween a dynamic CMOS blockAnd a C’ MOS latch stage. Let us now show that the input vari-an even number of inversions between this dynamic block andthe C2 MOS input stage (see Fig. 12); orb2) the total number of inversions between the two (input,ation racefree propertyoutput)can also be derived by the action oftwo C2MOS stages: “A NORA pipelined circuit is input variation racefree if the total number of inversions (static anddynamic)between two C2MOS latch stages is even.”The proofis indicated in Fig. 10. This racefree property can also be usedto solve the clock race condition of some conventional CMOScircuits. An important circuit which can be built using the aboveproperty is the shift register.Combiningfunctionsthe racefree propertiesderived from two C2MOSand from C2MOS with dynamic block, the followingresult can be proven.C* MOS stages is even (see Fig. 10).If the pipelined section does not satisfy the clock race conditions, generally, circuit modificationscan be easily included.By way of example, consider the nonracefreepipelinedsectionindicated in Fig. 13(a). For this example, the following circuitmodificationswould eliminate the race condition:1) conversion of one static function to dynamic function[see Fig. 13(b)] ;2) conversionof one staticfunction[see Fig. 13(c)] ;3) placement of one static functionto C 2MOS functionafter the C2MOS latch

GONCP,LVES AND DE. MAN: NORA: RACEFREE DYNAMIC CMOS TECHNIQUEJ-SECTION’ -VDD\SECTIONVDDVDD265VDDg j ;g”’[pEVENFig. ons betweenstage and the last dynamic block.Fig. 14.the C2MOSCharge redistributionin dynamicVnn.--VDD T‘- 1 &-D-@@i.J4kZIrr –lp1,ILLOUT LJn-Ch4,-VDDHIGHs! ZFig. 15. Dynamic CMOS for low operating frequency.EvENINVERSIONSFig. 12, Input variation racefree–even inversions between the C2MOSinput stageand one dynamic block.pear between the outputcapacitance and the parasitic logic treecapacitances.Normally, there will be no charge redistribution -J-SECTION’\SECTIONVDDVDDinputs.‘a) r&&4( -&SECTION’between theprecharged node and the lo c tree nodes controlledSECTIONby sectionThis occurs because these inputs are set up during theprecharge phase and, therefore, the logic tree nodes will alsobe precharged.Yet, some charge redistributioneffect willexist, if the precharge periodafter inputset up is too small.This extra period of precharge generally does not result in spepd‘limitationfor the pipelkedsystem duq to the small capacitances of the logic trees.For the internal inputs, such attenuation of the charge redistribution@&SECTION’\SECTIONVDDVDDmust be minimizedVDDment.& & -g-,.)does not exist, since these inputs are set up only afterIn this case, the charge redistributionthe precharge period.by layout and by proper logic tree arrange-The transistors driven by internal inputs must be placedas far as possible from the outputstorage node.B. Leahzrge and Noise Margin -&3ECTION’Another\SECTIONlimitationof the dynamicCMOS techniques is theleakage of the storage nodes. Due to clock feedthrough, powersupply variation, noise, etc., the inputs of the dynamic blockvDDVDDcan be altered from the ideal zero and. VDD values. Consequently, the logi

Iineal circuits, the proposed technique imposes no restriction to the amount of clock skew. The main building blocks of the NORA technique are dynamic CMOS and C2MOS logic functions. Static CMOS functions can ;also be employed. Logic composition rules to mix dynamic CMOS, C 2MOS, and conventional CMOS will be presented. Different from

Related Documents:

CMOS Digital Circuits Types of Digital Circuits Combinational . – Parallel Series – Series Parallel. 15 CMOS Logic NAND. 16 CMOS Logic NOR. 17 CMOS logic gates (a.k.a. Static CMOS) . nMOS and pMOS are not ideal switches – pMOS passes strong 1 , but degraded (weak) 0

8. n-CH Pass Transistors vs. CMOS X-Gates 9. n-CH Pass Transistors vs. CMOS X-Gates 10. Full Swing n-CH X-Gate Logic 11. Leakage Currents 12. Static CMOS Digital Latches 13. Static CMOS Digital Latches 14. Static CMOS Digital Latches 15. Static CMOS Digital Latches . Joseph A. Elias, PhD 2

SOI CMOS technology has been used to integrate analog circuits. In this section, SOI CMOS op amp is discussed. Then, the performance comparison of op amps using bulk and SOI CMOS technologies is presented. 3.1 Analysis on SOI CMOS Op amp Figure 5 shows an SOI CMOS single stage op amp with a symmetrical topology. This circuit has a good .

CMOS Setup Procedure for Dispense System CPU Board PN 2025-0121 CMOS Setup Procedure Use this procedure to set computer CMOS parameters for dispense system CPU board (PN 2025-0121) with CPU, memory, and fan. 1. Activate BIOS/CMOS Setup Utility (pg 1) 2. Preset CPU board (pg 2) 3. Computer CMOS Parameters (pg 2) 4. Save Changes (pg 5) Revision .

Circuits-A CMOS VLSI Design Slide 2 Outline: Circuits Lecture A – Physics 101 – Semiconductors for Dummies – CMOS Transistors for logic designers Lecture B – NMOS Logic – CMOS Inverter and NAND Gate Operation – CMOS Gate Design – Adders – Multipliers Lecture C – P

High-Speed CMOS Characteristics Table 1 compares the main characteristics of the high-speed CMOS family with those of standard TTL, LS, S, ALS, AS, and metal-gate CMOS. Table 1. Performance Comparison of High-Speed CMOS With Several Other Logic Families TECHNOLOGY† SILICON-GATE CMOS AHC METAL-GATE

The Mock CMOS process is shown in Figure 2. Using just a metal and oxide film stack on a silicon wafer, one is able to create similar microstructures as those produced in the CMOS-MEMS process, following equivalent post-CMOS fabrication steps. Yet by removing the CMOS component, a designer can place more focus on the

The Leaving Certificate Russian syllabus is set out in the context of a common syllabus framework for the teaching and examining of French, German, Spanish and Italian. The syllabus is "communicative" in the sense that it is based on the purposes to which learners are likely to want, need or expect to put the knowledge and skills they acquire in class to use, and in the sense that the .