Snap-3D: A Constrained Placement- Driven Physical Design .

Snap-3D: A Constrained PlacementDriven Physical Design Methodologyfor Face-to-Face-Bonded 3D ICsPruek Vanna-iampikul, Chengjia Shao, Yi-Chen Lu,Sai Pentapati, and Sung Kyu LimGeorgia Institute of Technology

Contents Pseudo-3D vs. True-3D physical design flows Snap-3D flow– Overview– Details– Strengths Experimental Results Conclusions2/16

Heterogenous Integration Technologies2.5D interposermicro bumpingTSMC CoWoSIntel Foverosmonolithic 3Dhybrid bondingcoming soonTSMC SoIC, Samsung X-cube3/16

Pseudo-3D vs. True-3D EDA Toolscircuit4/161true-3Dplace/route2commercial tool NOT e 2D (commercial tool READY)final 3D

Snap-3D: Overview5/16

Snap-3D: Design Flow Goal– Use EDA vendor tools as much as possible– Then add key missing engines and seamlessly integrate6/16

Our Automatic Tier Partitioner7/16 Bin-based hypergraph partitioning– Divide 2D into bins, and partition each bin– Bi-partitioning engine is Fiduccia-Matheyses algorithm [1982]intermediate 2Dhypergraph modelbucket sorting of “gain”Why binning? Bin size determines F2F usage!

Snap-3D: Key Benefit (1/2)8/16 Commercial placement quality– 2D placement preserved in 3D placement!aabb cdSnap-3D placementcdtop tier placementbottom tier placement

Snap-3D: Key Benefit (2/2)9/16 Commercial routingquality– We route both tierssimultaneously withdouble metal stack– This allows metal layersharing!connecting cellsin the bottom tierconnecting cellsin the top tier!!!M5 BottomM6 Bottom

Snap-3D: Placement Sample10/16

Handling Memory Macros Memory macros are used in processor designs– Mostly placed manually: become placement blockages in Snap-3D– If both tiers are blocked: gate placement not allowed– If one tier is blocked: corresponding rows are not used11/16

Full-Chip GDS Layouts12/16 Snap-3D using TSMC 28nm– Not just placement: does routing, timing closure, and PPA simulations– High-quality layouts: OUTPERFORMS COMMECIAL 2D PPACortex A53 2D vs. 3DTATE 2D vs. 3DCortex A7 2D vs. 3DAES 128 2D vs. 3DRocketCore 2D vs. 3DLDPC 2D vs. 3D

A53 Full-Chip PPA13/162DInnovusShrunk2D [2]target freq (GHz)footprint (mm2)Compact2D [3]Snap-3Dsame1.00.50.50.5-1.01.011.15wirelength (m)1.00.690.700.73power (mW)1.00.670.660.67WNS (ns)1.00.571.120.33power delay2.101.121.460.97# F2F padsInnovus 2D full-chip GDS, A53Snap-3D full-chip GDS, A53

A53 Memory Latency/Energy Shorter WL in 3D– Helps reduce memoryaccess latency and power!metric14/162D3D3D gainEnergy/cycle (pJ)3.732.5730.8Input latency (max, ps)2092023.4Input latency (ave, ps)704437.1Output latency (max, ps)27212554.0Output latency (ave, ps)572850.9

Clock Comparison : AES @ 28nm2DInnovusShrunk2D [2]Compact2D [3]Snap-3D211.8181.5177.6166.1Clock Skew (ps)9.911.711.38.5Clock WL. (mm)43.4242.1541.3338.99# Clk. F2F pads0674671731875910849862Clock MetricsClock Latency (ps)# Clock Bufferclock tree for AES, 2D Innovusclock tree for AES, Snap-3D15/16

Conclusions Snap-3D key ideas– Use half heights (for cells and rows)– Do tier partitioning first and snap cells to rows ( constrained placement)– Use double metal stack for routing Snap-3D key benefits– 2D placement 3D placement– Metal layer borrowing is supported– Outperforms Innovus 2D, Shrunk-2D [2] and Compact-2D [3]16/16

Snap-3D key ideas – Use half heights (for cells and rows) – Do tier partitioning first and snap cells to rows ( constrained placement) – Use double metal stack for routing Snap-3D key benefits – 2D placement 3D placement – Metal layer borrowing is supported – Outperforms Innovus 2D, Shrunk-2D [2] and Compact-2D [3 .