The Design And Implemen - CECS

The Design and Implementation of PowerMill3yCharlie X. HuangyBill ZhangAbstractIn this paper we discuss the design and implementation of the simulator PowerMill, a novel transistorlevel simulator for the simulation of current and powerbehavior in vlsi circuits. With a new transistor modeling technology and a versatile event driven simulation algorithm, PowerMill is capable of simulatingdetailed current behavior in modern deep-submicroncmos circuits, including sophisticated circuitries suchas exclusive-or gates and sense-ampli ers, with speedand capacity approaching conventional gate level simulators. The high accuracy and speed have made itpossible for designers to study and verify detailed current behavior of large functional blocks or even an entire chip with a reasonable amount of CPU resources,making it a de facto industry standard for power simulation.1IntroductionHigher integration density, smaller device geometry, larger chip size, faster clock frequency, and thedemand low power consumption have made powerrelated issues increasingly critical in vlsi circuits [1,2]. For battery-operated devices, such as those inportable and hand-held applications, achieving minimum power consumption is usually the primary designgoal. Controlling power consumption is also becoming an important design goal in designs that aren'tbattery-operated. This is because the excessive heatgenerated from high power consumption can seriouslydegrade chip performance and cause physical damageto the chip. It may also lead to increased packagingcost, which is a major cost factor for IC's. Electronmigration in metal lines and vias [3], due to high currentdensities, gives rise to chip failures in the eld. Unusually high current spikes can lead to signi cant voltage uctuations, both resistive and inductive, if thepower distribution network is not properly designed.Such uctuations in turn can lead to a wide varietyof problems, from unintended logic transitions due tothe lowered noise margin, to the slow down in localizedportions of a circuit which will often cause timingerrors as the e ective supply voltage is reduced.As process and design technology advance to makeIC's larger and faster, these problems will only becomeworse. Unfortunately, many of them are transient innature, and depend critically on the physical charac3 PowerMill isa trademark of EPIC Design Technology, Inc.Some sub ject matters in this paper are covered by one or morepending U.S. patents.y EPIC Design Technology Inc., Santa Clara,z ITT-Intermetall, Freiburg, GermanyCA, U.S.A.yAn-Chang DengzBurkhard Swirskiteristics of an IC, which will not become available untilvery late in the design cycle. Some of them, such aselectronmigration, will not manifest themselves untilafter extended use in the eld. It is clear that ane ective and e cient analysis tool is needed to helpdesigners address these problems.2Existing approachesProbabilistic approach [4, 5, 6, 7] for the estimation of power consumption has attracted a lot of attention. Instead of simulating a circuit, this approachcomputes and propagates the probability for a nodeto change its logic state. Since it doesn't require alengthy vector set, it can be quite fast. Nevertheless,its scope is con ned, to a large extent, to the powerconsumption arising from the dynamic charging anddischarging of capacitors. While it can be argued thatthis is generally the dominant component for powerconsumption in logic circuits, its dominance for memory circuits, nmos design, and non-digital circuits isquestionable at best.The idea to compute power consumption based onlogic changes on nodes is also used in another classof power simulators, which works by keeping track ofnode toggles using existing gate level or switch levelsimulators [8]. It su ers from the same limitationas the probabilistic approach in that non-capacitivepower consumption is generally ignored. Although recent re nements have attempted to approximate someshort-circuit power consumption, due to nite rise/falltimes, such approximations are usually pre-built intoa gate level library and is limited to some very speci cdesign styles, and usually cannot handle full customdesigns and memory designs.3PowerMill's approachEPIC Design Technology's PowerMill is a highlyaccurate and e cient transistor level simulator. Being a transistor level tool, it is capable of handling thefull spectrum of digital mos circuits and many analogcircuits. Its novel piecewise linear transistor modelmodel captures transistor characteristics in a table,which provides high accuracy with minimum modelevaluation overhead. A unique event driven algorithmis employed to exploit circuit latency to achieve aspeed and capacity level approaching that of logic simulators. Furthermore, in contrast to most switch andgate level simulators, events are determined in terms ofsmall voltage changes, as opposed to logic transitions,making it possible to handle non-digital behaviors inan accurate manner.

3.1Piecewise linear modelingMost timing simulators [9] use the resistor modelto model transistors. In this model, a transistor isconverted into a resistor, in series with a switch, between the drain and source terminals. The switch isclosed if the logic state of the gate terminal is high/lowfor an nmos/pmos transistor, and opened otherwise(Figure 1.) The value of the resistor is typically set tothat which yields the same delay charging/discharginga capacitor, from zero to V dd, as would the transistor.Some more sophisticated tools also use the slew rateof the gate terminal to modify the resistance.While this type of approach o ers the maximum efciency, compared to a full-blown spice-like analyticalmodel, it is not capable of providing the require generality and accuracy that we had in mind. In designswith tight feedbacks, such as latches, memory cells,and typical domino logic gates, and in cases when thevoltage waveforms of the terminals deviate too muchfrom begin a line trajectory between 0 and V dd, thismodel simply cannot provide satisfactory accuracy.To get the requisite generality and accuracy, we decided to revert to the companion models used by circuit simulators. In such a model, a transistor is represented as a current source, a transconductor, and aresistor, the values of them dependent on the voltageson all three terminals (Figure 2). Mathematically, thismodel is arrived at by expanding a nonlinear devicemodel equation into a Taylor series near the operating point (vgs0 ; vds0 ), which is in turn truncated intoa linear equation:ids f (vgs ; vds ) i0 @v@f jvds vds0 (vgs 0 vgs0 )gs@f j(vds 0 vds0 ):@vds vgs vgs0This approximation is always valid for a continuousfunction, and accurate within the neighborhood of theoperating point. The only di erence between spiceand PowerMill is that, in spice, model equations andpartial derivatives are expressed in terms of complicated analytical equations, and must evaluated whenever the operating point changes, and in PowerMillthey are and precomputed and stored in table formsthat can be quickly looked up. The loss of accuracybecause of this approximation is very small, yet thegain in e ciency is tremendous. This is borne outby the fact that model evaluation accounts for a verysmall portion of the total cpu time. The generality ofthe model has allowed the use PowerMill on deep submicron designs without appreciable loss of accuracy.The variable vgs in the discussion above should really have been vgseffective , which is the di erence between the gate voltage and the source voltage, less thethreshold voltage vth . For any transistors that do nothave have their source terminal connected to ground orV dd, the value of vth is a nonlinear function dependentprimarily on vsb vs 0 vbulk . The rather signi cantvariation of vth with respect to vsb leads us to comple-ment our model with a nonlinear vth model. Again,to expedite simulation, this nonlinearity is modeled intable.The companion model in Figure 2 and the nonlinear vth model are the primary d.c. componentsin our transistor model. To complete the model, weneed also the capacitors, which are generally nonlinear. We chose to rely on a constant capacitance modelfor the gate, the overlap, the source/drain di usionarea, and the sidewall of the source/drain di usion.It has been our experience that this simplistic modelprovides enough accuracy in real designs, where layoutparasitics dominate and mask the nonlinearity in thecapacitance. As a backup measure, nonlinear modelsare also available for the di usions, and the gate. Gatecapacitance can even be distributed over source anddrain terminals depending on the operating region ofthe transistor [11, page 98].To make the simulator practical and useful, we havealso developed a utility program that will convert avariety of spice models into the table. This utilityprogram works by generating test structures in spiceformat, running spice, and extracting the pertinentinformation from spice runs. By customizing the generation of spice netlist and the interpretation of spiceresults, user can e ectively convert any spice modelsinto our piecewise linear model, without requiring ourutility program to understand the complicated analytical or empirical spice models at all.3.2Event driven approach3.3Transient simulationPowerMill's table lookup model o ers a general, accurate, and e cient way to model a transistor. Modelcomputation, however, is not the only cause for theslow run time and excessive memory usage in circuit simulators. For PowerMill to simulate designswith hundred of thousands of transistors in a coupleof hours using an ordinary workstation, event-driventechniques [12, 10, 13], which decouple a large circuitinto collections of smaller ones that can be handledseparately, must also be used.Unlike digital simulators and conventional timingsimulators, in which events are de ned as logic transitions, events in PowerMill are associated with a \signi cant" change in voltage level as in [14].The processing of events is fairly conventional.Events are sorted using a wrapped-around array acting as an \event-wheel" [9]. By keeping track of andsimulating the active portions of a circuit, the spatialand temporal latencies are naturally exploited.The processing of an event involves the evaluation,or a transient simulation, of the channel connectedcomponent [9] in which the node resides.The evaluation of a channel connected component isaccomplished using numerical integration techniquesthat are generally consistent with ordinary circuit simulators. In contrast to circuit simulation, however, weuse the one-step-relaxation method (osr) [15]. Sizesof time steps are carefully controlled to bound theamount of change in node voltages from one time pointto the next. This bound ensures the validity of osr,which is critical to maintain the accuracy of the result.