Chap. 5 Basic Computer Org. And Design

Chap. 5 Basic Computer Org. and Design 5-15-1 Instruction Codes The user of a computer can control the process by means of a program. A program is a set of instructions that specify the operations, operand, and InstructionCycle the sequence (control)A instruction is a binary code that specifies a sequence of microoperationsInstruction codes together with data are stored in memory ( Stored ProgramConcept)The computer reads each instruction from memory and places it in acontrol register. The control then interprets the binary code of theinstruction and proceeds to execute it by issuing a sequence ofmicrooperations.Instruction Code :zzA group of bits that instruct the computer to perform a specific operationIt is usually divided into parts(refer to Fig. 5-1 instruction format) Instruction Format1512 110 Operation Code :Addressz The most basic part of an instruction code Op. Codez A group of bits that define such operations as add, subtract, multiply, shift, andcomplement(bit 12-15 : 24 16 가지 distinct operations)Computer System ArchitectureChap. 5 Basic Computer Organization and Design Korea Univ. of Tech. & Edu.Dept. of Info. & Comm.

5-2 Stored Program Organization : Fig. 5-1z The simplest way to organize a computer» One processor register : AC (Accumulator) The operation is performed with the memory operand and the content of AC» Instruction code format with two parts : Op. Code AddressExam)Clear AC, Increment AC,Complement AC, . Op. Code : specify 16 possible operations (4 bit)Address : specify the address of an operand (12 bit)If an operation in an instruction code does not need an operand from memory, the rest of thebits in the instruction(address field) can be used for other purpose (따라서 16개 이상의instruction을 사용 : Tab. 5-2 참고, 총 25 개 instruction)» Memory : 12 bit 4096 word(Instruction and Data are stored) Store each instruction code(program) and operand (data) in 16-bit memory word Addressing Modez Immediate operand :» the second part of an instruction code(address field) specifies an operandzDirect address operand : Fig. 5-2(b)» the second part of an instruction code specifies the address of an operandzI 0 : Direct,I 1 : IndirectIndirect address operand : Fig. 5-2(c)» the bits in the second part of the instruction designate an address of a memory wordin which the address of the operand is found (Pointer로 사용됨)zOne bit of the instruction code is used to distinguish between a direct and anindirect address : Fig. 5-2(a)Computer System ArchitectureChap. 5 Basic Computer Organization and Design Korea Univ. of Tech. & Edu.Dept. of Info. & Comm.

5-3 Effective Addressz The operand address in computation-type instruction or the target address in abranch-type instruction 5-2 Computer Registers List of Registers for the Basic Computer : Tab. 5-1 Basic computer registers and memory : Fig. 5-3z Data Register(DR) : hold the operand(Data) read from memoryz Accumulator Register(AC) : general purpose processing registerz Instruction Register(IR) : hold the instruction read from memoryz Temporary Register(TR) : hold a temporary data during processingz Address Register(AR) : hold a memory address, 12 bit widthz Program Counter(PC) :» hold the address of the next instruction to be read from memory after the currentinstruction is executed» Instruction words are read and executed in sequence unless a branch instruction isencountered» A branch instruction calls for a transfer to a nonconsecutive instruction in the program» The address part of a branch instruction is transferred to PC to become the address ofthe next instruction» To read instruction, memory read cycle is initiated, and PC is incremented by one (nextinstruction fetch)Computer System ArchitectureChap. 5 Basic Computer Organization and Design Korea Univ. of Tech. & Edu.Dept. of Info. & Comm.

5-4zzInput Register(INPR) : receive an 8-bit character from an input deviceOutput Register(OUTR) : hold an 8-bit character for an output device Common Bus Systemz The basic computer has eight registers, a memory unit, and a control unit(in Sec.5-4)z Paths must be provided to transfer information from one register to another andbetween memory and registersz A more efficient scheme for transferring information in a system with manyregisters is to use a common bus(in Sec. 4-3)z The connection of the registers and memory of the basic computer to a commonbus system : Fig. 5-4» The outputs of 8 registers and memory are connected to the common bus» The specific output is selected by mux (S0, S1, S2) : Memory (7), AR (1), PC (2), DR (3), AC (4), IR (5), TR (6)외부 Device와의 입출력은 AC를 통해서 가능하기 때문에 INPR과 OUTR은 선택 없음mux가 선택되어지면 memory 또는 register로 부터 데이터가 출력되어 bus위에 놓여진다When LD (Load Input) is enable, the particular register receives the data from the bus» Control Input : LD, INC, CLR, Write, Read» Address Register : 별도의 Address bus 불필요 (하나의 Bus로 address와 data 동시처리) Computer System ArchitectureAC는 DR을 통해서만 memory read 가능(p. 146, LDA 명령 참조)Memory write는 AC의 내용을 직접 write 가능(p. 147, STA 명령 참조)Chap. 5 Basic Computer Organization and Design Korea Univ. of Tech. & Edu.Dept. of Info. & Comm.

5-5» Accumulator(AC) : 3 종류의 입력 Path s2s1s01) Register Microoperation : clear AC, shfiftAC, Memory unit4096 16Write2) Data Register : add DR to AC, and DR toAC(연산결과는 AC에 저장하고 결과에 따라End carry bit set/reset), memory READ(DR을 통해서만 가능)LDLDD2T5 : AC DR, SC 0CLR2INRCLRDR3) INPR : 외부 Device에서 데이터입력(Adder & Logic을 거치지 않아도 됨)AdderandlogicINR3CLREACLD» Note) Two microoperations can be executedat the same timeINR4CLRINPRDR AC : s2 s1s0 100(4), DR (load )AC DR : DR Adder & Logic AC (load )INR1PCLD7ReadARD2T4 : DR M [ AR ] AddressBusIR5TR6LDLDINRCLROUTRLDClock16-bit common busFig. 5-4 Basic computer registers connected to a common busComputer System ArchitectureChap. 5 Basic Computer Organization and Design Korea Univ. of Tech. & Edu.Dept. of Info. & Comm.

5-6 5-3 Computer Instruction 3 Instruction Code Formats : Fig. 5-5z Memory-reference instruction» Opcode 000 110I 0 : 0xxx 6xxx, I 1: 8xxx Exxx I 0 : Direct,I 1 : Indirect15 14Iz12 11Opcode0AddressRegister-reference instruction» 7xxx (7800 7001) : CLA, CMA, .15 140z112 11110Register OperationInput-Output instruction» Fxxx(F800 F040) : INP, OUT, ION, SKI, .15 1411Computer System Architecture12 NCSPASNASZASZEHLTINPOUTSKISKOIONIOFHex CodeI 0 I 10xxx 8xxx1xxx 9xxx2xxx Axxx3xxx Bxxx4xxx Cxxx5xxx Dxxx6xxx 01F800F400F200F100F080F040DescriptionAnd memory word to ACAdd memory word to ACLoad memory word to ACStore content of AC in memoryBranch unconditionallyBranch and Save return addressIncrement and skip if zeroClear ACClear EComplement ACCompmeCirculate right AC and ECirculate left AC and EIncrement ACSkip next instruction if AC positiveSkip next instruction if AC negativeSkip next instruction if AC zeroSkip next instruction if E is 0Halt computerInput character to ACOutput character from ACSkip on input flagSkip on output flagInterrupInter0I/O OperationChap. 5 Basic Computer Organization and Design Korea Univ. of Tech. & Edu.Dept. of Info. & Comm.

5-7If the computer includes a sufficient number of Instruction Set Completenessinstructions in each of the following categoriesz Arithmetic, Logical, and shift : CMA, INC, .z Moving information to and from memory and AC : STA, LDAz Program control : BUN, BSA, ISZz Input/Output : INP, OUT 5-4 Timing and Control Clock pulsesz A master clock generator controls the timing for all registers in the basic computerz The clock pulses are applied to all F/Fs and registers in systemz The clock pulses do not change the state of a register unless the register isenabled by a control signalz The control signals are generated in the control unit : Fig. 5-6» The control signals provide control inputs for the multiplexers in the common bus,control inputs in processor registers, and microoperations for the accumulator Two major types of control organizationz Hardwired Control : Chap. 5» The control logic is implemented with gates, F/Fs, decoders, and other digital circuits» Fast operation, - Wiring change(if the design has to be modified)Computer System ArchitectureChap. 5 Basic Computer Organization and Design Korea Univ. of Tech. & Edu.Dept. of Info. & Comm.

5-8zMicroprogrammed Control : Chap. 7» The control information is stored in a control memory, and the control memory isprogrammed to initiate the required sequence of microoperations» Any required change can be done by updating the microprogram in control memory,- Slow operationInstruction register (IR)zTiming Signal 4 X 16 Decoder 4-bit Sequence Counter11 - 03 8decoder7 6 5 4 3 2 1 0IMemory R/W cycle time Clockcycle time» 만약 위와 같이 가정하지 않으면, waitcycle을 추가해야 함.Computer System ArchitectureOther inputsD0.D7 .Exam) Control timing : Fig. 5-7» Sequence Counter is cleared whenD3T4 1 : D3T4 : SC 0z12ControllogicgatesControloutputsT15T0.zControl Unit Control Logic Gate 3 X 8 Decoder Instruction Register Timing Signal1315 14.z14. Control Unit : Fig. 5-615104 ar(CLR)ClockChap. 5 Basic Computer Organization and Design Korea Univ. of Tech. & Edu.Dept. of Info. & Comm.

5-9 Exam) Register transfer statement : T0 : AR PCz A transfer of the content of PC into AR if timing signal T0 is active » 1) During T0 active, the content of PC is placed onto the bus ( S2 S1S0 )» 2) LD(load) input of AR is enabled, the actual transfer occurs at the next positivetransition of the clock(T0 rising edge clock)T0 : Inactive» 3) SC(sequence counter) is incremented : 0000(T0 ) 0001(T1 )T1 : Active5-5 Instruction Cycle Instruction Cyclez 1) Instruction Fetch from Memoryz 2) Instruction Decodez 3) Read Effective Address(if indirect addressing mode)z 4) Instruction Executionz 5) Go to step 1) : Next Instruction[PC 1]Continueindefinitelyunless HALTinstruction isencountered Instruction Fetch : T0, T1(Fig. 5-8)T0 : AR PCT1 : IR M [ AR ], PC PC 1zT0 1T0 : AR PC» 1) Place the content of PC onto the bus by making the bus selection inputs S2S1S0 010» 2) Transfer the content of the bus to AR by enabling the LD input of ARComputer System ArchitectureChap. 5 Basic Computer Organization and Design Korea Univ. of Tech. & Edu.Dept. of Info. & Comm.

5-10zT1 1»»»»T1 : IR M [ AR ], PC PC 11) Enable the read input memory2) Place the content of memory onto the bus by making S2S1S0 1113) Transfer the content of the bus to IR by enable the LD input of IR4) Increment PC by enabling the INR input of PC Instruction Decode : T2T2 : D0 ,., D7 Decode IR (12 14), AR IR (0 11), I IR (15)Op.codeT1 1s2T0 1s1Address Di/Indirect7MemoryMemory unitunit Buss0IR(12-14)에 따라 Fig. 5-6 에서 D0 - D7 출력AddressRead Instruction Execution : T3, T4, T5, T6IR(12 14) 111Read effectiveRegister(I 0)D7I’T3(Execute)AddressI/O(I 1)D7IT3 (Execute)D7’IT3( AR M [ AR ] )D7 0 : Memory Ref. Indirect(I 1)Direct (I 0)nothing in T3 Register 와 I/O 명령은 T3에서 실행되며 Memory Ref.명령은 T3에서 Operand의 effective address를 읽음D7 1 Memory Ref. 명령은 종류에 따라 T4, T5, T6을 갖음 :Fig. 5-11 Flowchart for instruction cycle(InitialConfiguration) : Fig. 5-9Computer System ArchitectureChap. 5 Basic Computer Organization and DesignAR1PC2LDINR5IRLDClockCommon bus Korea Univ. of Tech. & Edu.Dept. of Info. & Comm.010111