Investigation Of Comparator Topologies And Their Usage In .

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Investigation of Comparator Topologiesand their Usage in a TechnologyIndependent Flash-ADC TestbedCand.-Ing. Öner B. ErginProf. Dr.-Ing. Klaus SolbachDepartment of Microwave and RF-TechnologyUniversity of Duisburg-EssenDipl.-Ing. Harald Bothe and Dipl.-Ing. Reimund WittmannNokia Research Center BochumProf. Dr.-Ing. Werner SchardeinUniversity of Applied Sciences and Arts Dortmund

Contents Introduction State-of-the-Art Analog-to-Digital Converters (ADCs) Flash ADC Comparators Comparator Selection Procedure Flash ADC Testbed Verification in 65 nm Technology Conclusion

Introduction: Generic Engineering Model Variety of process technologies increases Circuits have to be rebuilt for every process The Generic Engineering Model (GEM) ·Circuits are portable to all technologies·Automatical symbol, schematic, layout and testbench generation During this thesis, all circuits were developed using the GEM approach

Introduction: Selection methodology Selection methodology on top of GEM implementation allows parameterizablelayout solutions Main high level design constraints:· Power· Supply voltage· Area· Bit resolution· Speed (clock rate) Comparator topologies are investigated with respect to the above listed constraintsfor flash ADC implementation

Contents Introduction State-of-the-Art Analog-to-Digital Converters (ADCs) Flash ADC Comparators Comparator Selection Procedure Flash ADC Testbed Verification in 65 nm Technology Conclusion

State-of-the-Art ADCs ADCs are developed for high speed or high resolution High resolution and high speed leads to high die size (high costs andimplementation effort)

Contents Introduction State-of-the-Art Analog-to-Digital Converters (ADCs) Flash ADC Comparators Comparator Selection Procedure Flash ADC Testbed Verification in 65 nm Technology Conclusion

Flash ADC Fastest ADC structure 2N resistors , 2N-1 comparators,thermometer-code to binary encoder Single-ended or differential type (widerintensity range) Drawbacks (bit wise increase):· Area and power double approximately· Resistor matching becomes morecritical· Input bandwidth limited by increasinginput capacitance

Contents Introduction State-of-the-Art Analog-to-Digital Converters (ADCs) Flash ADC Comparators· Comparator Specifications· Latch-Type Topologies· SC-Type Topologies· Simulation Results in 65 nm Technology Comparator Selection Procedure Flash ADC Testbed Verification in 65 nm Technology Conclusion

Comparators: Specifications Widely used components, especially in ADCs Comparator as 1-bit ADC Important specifications for implementation in flash ADCs:·Bit resolution ( maximum bit resolution of flash ADC) ·Input common mode range (ICMR) ( maximum flash ADC approximation range) ·Speed ( maximum speed of flash ADC) ·Power ( minimum power dissipation of flash ADC (after division by the number ofcomparators)) No Sample & Hold block needed when clocked comparators are implemented e.g.··Latch-type comparatorsSC-type comparators

Contents Introduction State-of-the-Art Analog-to-Digital Converters (ADCs) Flash ADC Comparators· Comparator Specifications· Latch-Type Topologies· SC-Type Topologies· Simulation Results in 65 nm Technology Comparator Selection Procedure Flash ADC Testbed Verification in 65 nm Technology Conclusion

Comparators: Latch-Type TopologiesLatch-type topologiesDynamiclatched4-inputsClass AB latched2-inputs4-inputs4-inputsStatic latched·Principle: Positive-feedback circuit·Phases: regeneration (latch 0) and amplification·Advantages:·High and rapid amplification·Low area·Low power·Disadvantages:·Kickback noise is the main challenge (Charge transfer between the input and the positive-feedback circuitwhen the amplification phase is active) ·Mismatch and parasitic sensitivity are additional drawbacks·Output changes to opposed digital state in the regeneration phase·Solution: SR-Latch at the output

Comparators: Latch-Type: 2-inputs Dynamic LatchedLatch-type topologiesDynamiclatched4-inputs Class ABlatched2-inputs4-inputs High speed Low power Low area High parasitic sensitivity Limited ICMR4-inputs staticlatched

Comparators: Latch-Type: 4-inputs Class AB LatchedLatch-type topologiesDynamiclatched4-inputs Class ABlatched High speed Low power Low area Rail-to-rail ICMR Not equal resolutionat different references4-inputs staticlatched

Contents Introduction State-of-the-Art analog-to-digital converters (ADCs) Flash ADC Comparators· Comparator Specifications· Latch-Type Topologies· SC-Type Topologies· Simulation Results in 65 nm Technology Comparator Selection Procedure Flash ADC Testbed Verification in 65 nm Technology Conclusion

Comparators: SC-Type TopologiesSC-type age4-inputsOOS·Principle: Periodically sense and store the offset on capacitors·Phases: Offset cancellation, amplification and latch·A PMOS-input differential amplifier is used as the preamplifier·The latch part is represented by the 2-inputs dynamic latchedcomparator·Advantages High Resolution·Disadvantages High area High power

Comparators: SC-Type: 2-inputs IOSSC-type age·IOS: Input offset storage Rail-to-rail ICMR High resolution High area High power4-inputsOOS

Comparators: SC-Type: 4-inputs OOSSC-type topologies2-inputsIOS2-inputsOOS·OOS: Output offset storage Rail-to-rail ICMR High resolution High area High power4-inputsOOS

Contents Introduction State-of-the-Art Analog-to-Digital Converters (ADCs) Flash ADC Comparators· Comparator Specifications· Latch-Type Topologies· SC-Type Topologies· Simulation Results in 65 nm Technology Comparator Selection Procedure Flash ADC Testbed Verification in 65 nm Technology Conclusion

Comparators: Results: Area and ResolutionArea [µm²]500·Latch-type comparators450400·Low area350300·Parasitic sensitivity degrades 250200maximum resolution150100·SC-type comparators500·High areaClass AB latched layoutOOS 4in layout2-input dynamic latched layoutIOS layout·Less parasitic sensitivityResolution [bits] for layouted Comparators·Conclusion:10·Lower area leads to less area 987consumption60,811,2543210Class AB latched layout2-input dynamic latched layoutOOS 4in layoutIOS layout

Comparators: Results: Speed and PowerSpeed [MHz]2500200015000,811,2100050002-input dynamic latched layoutClass AB latchedStatic latched2-input dynamic latched4-input dynamic latchedClass AB latched layoutIOS layoutIOSOOS 2inMulti IOSOOS 4in layoutOOS 4inPower [µW] at 10 -input dynamic latched layoutClass AB latchedStatic latched2-input dynamic latched4-input dynamic latchedClass AB latched layoutIOS layoutIOSOOS 2inMulti IOSOOS 4in layoutOOS 4in

Contents Introduction State-of-the-Art Analog-to-Digital Converters (ADCs) Flash ADC Comparators Comparator Selection Procedure Flash ADC Testbed Verification in 65 nm Technology Conclusion

Comparator Selection ProcedureParametersTechnologyBit resolutionSpeedApproximation rangeSupply voltage2-inputs / 4-inputsComparator selectionroutineOutputRelevant topologiesArea consumptionsPower dissipationsFlash ADC testbed GEMFAT tree encoderwith single bubbleerror correction arrayGEMComparator GEMPoly resistorarray GEM

Contents Introduction State-of-the-Art Analog-to-Digital Converters (ADCs) Flash ADC Comparators Comparator Selection Procedur

State-of-the-Art analog-to-digital converters (ADCs) . 2-input dynamic latched layout Class AB latched layout IOS layout OOS 4in layout 0 50 100 150 200 250 300 350 400 450 500 Area [µm²] 2-input dynamic latched layout Class AB latched layout

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