RAO PAHALD SINGH GROUP OF INSTITUTIONS

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1DIGITAL ELECTRONICS LABORATORY (LC-EE-204)DIGITAL ELECTRONICS LABORATORY(LC-EE-204)LAB MANUALIV SEMESTERRAO PAHALD SINGH GROUP OF INSTITUTIONSBALANA(MOHINDER GARH)123029Department Of Electronics & Communication Engg.RPS CET ,Balana(M/Garh)

2DIGITAL ELECTRONICS LABORATORY (LC-EE-204)LIST OF tion to Digital Electronics lab-nomenclature of digitalICS , specifications ,study of the datasheet , concept of vcc andground, verification of the truth tables of logic gates using TTLICS.3-5Implementation of the given Boolean function using logicgates in both sop and pos forms.6-7To Study the Half Adder36-78-9To study about full adder & verify its observation data.4567891010-11To Design & Verify the Operation of Magnitude ComparatorImplementation of 4x1 Multiplexer and 1x4 Demultiplexer usingLogic GatesVerification of State Tables of Rs ,J-k ,T and D Flip-Flops usingNAND GatesDesign, and Verify the 4-Bit Serial In - Parallel Out ShiftRegisters.12-1314-1516-1819-20Design ,and Verify the 4-Bit Synchronous Counter21-23Design, and Verify the 4-Bit Asynchronous Counter.24

3DIGITAL ELECTRONICS LABORATORY (LC-EE-204)EXPERIMENT 1AIM: - Introduction to Digital Electronics Lab- Nomenclature of Digital Ics ,Specifications, Study of the Data Sheet, Concept of Vcc and Ground, Verification of theTruth Tables of Logic Gates using TTL Ics.THEORETICAL CONCEPT:AND Gate: The AND operation is defined as the output as (1) one if and only if all theinputs are (1) one. 7408 is the two Inputs AND gate IC.A&B are the Input terminals & Yis the Output terminal.Y A.BOR Gate: The OR operation is defined as the output as (1) one if one or more than 0inputs are (1) one. 7432 is the two Input OR gate IC. A&B are the input terminals & Y isthe Output terminal.Y A BNOT GATE: The NOT gate is also known as Inverter. It has one input (A) & oneoutput (Y). IC No. is 7404. Its logical equation is,Y A NOT B, Y A’NAND GATE: The IC no. for NAND gate is 7400. The NOT-AND operation is knownas NAND operation. If all inputs are 1 then output produced is 0. NAND gate is invertedAND gate.Y (A. B)’NOR GATE: The NOR gate has two or more input signals but only one output signal. IC7402 is two I/P IC. The NOT- OR operation is known as NOR operation. If all the inputsare 0 then the O/P is 1. NOR gate is inverted OR gate.Y (A B)’EX-OR GATE: The EX-OR gate can have two or more inputs but produce one output.7486 is two inputs IC. EX-OR gate is not a basic operation & can be performed usingbasic gates.Y ABEXPERIMENTAL SET UP :Logic Symbol of Gates

4DIGITAL ELECTRONICS LABORATORY (LC-EE-204)

5DIGITAL ELECTRONICS LABORATORY (LC-EE-204)SPECIFICATION OF APPARATIUS USED: Power Supply, Digital Trainer Kit.,Connecting Leads, IC’s (7400, 7402, 7404, 7408, 7432, and 7486)PROCEDURE:(a)Fix the IC’s on breadboard & gives the supply.(b)Connect the ve terminal of supply to pin14 & -ve to pin7.(c)Give input at pin1, 2 & take output from pin3.It is same for all except NOT &NOR IC.(d)For NOR, pin1 is output & pin2&3 are inputs.(e)For NOT, pin1 is input & pin2 is output.(f)Note the values of output for different combination of inputs & draw the cktPRECAUTIONS:1. Make the connections according to the IC pin diagram.2. The connections should be tight.3. The Vcc and ground should be applied carefully at the specified pin only.OBSERVATION DATA:INPUTSA’ A (A B)ABNOBO’NO00 ND1110(AB)ExOR0110RESULT AND COMMENTS: We have learn tall the gates ICs according to the IC pindiagram.

6DIGITAL ELECTRONICS LABORATORY (LC-EE-204)EXPERIMENT 2AIM: Implementation of the Given Boolean Function using Logic Gates in Both Sop andPos Forms.THEORETICAL CONCEPT:Karnaugh maps are the most extensively used tool for simplification of Booleanfunctions. It is mostly used for functions having up to six variables beyond which itbecomes very cumbersome. In an n-variable K-map there are 2ⁿ cells. Each cellcorresponds to one of the combination of n variable, since there are 2ⁿ combinations of nvariables.Gray code has been used for the identification of cells.Example- SOP:POS:EXPERIMENTAL SET UP:SOP formPOS FORMSPECIFICATION OF APPARATUS USED:- Power Supply, Digital Trainer, IC’s(7404, 7408,7432) Connecting leads.

7DIGITAL ELECTRONICS LABORATORY (LC-EE-204)PROCEDURE:(a) With given equation in SOP/POS forms first of all draw a Kmap.(b) Enter the values of the O/P variable in each cell corresponding to its Min/Max term.(c) Make group of adjacent ones.(d) From group write the minimized equation.(e) Design the ckt. of minimized equation & verify the truth table.PRECAUTIONS:1) Make the connections according to the IC pin diagram.2) The connections should be tight.3) The Vcc and ground should be applied carefully at the specified pin only.RESULT AND COMMENTS:-Implementation of SOP and POS form is obtainedwith AND and OR gates.

8DIGITAL ELECTRONICS LABORATORY (LC-EE-204)EXPERIMENT NO. 3AIM:-To Study the Half Adder.THEORETICAL CONCEPT:A half adder is a logic circuit that performs one-digit addition.The half adder is an example of a simple, functional digital circuit built from logicgates. The half adder adds to one-bit binary numbers (AB). The output is the sum of thetwo bits (S) and the carry (C).EXPERIMENTAL SET UP:-SPECIFICATION OF APPARATUS USED:- I.C’s 7486, 7408, wires, LED, BreadBoard, 5 Volt supply.PROCEDURE:1. Write OBSERVATION DATA for variables A, B. solves this OBSERVATIONDATA with the help of K-map.2. Connect the circuit as shown and get the output of Sum and Carry separately.3. Firstly, we will put IC’s.4. Take input from Pin no. 1&2 of IC no.7486 and take output at Pin no.3.5. Pin no.3 is connected with LED.6. Short Pin no.1 of IC no.7486 to Pin no.2 of IC no.7408.7. Similarly, short Pin no.1 of IC no.7486 to Pin no.1 of IC no.7408.8. Take output at Pin no.3 of IC no.7408 and connect to LED.9. Connect the Pin no. 14 to the 5 volt supply for all IC’s used in the circuit.10. Connect Pin no. 7 to ground for all the IC’s

9DIGITAL ELECTRONICS LABORATORY (LC-EE-204)PRECAUTIONS:1. Supply should not exceed 5v.2. Connections should be tight and easy to inspect.3. Use L.E.D. with proper sign convention and check it before connecting in circuit.OBSERVATION DATA:A1100B1010Sum0110Carry1000RESULT AND COMMENTS:- the observation data of half adder verified.

DIGITAL ELECTRONICS LABORATORY (LC-EE-204)EXPERIMENT NO. 4AIM:-To study about full adder & verify its observation data.THEORETICAL CONCEPT:-An half adder has only two inputs and there is no provision to add a carrycoming from the lower order bits when multibit addition is performed. For this purpose, a third inputterminal is added and this circuit is used to add An, Bn and Cn-1 where An and Bn are the nth order bitsof the numbers A and B respectively and Cn-1 is the carry generated from the addition of (n-1)th orderbits. This circuit is referred to as FULL-ADDER.EXPERIMENTAL SET 3A1274H151213U4A1274H151213U5A121 01SPECIFICATION OF APPARATUS USED:-IC-(7486,7408,7432),Connecting wires, LED, Breadboard,Cutter,5v supply.

11DIGITAL ELECTRONICS LABORATORY (LC-EE-204)PROCEDURE:1. Write the OBSERVATION DATA for variables An, Bn and Cn-1.2. OBSERVATION DATA was solved with the help of K-map.3. Circuit was connected and the outputs of sum and carry was got separately.4. Connect the pin no.14 to 5v supply of all IC’s used in circuit.5.Pin no. 7 will be grounded of all IC’s.PRECAUTIONS:1. Supply should not exceed 5v.2. Connections should be tight and easy to inspect.3. Use L.E.D. with proper sign convention and check it before connecting in circuitOBSERVATION 1010101010110100100010111RESULT AND COMMENTS:- the observation data of full adder is verified.

12DIGITAL ELECTRONICS LABORATORY (LC-EE-204)EXPERIMENT NO. 5AIM:-To Design & Verify the Operation of Magnitude ComparatorTHEORETICAL CONCEPT:- Comparator compares the value of signal at the input. Itcan be designed to compare many bits. The adjoining figure shows the block diagram ofcomparator. Here it receives to two 2-bit numbers at the input & the comparison is at theoutput.EXPERIMENTAL SET UP: - ComparatorSPECIFICATION OF APPARATUS USED:Power Supply , Digital Trainer Kit. Connecting Leads, and IC’s (7404, 7408, and7486).PROCEDURE:a.Make the connections according to the circuit diagram.b.The output is high if both the input sare equal.c.Verify the truth table for different values.PRECAUTIONS:1)Make the connections according to the IC pin diagram.2)The connections should be tight.3)The Vcc and ground should be applied carefully at the specified pin only

13DIGITAL ELECTRONICS LABORATORY (LC-EE-204)OBSERVATION DATA:InputsOutputsBAA BA BA B00010011001000111010RESULT AND COMMENTS:- The comparator is designed & verified.

14DIGITAL ELECTRONICS LABORATORY (LC-EE-204)EXPERIMENT NO : 6AIM:- Implementation of 4x1 Multiplexer and 1x4 Demultiplexer using Logic Gates.THEORETICAL CONCEPT:MULTIPLEXER: Multiplexer generally means many into one. A multiplexer is acircuit with many Inputs but only one output. By applying control signals we can steerany input to the output .The fig. (1) Shows the general idea. The ckt. has n-inputsignal,control signal & one output signal. Where 2n m. One of the popular multiplexeris the 4 to 1 multiplexer, which has 4 input bits, 2 control bits & 1 output bit.DEMULTIPLEXER: Demultiplexer means generally one into many. A demultiplexer isa logic circuit with one input and many outputs. By applying control signals, we can steerthe input signal to one of the output lines. The ckt. has one input signal, m control signaland n output signals. Where 2n m. It functions as an electronic switch to route anincoming data signal to one of several outputsEXPERIMENTAL SET UP: Multiplexer (4x1)Demultiplexer (1x4)SPECIFICATION OF APPARATUS USED:Power Supply, Digital Trainer, Connecting Leads, IC’s74153(4x1 multiplexer).

15DIGITAL ELECTRONICS LABORATORY (LC-EE-204)PROCEDURE:1) Connect the circuit as shown in figure.2) Apply Vcc & ground signal to every IC.3) Observe the input & output according to the truth table.PRECAUTIONS:1) Make the connections according to the IC pin diagram.2) The connections should be tight.3) The Vcc and ground should be applied carefully at the specified pin only.OBSERVATION DATA:Truth table for MuxTruth table for DemuxRESULT AND COMMENTS:Verify the truth table of multiplexer and demultiplexer for various inputs.

16DIGITAL ELECTRONICS LABORATORY (LC-EE-204)EXPERIMENT NO. 7AIM: Verification of State Tables of Rs ,J-k ,T and D Flip-Flops using NAND GatesTHEORETICAL CONCEPT: RS FLIP-FLOP: There are two inputs to the flip-flop defined as R and S . When I/PsR 0 and S 0 then O/P remains unchanged .When I/Ps R 0andS 1 the flip-flop isswitches to the stable state where O/P is 1i.e. SET. The I/P condition is R 1 and S 0 theflip-flop is switched to the stable state where O/P is 0i.e. RESET. The I/P condition isR 1 and S 1 the flip-flop is switched to the stable state where O/P is forbidden. JK FLIP-FLOP: For purpose of counting, the JK flip-flop is the ideal element to use.The variable J and K are called control I/Ps because they determine what the flip-flopdoes when a positive edge arrives. When J and K are both0s, both AND gates aredisabled and Q retain sits last value. D FLIP–FLOP: This kind of ransferredtotheoutputafteraclockpulseisreceived. T yofthesignaltotheTinput.It ENTAL SET UP: SRFlipFlopDFlipFlop

17DIGITAL ELECTRONICS LABORATORY (LC-EE-204)JK FLIP FLOPT FLIP FLOPSPECIFICATION OF APPARATUS USED:- IC’ S 7400, 7402 Digital Trainer &Connecting leads.PROCEDURE:1.Connect the circuit as shown in figure.2.Apply Vcc & ground signal to every IC.3.Observe the input & output according to the truth table.PRECAUTIONS:1)Make the connections according to the IC pin diagram.2)The connections should be tight.3)The Vcc and ground should be applied carefully at the specified pin onlyOBSERVATION DATA:TRUTHTABLE:SRFLIP FLOP:SR FLIP FLOP:CLOCK1111S0011R0101QNOCHANGE01?D FLIP FLOP:CLOCK11D01Q01JK FLIP FLOP:CLOCK1111J0011K0101QNOCHANGE01Q’

18DIGITAL ELECTRONICS LABORATORY (LC-EE-204)T FLIP FLOP:CLOCK11T01QNOCHANGEQ’RESULT AND COMMENT:-Truth table is verified on digital trainer.

19DIGITAL ELECTRONICS LABORATORY (LC-EE-204)EXPERIMENT NO. 8Aim: – Design, and Verify the 4-Bit Serial In - Parallel Out Shift Registers.THEORETICAL CONCEPT:-shift register is used to shift the data there 4 type of shiftregister: siso,sipo,piso,pipo. The difference is the way in which the data bits are taken outof the register. Once the data are stored, each bit appears on its respective output line, andall bits are available simultaneously. A construction of a four-bit serial in - parallel outregister is shown belowEXPERIMENTAL SET UP: -SPECIFICATION OF APPARATUS USED:- Digital trainer kit and 4 JK flip flopeach IC 7476 (i.e dual JK flip flop) and two AND gates IC 7408.OBSERVATION DATA:TRUTH TABLE:

20DIGITAL ELECTRONICS LABORATORY (LC-EE-204)PROCEDURE:a) Make the connections as per the logic diagram.b) Connect 5v and ground according to pin configuration.c) Apply diff combinations of inputs to the i/p terminals.d) Note o/p for summation.e) Verify the truth table.PRECAUTIONS:1. Make the connections according to the IC pin diagram.2. The connections should be tight.3. The Vcc and ground should be applied carefully at the specified pin only.RESULT AND COMMENT: 4-bit Serial In – Parallel Out Shift Registers studied andverified.

21DIGITAL ELECTRONICS LABORATORY (LC-EE-204)EXPERIMENTNO:9Aim:–Design ,and Verify the 4-Bit Synchronous CounterTHEORETICAL CONCEPT:Counter is a circuit which cycle through state sequence. Two types of counter,Synchronous counter(e.g. parallel) and Asynchronous counter(e.g. ripple). In Ripplecounter same flip-flop output to be used as clock signal source for other flip-flop.Synchronous counter use the same clock signal for all flip-flop.EXPERIMENTAL SET UP: -SPECIFICATION OF APPARATUS USED:- Digital trainer kit and 4 JK flip flopeach IC7476 (i.e dual JK flip flop)andtwoANDgatesIC7408.

22DIGITAL ELECTRONICS LABORATORY (LC-EE-204)OBSERVATION DATA:TRUTH TABLE

23DIGITAL ELECTRONICS LABORATORY (LC-EE-204)PROCEDURE:a) Make the connections as per the logic diagram.b) Connect 5v and ground according to pin configuration.c) Apply diff combinations of inputs to the i/p terminals.d) Note o/p for summation.e) Verify the truth table.PRECAUTIONS:1. Make the connections according to the IC pin diagram.2. The connections should be tight.3. The Vcc and ground should be applied carefully at the specified pin only.RESULT AND COMMENT: 4-bit synchronous counter studied and verified.

24DIGITAL ELECTRONICS LABORATORY (LC-EE-204)EXPERIMENT NO: 10Aim: – Design, and Verify the 4-Bit Asynchronous Counter.THEORETICAL CONCEPT:-Counter is a circuit which cycle through state sequence.Two types of counter, Synchronous counter (e.g. parallel) and Asynchronous counter(e.g. ripple). In Ripple counter same flip-flop output to be used as clock signal source forother flip-flop. Synchronous counter use the same clock signal for all flip-flop.EXPERIMENTAL SET UP: -4-Bit Asynchronous counterSPECIFICATION OF APPARATUS USED:- Digital trainer kit and 4 JK flip flopeach IC 7476 (i.e dual JK flip flop) and two AND gates IC 7408.PROCEDURE:a) Make the connections as per the logic diagram.b) Connect 5v and ground according to pin configuration.c) Apply diff combinations of inputs to the i/p terminals.d) Note o/p for summation.e) Verify the truth table.PRECAUTIONS:1. Make the connections according to the IC pin diagram.2. The connections should be tight.3. The Vcc and ground should be applied carefully at the specified pin only.RESULT AND COMMENT: 4-bit asynchronous counter studied and verified.

To Study the Half Adder 6-7 3 8-9 To study about full adder & verify its observation data 4 . 10-11 5 To Design & Verify the Operation of Magnitude Comparator 12-13 6 Implementation of 4x1 Multiplexer and 1x4 Demultiplexer using Logic Gates 14-15 7 Verification of State Tables of Rs ,J-k ,T and D Flip-Flops using NAND Gates 16-18 8

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