Latches, The D Flip-Flop & Counter Design
Latches, the D Flip-Flop &Counter DesignECE 152A – Winter 2012
Reading Assignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a SimpleProcessor 7.1 Basic Latch7.2 Gated SR Latch 7.3 Gated D Latch February 6, 20127.2.1 Gated SR Latch with NAND Gates7.3.1 Effects of Propagation DelaysECE 152A - Digital Design Principles2
Reading Assignment Brown and Vranesic (cont) 7 Flip-Flops, Registers, Counters and a SimpleProcessor (cont) 7.4 Master-Slave and Edge-Triggered D Flip-Flops February 6, 20127.4.1 Master-Slave D Flip-Flop7.4.2 Edge-Triggered D Flip-Flop7.4.3 D Flip-Flop with Clear and Preset7.4.4 Flip-Flop Timing Parameters (2nd edition)ECE 152A - Digital Design Principles3
Reading Assignment Roth 11 Latches and Flip-Flops February 6, 201211.1 Introduction11.2 Set-Reset Latch11.3 Gated D Latch11.4 Edge-Triggered D Flip-FlopECE 152A - Digital Design Principles4
Reading Assignment Roth (cont) 12 Registers and Counters February 6, 201212.1 Registers and Register Transfers12.2 Shift Registers12.3 Design of Binary Counters12.4 Counters for Other SequencesECE 152A - Digital Design Principles5
Combinational vs. Sequential Logic Combinational logic Function of present inputs only Output is known if inputs (some or all) are knownSequential logic Function of past and present inputs Memory or “state”Output known if present input and present state areknown February 6, 2012Initial conditions often unknown (or undefined)ECE 152A - Digital Design Principles6
Gate Delays Recall from earlier lecture When gate inputs change, outputs don’t changeinstantaneouslyFebruary 6, 2012ECE 152A - Digital Design Principles7
Feedback Outputs connected to inputs Single inverter feedback February 6, 2012If propagation delay is long enough, output will oscillateECE 152A - Digital Design Principles8
Feedback If the propagationdelay is not longenough, the outputwill settle somewherein the middle February 6, 2012Vin VoutECE 152A - Digital Design Principles9
Feedback Ring Oscillator Any odd number of inverters will oscillate February 6, 2012½ period total prop delay of chainECE 152A - Digital Design Principles10
Feedback What about an even number of inversions? Two inverter feedback February 6, 2012Memory (or State)Static 1 or 0 “stored” in memoryECE 152A - Digital Design Principles11
The Latch Replace inverters with NOR gatesFebruary 6, 2012ECE 152A - Digital Design Principles12
The Set-Reset (SR) Latch NOR implementation Inverted feedbackFebruary 6, 2012ECE 152A - Digital Design Principles13
The SR Latch R Reset (clear) S Set (preset) Q 0, Q* 1Q 1, Q* 0NOR gate implementation Either input 1 forces an output to 0February 6, 2012ECE 152A - Digital Design Principles14
The SR Latch (cont) Terminology Present state, Q Current value of Q and Q*Next state, Q February 6, 2012Final value of Q and Q* after input changesECE 152A - Digital Design Principles15
The SR Latch (cont) Operation S 1, R 0 : set to 1, Q 1S 0, R 1 : reset to 0, Q 0S 0, R 0 : hold state, Q QS 1, R 1 : not allowed February 6, 2012Q Q* 0, lose stateECE 152A - Digital Design Principles16
The SR Latch (cont) Timing Diagram RS inputs are “pulses” February 6, 2012Temporarily high, but normally lowECE 152A - Digital Design Principles17
The SR Latch (cont) Characteristic Equation Algebraic expression of flip-flop behaviorPlot characteristic table on map, find Q February 6, 2012Q S R’Q (S R 1 not allowed)ECE 152A - Digital Design Principles18
The SR Latch (cont) Characteristic Equation Q S R’Q (S R 1 not allowed) February 6, 2012Q becomes 1 when S 1, R 0Stays Q when S R 0Q becomes 0 when S 0, R 1ECE 152A - Digital Design Principles19
The SR Latch (cont) State TableNS (Q )February 6, 2012PS (Q)SR 000110110001X1101XECE 152A - Digital Design Principles20
The SR Latch (cont) State DiagramSR 01SR X010SR 0XSR 10February 6, 2012ECE 152A - Digital Design Principles21
The Gated SR Latch Also known as “transparent” latch Output follows input (transparent) when enabledFebruary 6, 2012ECE 152A - Digital Design Principles23
The Gated SR Latch (cont) Timing DiagramFebruary 6, 2012ECE 152A - Digital Design Principles24
The Gated SR Latch (cont) NAND ImplementationFebruary 6, 2012ECE 152A - Digital Design Principles25
The Gated Data (D) Latch NAND Implementation of transparent D latchFebruary 6, 2012ECE 152A - Digital Design Principles26
The Gated D Latch Timing DiagramFebruary 6, 2012ECE 152A - Digital Design Principles27
The Edge Triggered D Flip-Flop The D Flip-Flop Input D, latched and passed to Q on clock edgeRising edge triggered or falling edge triggered February 6, 2012Characteristic table and functionECE 152A - Digital Design Principles28
The Edge Triggered D Flip-Flop Most commonly used flip-flopOutput follows input after clock edge February 6, 2012Q and Q* change only on clock edgeTiming diagram for negative edge triggered flip-flopECE 152A - Digital Design Principles29
The D Flip-Flop State TableNS (Q )February 6, 2012PS (Q)D 0D 1001101ECE 152A - Digital Design Principles30
The D Flip-Flop (cont) State DiagramD 0D 110D 0D 1February 6, 2012ECE 152A - Digital Design Principles31
The Master-Slave D Flip-Flop Construct edge triggered flip-flop from 2transparent latches Many other topologies for edge triggered flip-flopsFalling edge triggered (below)February 6, 2012ECE 152A - Digital Design Principles32
The Master-Slave D Flip-Flop (cont) Timing Diagram Falling edge triggeredFebruary 6, 2012ECE 152A - Digital Design Principles33
The Master-Slave D Flip-Flop (cont) A Second Timing Diagram Rising edge triggeredFebruary 6, 2012ECE 152A - Digital Design Principles34
The Edge Triggered D Flip-Flop “True” Edge Triggered D Flip-Flop Never transparent (unlike Master Slave)February 6, 2012ECE 152A - Digital Design Principles35
The Edge Triggered D Flip-Flop Operation of Flip-FlopFebruary 6, 2012ECE 152A - Digital Design Principles36
Types of D Flip-Flops Gated, Positive Edge and Negative EdgeFebruary 6, 2012ECE 152A - Digital Design Principles37
Timing Parameters CLK Q Setup time tsu Delay from clock edge (CLK) to valid (Q, Q*) outputStable, valid data (D) before clock edge (CLK)Hold time thold February 6, 2012Stable, valid data (D) after clock edge (CLK)ECE 152A - Digital Design Principles38
Maximum Frequency Maximum frequency (minimum clock period)for a digital system CLK Q propagation delay tsuFebruary 6, 2012ECE 152A - Digital Design Principles39
Counter Design with D Flip-Flops Design Example #1: Modulo 3 counter 00 01 10 Requires 2 flip-flops One for each “state variable”February 6, 2012ECE 152A - Digital Design Principles40
Counter Design with D Flip-Flops State Diagram00Transitions onclock edgeFebruary 6, 20120110ECE 152A - Digital Design Principles41
Counter Design with D Flip-Flops State TablePSA0011February 6, 2012NSB0101A 010XECE 152A - Digital Design PrinciplesB 100X42
Counter Design with D Flip-Flops Next State MapsB0100110XAB0101010XAA BFebruary 6, 2012B A’B’ECE 152A - Digital Design Principles43
Counter Design with D Flip-Flops Implementation with D Flip-FlopsWhat are the D inputs to flip-flops A and B? Recall characteristic equation for D flip-flop February 6, 2012Q DTherefore,and A B DA BB A’B’ DB A’B’ECE 152A - Digital Design Principles44
Counter Design with D Flip-Flops Implementation with positive edge triggeredflip-flopsFebruary 6, 2012ECE 152A - Digital Design Principles45
Counter Design with D Flip-Flops Implementation with positive edge triggeredflip-flops Timing diagram00February 6, 2012011000ECE 152A - Digital Design Principles0146
Counter Design with D Flip-Flops Design Example #2: Modulo 3 counter with up/down* input Counter counts up with input 1 and down withinput 0Implement with D flip-flopsFebruary 6, 2012ECE 152A - Digital Design Principles47
Counter Design with D Flip-Flops State diagram1000010101February 6, 201210ECE 152A - Digital Design Principles48
Counter Design with D Flip-Flops State tableFebruary 6, 2012UABA B 000100010001001011XX100011011011000111XXECE 152A - Digital Design Principles49
Counter Design with D Flip-Flops Next state maps and flip-flop inputsABAB00011110U00011110X1U0111X0X1A DA UB U’A’B’February 6, 2012ECE 152A - Digital Design Principles1XB DB U’A UA’B’50
February 6, 2012 ECE 152A - Digital Design Principles 3 Reading Assignment Brown and Vranesic (cont) 7Flip-Flops, Registers, Counters and a Simple Processor (cont) 7.4 Master-Slave and Edge-Triggered D Flip-Flops 7.4.1 Master-Slave D Flip-Flop 7.4.2 Edge-Triggered D Flip-Flop 7.4.3 D Flip-Flop with Clear a
Rangkaian Flip-Flop JK Pada flip-flop JK ini, masukan J dan K disebut masukan pengendali karena kedua masukan ini yang menentukan keadaan yang harus dipilih oleh flip-flop pada saat pulsa clock tiba (dapat pinggiran positif atau negatif, tergantung kepada jenis flip-flopnya). flip-flop ini berbeda dengan flip-flop-D karena pada flip-flop-JK
D Flip Flop. Seperti yang diketahui, flip-flop (Bistable Multivibrator) dalah suatu rangkaian sel biner yang memiliki dua buah output yang saling berkebalikan keadaannya (0 atau 1). Di dalam FPGA, terdapat sebuah jenis flip-flop yaitu D flip-flop atau Data flip flop. Rangkaian D flip-flop ini berfungsi sebagai rangkaian
FLIP-FLOP (BISTABLE MULTIVIBRATOR / BISTABLE) DAN LATCH Flip-flop adalah perangkat 2 state, mempunyai 2 state pengoperasian stabil yg bersesuaian dgn 0 dan 1 biner. LATCH Flip flop yg state-state output tergantung pada tingkat sinyal input (0 atau 1). EDGE-TRIGERRED FLIP-FLOP Flip flop yg state-state output tergantung pada transisi
College/ Department: Keshav Mahavidyalaya, University of Delhi . Sequential Circuits-II 2 Institute of Lifelong Learning, University of Delhi . 4.2.1 Edge Triggered Flip-flop 4.2 Edge Triggered S-R Flip-flop 4.3 Edge Triggered D Flip-flop 4.4 Edge Triggered J-K Flip-flop 4.4.1 Racing 4.4.2 J-K Master Slave Flip-flop 4.5 Asynchronous Preset .
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Bentuk dasarnya adalah rangkaian flip-flop Bermanfaat karena karakteristik memorinya Gerbang adalah : pembuat keputusan . Sistem Digital. Missa Lamsani Hal 3 Flip-Flop Flip-flop mempunyai 2 keadaan stabil, dan akan bertahan pada salah satu dari dua keadaan itu sampai adanya pemicu yang membuatnya .
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