AN4881, MPC57xx SAR ADC Implementation And Use .
Freescale SemiconductorApplication NoteDocument Number: AN4881Rev 0, 06/2014MPC57xx SAR ADCImplementation and Useby:Curt Hillier, Siva M, Neeraj Jain, Sudhansu Mishra, Steve Mihalik, and SanjoyDeyContents1 Introduction1Introduction.1Analog-to-Digital Converters (ADCs) are used in a rapidlyincreasing number of automotive applications. From simplymonitoring DC voltages to supporting radar detection ofobstacles in ADAS solutions, ADCs find wide acceptance inautomotive Micro Controller Units (MCUs). The highlyintegrated Qorivva MPC57xx MCUs on the market todayincorporate high performance ADCs supporting up to 84channels with various combinations of Sigma Delta (SD)ADC, enhanced queued eQADC, and SuccessiveApproximation (SAR) ADC architectures in the same device.In these advanced MCUs, conversions from multiple types ofanalog inputs are supported in real time with a minimum ofcontrol required by the CPUs inside the MCU.2MPC57xx ADC Integration and FeatureSets. . 23SAR ADC integration examples. . 34Designing for best possibleperformance. . 5Depending on the system application requirements, theMPC57xx devices use three different ADC architectures: eQADC (an RSD solution) Successive Approximation Register (SAR) Sigma Delta modulator (SD)The SAR is available in two speed variants - a 1 MSPS (MegaSamples Per Second) SAR and 400 KSPS (Kilo Samples PerSecond) SAR.This application note discusses SAR ADC implementation anduse in the MPC57xx family of devices. The documentincludes the following topics: MPC57xx Device Family ADC implementation 2014 Freescale Semiconductor, Inc.4.1Input circuit. 64.2Clock circuit. . 94.3Power supply circuit. . 134.4PCB design recommendations.154.4.1Power supply design. .164.4.2Decoupling capacitors. . 164.4.3Grounding. . 164.4.4PCB routing. . 175SAR ADC calibration for gain error andoffset error. .176SAR ADC initialization example. 187Conclusion.228References. . 23
MPC57xx ADC Integration and Feature Sets MPC57xx SAR ADC featuresDesigning for best ADC performanceCalibrating the SAR to minimize gain error and offset errorInitializing the SAR ADC2 MPC57xx ADC Integration and Feature SetsFreescale supports a powerful family of MCUs focused on the automotive market space. Depending on the application, anMCU will contain various numbers of SAR ADCs, eQADCs and/or SD ADC's. The following table lists the number ofADCs, type of ADC, and number of inputs for each device in the MPC57xx family.Table 1. ADC support in the MPC57xx familyDevice1 MSPS 400 KSPSSAR ADC SAR ADCeQADC(RSD)SD ADCTotalnumberof inputs106Target 5Safety / body Motor Controlapplication, mid-range requirementsMPC5746M-8-8260Powertrain application, mid-rangerequirements12-12284Powertrain application, high endrequirements48Powertrain application, high-endrequirements, compatible ty / body motor controlapplication, lower end requirements25 (SAR) ADAS application, Radar interfacehigh end requirement8 (SD)52 (SAR) Powertrain application, mid-rangerequirements12 (SD)1. 320 MHz SD ADC for Analog Front End (AFE) radar interface, up to 5 MHz input bandwidth2. 16 MHz SD ADC for engine knock processing, up to 300 kHz input bandwidth.Each of the SAR ADCs supports similar functions such as multiplexed inputs, normal conversions, injected conversions,DMA of conversion data to System RAM, and interrupt generation. The following table summarizes features, and differencesexist between the SAR ADC implementations supported for each SAR type .Table 2. SAR ADC comparison tableParameter1 MSPS SAR ADC400 KSPS SAR ADC200 KSPS SAR ADC (inputmonitoring)Resolution10 or 12 bits12 bits12 bitsConversion Time1 microsecond conversiontime2.5 microsecond conversiontime5.0 microsecond conversiontimeClock80 MHz14.6 MHz14.6 MHzTable continues on the next page.MPC57xx SAR ADC Implementation and Use, Rev 0, 06/20142Freescale Semiconductor, Inc.
SAR ADC integration examplesTable 2. SAR ADC comparison table (continued)Parameter1 MSPS SAR ADCIntegration Strategy400 KSPS SAR ADC200 KSPS SAR ADC (inputmonitoring)Low ADC instance count (2 Higher ADC instance count (8Single ADC instance perto 4 ADCs per device), highto 12 ADCs per device), low device, monitors all inputs (60input channel count per ADCinput channel count (4 to 8inputs or 84 inputs, deviceinputs) per ADCdependent)InputsUp to maximum 96 channels(32 A/D inputs, 32 on-chipinputs, and 32 externalinputs)typically 4 to 8 inputsSupports up to 128 channels.Supports monitoring of allother SAR ADC inputs andSigma-Delta ADC inputs inthe deviceOperating Modes3 modes: Normal / Injected /CTU2 modes: Normal / Injected2 modes: Normal / InjectedScanning ModesOne shot, chain, andcontinuous modes ofscanningOne shot, chain, andcontinuous modes ofscanningOne shot, chain, andcontinuous modes ortAbort capability for either asingle channel or chain inNormal or Injected modesAbort capability for either asingle channel or chain inNormal or Injected modesAbort capability for either asingle channel or chain inNormal or Injected modesAnalog portedsupportedInterruptsInterrupt for the followingconditions:Interrupt for the followingconditions:Interrupt for the followingconditions:End of conversion of singlechannel for both normal,injected conversionsEnd of conversion of singlechannel for both normal,injected conversionsEnd of conversion of singlechannel for both normal,injected conversionsEnd of conversion chain forboth normal, injectedconversionsEnd of conversion chain forboth normal, injectedconversionsEnd of conversion chain forboth normal, injectedconversionsEnd of CTU conversionNo CTU interruptNo CTU interruptWatchdog thresholdscrossoverWatchdog thresholdscrossoverWatchdog thresholdscrossoverCalibrationSoftware Initiated CalibrationAutomatic, hidden from userAutomatic, hidden from userSelf TestIntegrated Self Testingfeature, software drivenUses SAR ADC B supervisorfor monitoring test channelsupported: Test channelimpedance comparison toexternal input impedanceTriggersTrigger from Cross Triggering Trigger sources from external Trigger sources from externalUnit (CTU)pins and GTM channelspins and GTM channelsCTU / BCTUSupportedNoneNone3 SAR ADC integration examplesThe MPC57xx family of devices integrates 1 MSPS SAR ADCs, 400 KSPS SAR ADCs, and 200 KSPS SARADCsdepending on application requirements. 1 MSPS SAR ADC integration typically includes the following: Self Test logic in each SAR ADC Calibration logic initiated by softwareMPC57xx SAR ADC Implementation and Use, Rev 0, 06/2014Freescale Semiconductor, Inc.3
SAR ADC integration examples Triggers from Cross Triggering Logic Triggers from eTPU and external sources Monitoring of internal voltagesFigure 1 illustrates 1 MSPS SAR integration in the MPC5746R device.SystemRAMADC Self TestLogic in each SAR ADCDMAADC BandgapTemp Sensor1MspsConversion ResultsPMC SignalsSAR ADC Limit FlagEMIOSETPUExternal TriggerTrigger Out to ADCs.INTCNormalTriggersCTUTriggerConversion ResultExternal InputsSAR ADCs (4)SIUL2ETPUEMIOSBCTUTrigger InputsReactionChannelMuxingExternal PinsPITFigure 1. 1 MSPS SAR ADC integration400 KSPS and 200 KSPS SAR ADC integration typically includes the following: Self Test of 400 KSPS SAR ADCs supported by the 200 KSPS SAR ADC B No Calibration needed No CTU logic support Triggers from external sources such as Generic Timer Module (GTM)Figure 2 illustrates 400 KSPS and 200 KSPS SAR ADC implementation in the MPC5777M device.MPC57xx SAR ADC Implementation and Use, Rev 0, 06/20144Freescale Semiconductor, Inc.
Designing for best possible IMMSCRinput muxanalog switchpad cellsTOM/ATOMexternal pintrigger inputsMSCRMSCR400KspsInjection TriggersSARADC(0.11)Sigma-DeltaADC inputsINTC2ndlevelSoCmuxADC bandgapTemp sensorPMC signalsNormal TriggersDMASARADC B200KspsRAMSARADC B usedfor Self Test of SARADC (0.11)Figure 2. 400 KSPS and 200 KSPS SAR ADC integration (MPC5777M example)4 Designing for best possible performanceThis section provides guidelines to achieve the best dynamic performance from a Successive Approximation Register (SAR)ADC. There are several parameters defining performance for an ADC [4]. This document concentrates only on dynamicparameters and how to achieve maximum dynamic performance. Signal-to-Noise Ratio (SNR), Total Harmonic Distortion(THD), and Signal-to-Noise and Distortion (SINAD) are the most common dynamic specs for ADCs.These recommendations are supported by theory and silicon test data which was collected at Freescale on a Bench Validationboard for the MPC57XX device family. Even though silicon results are shared for a 12-bit SAR ADC only, guidelines areapplicable for any other SAR ADC evaluation. It is strongly recommended to validate the dynamic performance in additionto adhering to guidelines in this note.The Figure 3 below shows a typical ADC interface in a System on a Chip (SoC). It consists of:1. Input signal: Signal conditioning circuit to feed input analog signal to the ADC2. ADC Clock: Clock synthesis circuit to provide required clock frequency to the ADC3. ADC Supply & Reference: Power supply circuits to provide analog and reference supplies to the ADCMPC57xx SAR ADC Implementation and Use, Rev 0, 06/2014Freescale Semiconductor, Inc.5
Designing for best possible performancePOWER MANAGEMENTSMPS RegulatorsLinear RegulatorAnalog InputMCUDigital I/OSIGNALCONDITIONINGCIRCUITSADCIRCXOSCPLLCLOCK MANAGEMENTFigure 3. Typical ADC in an SoCEquation 1 on page 6 gives the relation between ADC output, input and reference voltage for an ideal SAR ADC.Equation 1VIN Analog input voltageVREF ADC reference voltageN resolution of the ADC (number of bits)From Equation 1 on page 6 it is clear that any noise at the input and reference will have direct impact on the output voltage.Noise at the ADC clock input will also impact the ADC performance. To measure true performance of an ADC, performanceof all these circuits should be better as compared to ADC. Table 3 shows the effect of external noise on the overallperformance of the ADC. Here external noise refers to input signal source noise, clock jitter related noise, ADC referencevoltage noise or combination of all. From Table 3 it is clear that to get true of performance of ADC, quality of externalsystem should be at least 10 dB better than Device Under Test (DUT). In this application note, basic circuit details, theirimportance and results are shared for an ADC input, clock and supply interfacing blocks.Table 3. Effect of external circuit noise on ADC performanceVREF (V)ADC SNR(dB)ADC Noise(rms V)ExternalExternalSystem SNRCircuit Noise Circuit Noise(dB)(dB)(rms V)SystemNoise (rms V)Error inmeasuredSNR 67.0791-3.0MPC57xx SAR ADC Implementation and Use, Rev 0, 06/20146Freescale Semiconductor, Inc.
Designing for best possible performance4.1 Input circuitThe SAR ADC consists of a sample-and-hold circuitry to acquire the input voltage VIN, a comparator, a successiveapproximation register sub-circuit, and an internal reference capacitive Digital to Analog Converter (DAC). This DACsupplies the comparator with an analog voltage equivalent of the digital code output of the SAR, for comparison with VIN.Any SAR ADC will have two phases: sampling phase and conversion phase. During the sampling phase the input has tosettle to the less than or equal to quantization level, i.e. 0.5 LSB. In the sampling phase, the sample and hold switch is closed,thereby charging the internal SAR ADC capacitors. During the conversion phase, the sample and hold switch is open and theSAR approximates its registers to the held VIN.The Input signal conditioning circuit typically consists of buffer followed by a first order RC-low pass filter. Figure 4 showsa simple mixer circuit using an ideal Op Amp.In the input circuit, the RC filter serves two purposes, it limits the amount out-of-band noise arriving at the ADC input andhelps to attenuate any voltage kicks from the ADC sampling. Low pass filter RC bandwidth is a function of input frequency,resolution, sampling time of ADC. For a given RC bandwidth, selection of the R and C values depends on the Op Ampdriving capability and ADC Input channel capacitance. The lower limit on the R value comes from the Op Amp. There is anupper limit on C also due to the Op Amp capability. The Op Amp cannot drive big capacitance values in the order of tens ofnF. Figure 6 shows an FFT plot using R 1 Ohm and C 47 nF. Figure 6 clearly shows that the Op Amp is not able to drivebig capacitances such as 47 nF and due to this quality of the input signal is distorted -- notice the harmonic components in theFFT at the output of the ADC. The lower limit on the capacitance is a function of SoC input sampling capacitance. There is alimit on the boundary values of R and C, but within the range any value of R and C is allowed. Freescale recommendschecking the ADC performance on silicon to get optimal R and C values. Figure 5 shows a typical FFT plot with R 36 Ohmand C 3 nF.For capacitor, selection of type of dielectric material is important. Capacitor voltage coefficient determines the THD of thesystem. Select the capacitor with low voltage coefficient. Silver Mica, polypropylene, polystyrene, and COG/NPO types havelower voltage coefficient as compared to other types. Generally COG/NPO types are readily available in wide range and withdifferent foot print sizes.MPC57xx SAR ADC Implementation and Use, Rev 0, 06/2014Freescale Semiconductor, Inc.7
Designing for best possible performanceFigure 4. Typical Op Amp driver circuit input and output waveformsMPC57xx SAR ADC Implementation and Use, Rev 0, 06/20148Freescale Semiconductor, Inc.
Designing for best possible performanceFigure 5. ADC FFT with Fin 125 kHz, R 36 Ohm and C 3 nFFigure 6. ADC FFT with Fin 125 kHz, R 1 Ohm and C 47 nF4.2 Clock circuitFreescale MCUs provides several options to feed clocks to the ADC module through on-chip options. The internal RCoscillator and Crystal oscillator circuits are commonly available circuits in most of the MCUs. The following is the briefdescription of common clock modules available in a typical MCU.MPC57xx SAR ADC Implementation and Use, Rev 0, 06/2014Freescale Semiconductor, Inc.9
Designing for best possible performanceInternal RC Oscillator (IRC OSC): Provides fast startup, low power, but generally suffer from high jitter, poor accuracyover temperature and supply voltage.CRYSTAL OSCILLATOR (XTAL OSC): Typically provides very high initial accuracy and a moderately low temperaturecoefficient, low jitter and will have higher startup time and consumes more power.PLL: Generally it will be used to bring different frequency clocks to various modules of SOC using a fixed reference source.Input reference clock to the PLL can be either IRC or XTAL OSC. Proceeding further below nomenclature will be used.IRC PLL: Input reference clock to the PLL is Internal RC oscillator. PLL is programmed to provide required clockfrequency to ADCXTAL PLL: Input reference clock to the PLL is crystal oscillator. PLL is programmed to provide required clock frequencyto ADCSelection of clock circuit combinations is important because it will impact the dynamic performance of the ADC. The term"jitter" describes timing errors within a system.It can be shown that jitter on the sampling clock degrades the overall SNR per the simple equation:Equation 2Equation 3where:fIN analog input frequencytRMS RMS clock jitterN resolution of the ADC (number of bits)From Equation 2 on page 10 it is clear that the degradation in SNR is dependent on the input frequency and clock RMS jitter.It should be noted that this equation assumes IDEAL ADC of infinite resolution, where the only error source is clock jitter.Ideal SNR limitation of the ADC for a given resolution is given by Equation 3 on page 10. From Table 3 it is clear that clocksource quality should be at least 10 dB better than DUT. Consequently, to get proper performance for a 12-bit SAR ADC atfIN 125 kHz, clock jitter should be less than 100 ps (corresponds to 82 dB at fIN 125 kHz).RMS clock jitter can be calculated by integrated phase noise to the required BW. Generally the upper frequency range for theintegration should be twice the sampling frequency [3]. In our example case we use the 1 MSPS SAR ADC, therefore,integration bandwidth is from zero to 2 MHz. Figure 7 and Figure 8 shows phase noise plot of IRC PLL and XTAL PLLcollected using Agilent E5052B Signal Source Analyzer with integration from close to DC to 2 MHz. Measured RMS jitter is50 ns and 25 ps approximately for IRC PLL and XTAL PLL respectively.Figure 9 and Figure 10 show the effect of clock sources on the ADC dynamic performance for a 12-bit 1 MSPS ADC withFin 125 kHz for IRC PLL and XTAL PLL respectively. From the figures it is clear the noise floor has gone up and alsosome smearing is observed around the fundamental for IRC PLL as clock source for ADC. IRC should never be used as aclock source if dynamic performance is important. Below are some of the reasons for this: IRC has very high Jitter (in nS range) Jitter will not be constant, multiple measurements will result in varying Jitter IRC Jitter will vary with Voltage & TemperatureDue to above issues Run-to-Run variation can be observed in the SNR measurements.MPC57xx SAR ADC Implementation and Use, Rev 0, 06/201410Freescale Semiconductor, Inc.
Designing for best possible performanceFigure 7. Phase noise plot of IRC PLLFigure 8. Phase noise plot of XTAL PLLMPC57xx SAR ADC Implementation and Use, Rev 0, 06/2014Freescale Semiconductor, Inc.11
Designing for best possible performanceFigure 9. IRC PLL as clock sourceFigure 10. XTAL PLL as clock sourceFigure 11 shows variation of SNR with input frequency with different clock sources. For below 1 kHz, SNR is almost samewith IRC PLL and XTAL PLL as a source. As frequency increases effect of jitter is clearly observed for IRC PLL.Therefore, for frequency 1 kHz, XTAL PLL circuit should be used as clock source for the ADC.MPC57xx SAR ADC Implementation and Use, Rev 0, 06/201412Freescale Semiconductor, Inc.
Designing for best possible performanceFigure 11. Effect of clock source on ADC performance4.3 Power supply circuitNoise, stability and drive capability are some of the important characteristics need to be considered for a SAR ADC voltagereference circuit. From Equation 1 on page 6 it is clear that noise at the reference will impact the ADC performance. Figure12 shows the variation of system noise with DC input voltage for a SAR ADC. Here data is collected with a low noise andnoisy voltage reference circuit at the same conditions. From Figure 12, it is clear that effect of the reference noise is notconstant and is dependent on the ADC input [2].MPC57xx SAR ADC Implementation and Use, Rev 0, 06/2014Freescale Semiconductor, Inc.13
Designing for best possible performanceFigure 12. Effect of reference noise on the ADC performanceGiven the importance o
2. ADC Clock: Clock synthesis circuit to provide required clock frequency to the ADC 3. ADC Supply & Reference: Power supply circuits to provide analog and reference supplies to the ADC Designing for best possible performance MPC57xx SAR ADC Implementation and Use, Rev 0, 06/2014 Freescale Semiconductor, Inc. 5
DAC DAC ADC ADC. X19532-062819. Figur e 2: RF-ADC Tile Structure. mX0_axis Data Path ADC VinX0 mX1_axis Data Path ADC VinX1 mX2_axisData Path ADC VinX2 mX3_axis Data Path ADCVinX3 mX3_axis mX1_axis ADC mX0_axis Data Path ADC Data Path ADC VinX_23 VinX_01 Data Path Data Path Dual RF-ADC Tile Quad RF-ADC Tile. X23275-100919. Chapter 2: Overview
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· ADC-20 or ADC-24 High-Resolution Data Logger · Quick Start Guide For detailed technical information, please refer to the ADC-20 and ADC-24 Data Sheet. An optional PP310 ADC-20/ADC-24 Terminal Board is designed for use with both data loggers. For simple applications, you can connect sensor wires to the screw terminals on the terminal board,
An ADC refers to a system that converts an analog signal into a digital signal. ADC architectures, notably the Flash ADC, Successive Approximation Register (SAR) ADC and the Pipeline ADC have evolved over the years, each offering one advantage over the other. High speed of operation while resolving a high number of bits with
tions that require power-e cient analog-to-digital conversion. Based on Berkeley Analog Generator (BAG), a time-interleaved SAR ADC generator has been implemented in di er-ent technologies. To explore the design ow using circuit generators, this report discusses the working principle and implementation of time-interleaved SAR ADC. A test chip has
third-order Σ ADC is similar to that of a first-order CT Σ ADC. Its robustness against RC product variation is higher than that of a third-order purely CT Σ ADC. Fig. 11 shows the simulated SQNR of the proposed third-order Σ ADC and the proposed second-order NS SAR quantizer. At the OSR of 20, the second-order NS SAR
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