Spartan-3A FPGA Family Data Sheet (DS529)

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0Spartan-3A FPGA Family:Data SheetDS529 December 18, 201800Product SpecificationModule 1:Introduction and Ordering InformationModule 3:DC and Switching CharacteristicsDS529 (v2.1) December 18, 2018DS529 (v2.1) December 18, 2018 IntroductionFeaturesArchitectural and Configuration OverviewGeneral I/O CapabilitiesProduction StatusSupported Packages and Package MarkingOrdering Information Module 2:Spartan-3A FPGA Family: FunctionalDescriptionDS529 (v2.1) December 18, 2018DC Electrical Characteristics Absolute Maximum Ratings Supply Voltage Specifications Recommended Operating ConditionsSwitching Characteristics I/O Timing Configurable Logic Block (CLB) Timing Multiplier Timing Block RAM Timing Digital Clock Manager (DCM) Timing Suspend Mode Timing Device DNA Timing Configuration and JTAG TimingThe functionality of the Spartan -3A FPGA family isdescribed in the following documents.Module 4:Pinout Descriptions DS529 (v2.1) December 18, 2018 UG331: Spartan-3 Generation FPGA User Guide Clocking Resources Digital Clock Managers (DCMs) Block RAM Configurable Logic Blocks (CLBs)Distributed RAMSRL16 Shift RegistersCarry and Arithmetic Logic I/O Resources Embedded Multiplier Blocks Programmable Interconnect ISE Design Tools and IP Cores Embedded Processing and Control Solutions Pin Types and Package Overview Package Drawings Powering FPGAs Power ManagementUG332: Spartan-3 Generation Configuration User Guide Configuration Overview Configuration Pins and Behavior Bitstream Sizes Detailed Descriptions by ModeMaster Serial Mode using Platform Flash PROMMaster SPI Mode using Commodity Serial FlashMaster BPI Mode using Commodity Parallel FlashSlave Parallel (SelectMAP) using a ProcessorSlave Serial using a ProcessorJTAG Mode ISE iMPACT Programming Examples MultiBoot Reconfiguration Design Authentication using Device DNAUG334: Spartan-3A/3AN FPGA Starter Kit User Guide Pin DescriptionsPackage OverviewPinout TablesFootprint DiagramsFor more information on the Spartan-3A FPGA family, go towww.xilinx.com/spartan3aSpartan-3A 00AProductionXC3S700AProductionXC3S1400AProduction Copyright 2006–2018 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States andother countries. PCI is a registered trademark of the PCI-SIG. All other trademarks are the property of their respective owners.DS529 December 18, 2018Product Specificationwww.xilinx.com1

Spartan-3A FPGA Family: Data Sheet2www.xilinx.comDS529 December 18, 2018Product Specification

8Spartan-3A FPGA Family:Introduction and Ordering InformationDS529 (v2.1) December 18, 2018Product SpecificationIntroductionThe Spartan -3A family of Field-Programmable GateArrays (FPGAs) solves the design challenges in mosthigh-volume, cost-sensitive, I/O-intensive electronicapplications. The five-member family offers densities rangingfrom 50,000 to 1.4 million system gates, as shown in Table 1.The Spartan-3A FPGAs are part of the ExtendedSpartan-3A family, which also include the non-volatileSpartan-3AN and the higher density Spartan-3A DSPFPGAs. The Spartan-3A family builds on the success of theearlier Spartan-3E and Spartan-3 FPGA families. Newfeatures improve system performance and reduce the costof configuration. These Spartan-3A family enhancements,combined with proven 90 nm process technology, delivermore functionality and bandwidth per dollar than ever before,setting the new standard in the programmable logic industry.Because of their exceptionally low cost, Spartan-3A FPGAsare ideally suited to a wide range of consumer electronicsapplications, including broadband access, home networking,display/projection, and digital television equipment.The Spartan-3A family is a superior alternative to maskprogrammed ASICs. FPGAs avoid the high initial cost,lengthy development cycles, and the inherent inflexibility ofconventional ASICs, and permit field design upgrades. Very low cost, high-performance logic solution forhigh-volume, cost-conscious applicationsDual-range VCCAUX supply simplifies 3.3V-only designSuspend, Hibernate modes reduce system powerMulti-voltage, multi-standard SelectIO interface pins Up to 502 I/O pins or 227 differential signal pairsLVCMOS, LVTTL, HSTL, and SSTL single-ended I/O3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signalingSelectable output drive, up to 24 mA per pinQUIETIO standard reduces I/O switching noiseFull 3.3V 10% compatibility and hot swap compliance Low-cost, space-saving SPI serial Flash PROMx8 or x8/x16 BPI parallel NOR Flash PROMLow-cost Xilinx Platform Flash with JTAGUnique Device DNA identifier for design authenticationLoad multiple bitstreams under FPGA controlPost-configuration CRC checkingComplete Xilinx ISE and WebPACK developmentsystem software support plus Spartan-3A Starter KitMicroBlaze and PicoBlaze embedded processorsLow-cost QFP and BGA packaging, Pb-free options Clock skew elimination (delay locked loop)Frequency synthesis, multiplication, divisionHigh-resolution phase shiftingWide frequency range (5 MHz to over 320 MHz)Eight low-skew global clock networks, eight additionalclocks per half device, plus abundant low-skew routingConfiguration interface to industry-standard PROMs Up to 576 Kbits of fast block RAM with byte write enablesfor processor applicationsUp to 176 Kbits of efficient distributed RAMUp to eight Digital Clock Managers (DCMs) Densities up to 25,344 logic cells, including optional shiftregister or distributed RAM supportEfficient wide multiplexers, wide logicFast look-ahead carry logicEnhanced 18 x 18 multipliers with optional pipelineIEEE 1149.1/1532 JTAG programming/debug portHierarchical SelectRAM memory architecture Features Abundant, flexible logic resources 640 Mb/s data transfer rate per differential I/OLVDS, RSDS, mini-LVDS, HSTL/SSTL differential I/Owith integrated differential termination resistorsEnhanced Double Data Rate (DDR) supportDDR/DDR2 SDRAM support up to 400 Mb/sFully compliant 32-/64-bit, 33/66 MHz PCI technologysupportCommon footprints support easy density migrationCompatible with select Spartan-3AN nonvolatile FPGAsCompatible with higher density Spartan-3A DSP FPGAsXA Automotive version availableTable 1: Summary of Spartan-3A FPGA AttributesCLB Array(One CLB Four 00ASystem EquivalentGates Logic Cells Rows 825,34416324048721216243240DistributedRAM 60K576KMaximumDedicatedMaximum DifferentialMultipliers DCMs User I/OI/O tes:1. By convention, one Kb is equivalent to 1,024 bits. Copyright 2006–2018 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States andother countries. PCI is a registered trademark of the PCI-SIG. All other trademarks are the property of their respective owners.DS529 (v2.1) December 18, 2018www.xilinx.com3

Introduction and Ordering InformationArchitectural Overview The Spartan-3A family architecture consists of fivefundamental programmable functional elements: Configurable Logic Blocks (CLBs) contain flexibleLook-Up Tables (LUTs) that implement logic plusstorage elements used as flip-flops or latches. CLBsperform a wide variety of logical functions as well asstore data.Input/Output Blocks (IOBs) control the flow of databetween the I/O pins and the internal logic of thedevice. IOBs support bidirectional data flow plus 3-stateoperation. Supports a variety of signal standards,including several high-performance differentialstandards. Double Data-Rate (DDR) registers areincluded.Block RAM provides data storage in the form of 18-Kbitdual-port blocks.Multiplier Blocks accept two 18-bit binary numbers asinputs and calculate the product.Digital Clock Manager (DCM) Blocks provideself-calibrating, fully digital solutions for distributing,delaying, multiplying, dividing, and phase-shifting clocksignals.These elements are organized as shown in Figure 1. A dualring of staggered IOBs surrounds a regular array of CLBs.Each device has two columns of block RAM except for theXC3S50A, which has one column. Each RAM columnconsists of several 18-Kbit RAM blocks. Each block RAM isassociated with a dedicated multiplier. The DCMs arepositioned in the center with two at the top and two at thebottom of the device. The XC3S50A has DCMs only at thetop, while the XC3S700A and XC3S1400A add two DCMs inthe middle of the two columns of block RAM and multipliers.The Spartan-3A family features a rich network of routing thatinterconnect all five functional elements, transmitting signalsamong them. Each functional element has an associatedswitch matrix that permits multiple connections to therouting.IOBsMultiplierDCMBlock RAMCLBIOBsOBsIOBsIOBsCLBsDCMBlock RAM / MultiplierDCMIOBsDS312-1 01 032606Notes:1.The XC3S700A and XC3S1400A have two additional DCMs on both the left and right sides as indicated by thedashed lines. The XC3S50A has only two DCMs at the top and only one Block RAM/Multiplier column.Figure 1: Spartan-3A FPGA Architecture4www.xilinx.comDS529 (v2.1) December 18, 2018

Introduction and Ordering InformationConfigurationI/O CapabilitiesSpartan-3A FPGAs are programmed by loadingconfiguration data into robust, reprogrammable, staticCMOS configuration latches (CCLs) that collectively controlall functional elements and routing resources. The FPGA’sconfiguration data is stored externally in a PROM or someother non-volatile medium, either on or off the board. Afterapplying power, the configuration data is written to theFPGA using any of seven different modes:The Spartan-3A FPGA SelectIO interface supports manypopular single-ended and differential standards. Table 2shows the number of user I/Os as well as the number ofdifferential I/O pairs available for each device/packagecombination. Some of the user I/Os are unidirectionalinput-only pins as indicated in Table 2. Master Serial from a Xilinx Platform Flash PROMSerial Peripheral Interface (SPI) from anindustry-standard SPI serial FlashByte Peripheral Interface (BPI) Up from anindustry-standard x8 or x8/x16 parallel NOR FlashSlave Serial, typically downloaded from a processorSlave Parallel, typically downloaded from a processorBoundary Scan (JTAG), typically downloaded from aprocessor or system tester Furthermore, Spartan-3A FPGAs support MultiBootconfiguration, allowing two or more FPGA configurationbitstreams to be stored in a single SPI serial Flash or a BPIparallel NOR Flash. The FPGA application controls whichconfiguration to load next and when to load it.Spartan-3A FPGAs support the following single-endedstandards: 3.3V low-voltage TTL (LVTTL)Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V,1.5V, or 1.2V3.3V PCI at 33 MHz or 66 MHzHSTL I, II, and III at 1.5V and 1.8V, commonly used inmemory applicationsSSTL I and II at 1.8V, 2.5V, and 3.3V, commonly usedfor memory applications Spartan-3A FPGAs support the following differentialstandards: LVDS, mini-LVDS, RSDS, and PPDS I/O at 2.5V or3.3VBus LVDS I/O at 2.5VTMDS I/O at 3.3VDifferential HSTL and SSTL I/OLVPECL inputs at 2.5V or 3.3V Additionally, each Spartan-3A FPGA contains a unique,factory-programmed Device DNA identifier useful fortracking purposes, anti-cloning designs, or IP protection.Table 2: Available User I/Os and Differential (Diff) I/O PairsPackageVQ100VQG100Body Size(mm)TQ144TQG14414 x 14(2)20 x G676FGG67617 x 1719 x 1921 x 2123 x 2327 x 1.2.The number shown in bold indicates the maximum number of I/O and input-only pins. The number shown in (italics) indicates the numberof input-only pins. The differential (Diff) input-only pin count includes both differential pairs on input-only pins and differential pairs on I/O pinswithin I/O banks that are restricted to differential inputs.The footprints for the VQ/TQ packages are larger than the package body. See the Package Drawings for details.DS529 (v2.1) December 18, 2018www.xilinx.com5

Introduction and Ordering InformationProduction StatusTable 3 indicates the production status of each Spartan-3AFPGA by temperature range and speed grade. The tablealso lists the earliest speed file version required for creatinga production configuration bitstream. Later versions are alsosupported.Table 3: Spartan-3A FPGA Production Status (Production Speed File)Temperature RangeCommercial (C)Part NumberSpeed GradeIndustrialStandard (–4)High-Performance (–5)Standard )Package MarkingThe “5C” and “4I” Speed Grade/Temperature Range partcombinations may be dual marked as “5C/4I”. Devices witha single mark are only guaranteed for the marked speedgrade and temperature range.Figure 2 provides a top marking example for Spartan-3AFPGAs in the quad-flat packages. Figure 3 shows the topmarking for Spartan-3A FPGAs in BGA packages. Themarkings for the BGA packages are nearly identical to thosefor the quad-flat packages, except that the marking isrotated with respect to the ball A1 indicator.Mask Revision CodeFabrication CodeRSPARTANRProcess TechnologyTMDevice TypePackageXC3S50ATQ144AGQ0625D1234567ADate CodeSpeed Grade4CLot CodeTemperature RangePin P1DS529-1 03 080406Figure 2: Spartan-3A QFP Package Marking ExampleMask Revision CodeBGA Ball A1RSPARTANDevice TypePackageRXC3S50ATMFT256 AGQ0625D1234567A4CFabrication CodeProcess CodeDate CodeLot CodeSpeed GradeTemperature RangeDS529-1 02 021206Figure 3: Spartan-3A BGA Package Marking Example6www.xilinx.comDS529 (v2.1) December 18, 2018

Introduction and Ordering InformationOrdering InformationSpartan-3A FPGAs are available in both standard and Pb-free packaging options for all device/package combinations. ThePb-free packages include a ‘G’ character in the ordering code.Example:XC3S50A -4 FT 256 CDevice TypeTemperature RangeSpeed GradePackage Type/Number of PinsDS529-1 05 011309DevicePackage Type / Number of Pins(1)Speed GradeTemperature Range ( TJ )XC3S50A–4 Standard Performance VQ100/VQG100100-pin Very Thin Quad Flat Pack (VQFP)C Commercial (0 C to 85 C)XC3S200A–5 High Performance(Commercial only)TQ144/TQG144144-pin Thin Quad Flat Pack (TQFP)I Industrial (–40 C to 100 C)XC3S400AFT256/FTG256256-ball Fine-Pitch Thin Ball Grid Array (FTBGA)XC3S700AFG320/FGG320320-ball Fine-Pitch Ball Grid Array (FBGA)XC3S1400AFG400/FGG400400-ball Fine-Pitch Ball Grid Array (FBGA)FG484/FGG484484-ball Fine-Pitch Ball Grid Array (FBGA)FG676FGG676676-ball Fine-Pitch Ball Grid Array (FBGA)Notes:1.2.See Table 2 for specific device/package combinations.See DS681 for the XA Automotive Spartan-3A FPGAs.Revision HistoryThe following table shows the revision history for this document.DateVersion12/05/061.0Initial release.02/02/071.1Promoted to Preliminary status. Updated maximum differential I/O count for XC3S50A in Table 1.Updated differential input-only pin counts in Table 2.03/16/071.2Minor formatting updates.04/23/071.3Added "Production Status" section.05/08/071.4Updated XC3S400A to Production.07/10/071.4.104/15/081.6Added VQ100 for XC3S50A and XC3S200A and extended FT256 to XC3S700A and XC3S1400AAdded reference to SCD 4103 for 750 Mbps performance.05/28/081.7Added reference to XA Automotive version.03/06/091.8Simplified Ordering Information. Added references to Extended Spartan-3A Family.Removed reference to SCD 4103.08/19/102.0Updated Table 2 to clarify TQ/VQ size.12/18/20182.1Updated for Lead-Frame Plating Composition Change For Legacy Eutectic Products (XCN18024).DS529 (v2.1) December 18, 2018RevisionMinor updates.www.xilinx.com7

Introduction and Ordering Information8www.xilinx.comDS529 (v2.1) December 18, 2018

10Spartan-3A FPGA Family:Functional DescriptionDS529 (v2.1) December 18, 2018Product Specification0Spartan-3A FPGA Design Documentation The functionality of the Spartan -3A FPGA Family isdescribed in the following documents. The topics covered ineach guide is listed below. DS706: Extended Spartan-3A Family Overviewwww.xilinx.com/support/documentation/data sheets/ds706.pdf UG331: Spartan-3 Generation FPGA User Guidewww.xilinx.com/support/documentation/user guides/ug331.pdf Clocking Resources Digital Clock Managers (DCMs) Block RAM Configurable Logic Blocks (CLBs)-Distributed RAM-SRL16 Shift Registers-Carry and Arithmetic LogicDetailed Descriptions by Mode-Master Serial Mode using Xilinx PlatformFlash PROM-Master SPI Mode using Commodity SPI SerialFlash PROM-Master BPI Mode using Commodity ParallelNOR Flash PROM-Slave Parallel (SelectMAP) using a Processor-Slave Serial using a Processor-JTAG Mode ISE iMPACT Programming Examples MultiBoot Reconfiguration Design Authentication using Device DNAFor application examples, see the Spartan-3A FPGAapplication notes. Spartan-3A FPGA Application 3a application notes.htm I/O Resources Embedded Multiplier Blocks Programmable Interconnect ISE Software Design Tools IP CoresFor specific hardware examples, please see the Spartan-3AFPGA Starter Kit board web page, which has links tovarious design examples and the user guide. Embedded Processing and Control Solutions Pin Types and Package OverviewSpartan-3A/3AN FPGA Starter Kit Board Pagewww.xilinx.com/s3astarter Package Drawings Powering FPGAs Power ManagementUG334: Spartan-3A/3AN FPGA Starter Kit ds and kits/ug334.pdfUG332: Spartan-3 Generation Configuration UserGuidewww.xilinx.com/support/documentation/user guides/ug332.pdf For information on the XA Automotive version of theSpartan-3A family, see the following data sheet. Configuration Overview-Configuration Pins and Behavior-Bitstream SizesXA Spartan-3A Automotive FPGA Family Data Sheetwww.xilinx.com/support/documentation/data sheets/ds681.pdfCreate a Xilinx user account and sign up to receiveautomatic e-mail notification whenever this data sheet orthe associated user guides are updated. Sign Up for Alertswww.xilinx.com/support/answers/18683.htm Copyright 2006–2018 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States andother countries. PCI is a registered trademark of the PCI-SIG. All other trademarks are the property of their respective owners.DS529 (v2.1) December 18, 2018www.xilinx.com9

Spartan-3A FPGA Family: Functional DescriptionRelated Product FamiliesThe Spartan-3AN nonvolatile FPGA family is architecturallyidentical to the Spartan-3A FPGA family, except that it hasin-system flash memory and is offered in selectpin-compatible package options. DS557: Spartan-3AN Family Data Sheetwww.xilinx.com/support/documentation/data sheets/ds557.pdfThe compatible Spartan-3A DSP FPGA family replaces the18-bit multiplier with the DSP48A block, while alsoincreasing the block RAM capability and quantity. The twomembers of the Spartan-3A DSP FPGA family extend theSpartan-3A density range up to 37,440 and 53,712 logiccells. DS610: Spartan-3A DSP FPGA Family Data Sheetwww.xilinx.com/support/documentation/data sheets/ds610.pdf UG431: XtremeDSP DSP48A for Spartan-3A DSPFPGAswww.xilinx.com/support/documentation/user guides/ug431.pdfRevision HistoryThe following table shows the revision history for this document.DateVersion12/05/061.0Initial release.02/02/071.1Promoted to Preliminary status.03/16/071.2Added cross-reference to nonvolatile Spartan-3AN FPGA family.04/23/071.3Added cross-reference to compatible Spartan-3A DSP family.07/10/071.4Updated Starter Kit reference to new UG334.04/15/081.6Updated trademarks.05/28/081.7Added reference to XA Automotive version.03/06/091.8Added link to DS706 on Extended Spartan-3A family.08/19/102.0Updated link to sign up for Alerts.12/18/1810RevisionUpdated for Lead-Frame Plating Composition Change For Legacy Eutectic Products (XCN18024).www.xilinx.comDS529 (v2.1) December 18, 2018

64Spartan-3A FPGA Family:DC and Switching CharacteristicsDS529 (v2.1) December 18, 2018Product Specification0DC Electrical CharacteristicsIn this section, specifications may be designated asAdvance, Preliminary, or Production. These terms aredefined as follows:Advance: Initial estimates are based on simulation, earlycharacterization, and/or extrapolation from thecharacteristics of other families. Values are subject tochange. Use as estimates, not for production.Preliminary: Based on characterization. Further changesare not expected.Production: These specifications are approved once thesilicon has been characterized over numerous productionlots. Parameter values are considered stable with no futurechanges expected.All parameter limits are representative of worst-case supplyvoltage and junction temperature conditions. Unlessotherwise noted, the published parameter values applyto all Spartan -3A devices. AC and DC characteristicsare specified using the same numbers for bothcommercial and industrial grades.Absolute Maximum RatingsStresses beyond those listed under Table 4: AbsoluteMaximum Ratings may cause permanent damage to thedevice. These are stress ratings only; functional operationof the device at these or any other conditions beyond thoselisted under the Recommended Operating Conditions is notimplied. Exposure to absolute maximum conditions forextended periods of time adversely affects device reliability.Table 4: Absolute Maximum TInternal supply voltage–0.51.32VVCCAUXAuxiliary supply voltage–0.53.75VVCCOOutput driver supply voltage–0.53.75VVREFInput reference voltage–0.5VCCO 0.5V–0.954.6V–0.54.6V– 100mAHuman body model– 2000VCharged device model– 500VMachine model– 200VVINVoltage applied to all User I/O pins anddual-purpose pinsDriver in a high-impedance stateVoltage applied to all Dedicated pinsIIKVESDInput clamp current per I/O pinElectrostatic Discharge Voltage–0.5V VIN (VCCO 0.5V) (1)TJJunction temperature–125 CTSTGStorage temperature–65150 CNotes:1.2.Upper clamp applies only when using PCI IOSTANDARDs.For soldering guidelines, see UG112: Device Packaging and Thermal Characteristics and XAPP427: Implementation and Solder ReflowGuidelines for Pb-Free Packages. Copyright 2006–2018 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States andother countries. PCI is a registered trademark of the PCI-SIG. All other trademarks are the property of their respective owners.DS529 (v2.1) December 18, 2018www.xilinx.com11

DC and Switching CharacteristicsPower Supply SpecificationsTable 5: Supply Voltage Thresholds for Power-On ResetSymbolDescriptionMinMaxUnitsVCCINTTThreshold for the VCCINT supply0.41.0VVCCAUXTThreshold for the VCCAUX supply1.02.0VVCCO2TThreshold for the VCCO Bank 2 supply1.02.0VNotes:1.2.VCCINT, VCCAUX, and VCCO supplies to the FPGA can be applied in any order. However, the FPGA’s configuration source (Platform Flash,SPI Flash, parallel NOR Flash, microcontroller) might have specific requirements. Check the data sheet for the attached configurationsource. Apply VCCINT last for lowest overall power consumption (see UG331 chapter “Powering Spartan-3 Generation FPGAs” for moreinformation).To ensure successful power-on, VCCINT, VCCO Bank 2, and VCCAUX supplies must rise through their respective threshold-voltage ranges withno dips at any point.Table 6: Supply Voltage Ramp RateSymbolDescriptionMinMaxUnitsVCCINTRRamp rate from GND to valid VCCINT supply level0.2100msVCCAUXRRamp rate from GND to valid VCCAUX supply level0.2100msVCCO2RRamp rate from GND to valid VCCO Bank 2 supply level0.2100msNotes:1.2.VCCINT, VCCAUX, and VCCO supplies to the FPGA can be applied in any order. However, the FPGA’s configuration source (Platform Flash,SPI Flash, parallel NOR Flash, microcontroller) might have specific requirements. Check the data sheet for the attached configurationsource. Apply VCCINT last for lowest overall power consumption (see UG331 chapter "Powering Spartan-3 Generation FPGAs" for moreinformation).To ensure successful power-on, VCCINT, VCCO Bank 2, and VCCAUX supplies must rise through their respective threshold-voltage ranges withno dips at any point.Table 7: Supply Voltage Levels Necessary for Preserving CMOS Configuration Latch (CCL) Contents and RAMDataSymbol12DescriptionMinUnitsVDRINTVCCINT level required to retain CMOS Configuration Latch (CCL) and RAM data1.0VVDRAUXVCCAUX level required to retain CMOS Configuration Latch (CCL) and RAM data2.0Vwww.xilinx.comDS529 (v2.1) December 18, 2018

DC and Switching CharacteristicsGeneral Recommended Operating ConditionsTable 8: General Recommended Operating ConditionsSymbolTJDescriptionJunction –40–85 C–100 CVCCINTInternal supply voltage1.141.201.26VVCCO (1)Output driver supply voltage1.10–3.60VVCCAUXAuxiliary supply voltage(2)VCCAUX 2.52.252.502.75VVCCAUX 3.33.003.303.60VPCI IOSTANDARD–0.5–VCCO 0.5VIP or IO #All otherIOSTANDARDs IO Lxxy # putvoltage(3)Input signal transition time(5)Notes:1.2.3.4.5.This VCCO range spans the lowest and highest operating voltages for all supported I/O standards. Table 11 lists the recommended VCCOrange specific to each of the single-ended I/O standards, and Table 13 lists that specific to the differential standards.Define VCCAUX selection using CONFIG VCCAUX constraint.See XAPP459, “Eliminating I/O Coupling Effects when Interfacing Large-Swing Single-Ended Signals to User I/O Pins.”For single-ended signals that are placed on a differential-capable I/O, VIN of –0.2V to –0.5V is supported but can cause increased leakagebetween the two pins. See Parasitic Leakage in UG331, Spartan-3 Generation FPGA User Guide .Measured between 10% and 90% VCCO. Follow Signal Integrity recommendations.DS529 (v2.1) December 18, 2018www.xilinx.com13

DC and Switching CharacteristicsGeneral DC Characteristics for I/O PinsTable 9: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins (1)SymbolIL(2)IHSDescriptionTest ConditionsMinTypMaxUnitsLeakage current at User I/O,input-only, dual-purpose, anddedicated pins, FPGA poweredDriver is in a high-impedance state,VIN 0V or VCCO max, sample-tested–10– 10µALeakage current on pins duringhot socketing, FPGA unpoweredAll pins except INIT B, PROG B, DONE, and JTAGpins when PUDC B 1.–10– 10µAINIT B, PROG B, DONE, and JTAG pins or otherpins when PUDC B 0.IRPU(3)RPU(3)IRPD(3)RPD(3)Current through pull-up resistorat User I/O, dual-purpose,input-only, and dedicated pins.Dedicated pins are powered byVCCAUX.Equivalent pull-up resistor valueat User I/O, dual-purpose,input-only, and dedicated pins(based on IRPU per Note 3)VIN GNDVCCO or VCCAUX 3.0V to 3.6V–151–315–710µAVCCO or VCCAUX 2.3V to 2.7V–82–182–437µAVCCO 1.7V to 1.9V–36–88–226µAVCCO 1.4V to 1.6V–22–56–148µAVCCO 1.14V to 1.26V–11–31–83µAVCCO 3.0V to 3.6V5.111.423.9kΩVCCO 2.3V to 2.7V6.214.833.1kΩVCCO 1.7V to 1.9V8.421.652.6kΩVCCO 1.4V to 1.6V10.828.474.0kΩVCCO 1.14V to 1.26V15.341.1119.4kΩVCCAUX 3.0V to 3.6V167346659µA100225457µAVIN 3.0V to 3.6V5.510.420.8kΩVIN 2.3V to 2.7V4.17.815.7kΩVIN 1.7V to 1.9V3.05.711.1kΩVIN 1.4V to 1.6V2.75.19.6kΩVIN 1.14V to 1.26V2.44.58.1kΩVIN 3.0V to 3.6V7.916.035.0kΩVIN 2.3V to 2.7V5.912.026.3kΩVIN 1.7V to 1.9V4.28.518.6kΩVIN 1.4V to 1.6V3.67.215.7kΩVIN GNDCurrent through pull-downresistor at User I/O,dual-purpose, input-only, anddedicated pins. Dedicated pinsare powered by VCCAUX.VIN VCCOEquivalent pull-down resistorvalue at User I/O, dual-purpose,input-only, and dedicated pins(based on IRPD per Note 3)VCCAUX 3.0V to 3.6VVCCAUX 2.25V to 2.75VVCCAUX 2.25V to 2.75VVIN 1.14V to 1.26VIREFVREF current per pinCINInput capacitanceRDTResistance of optional differentialtermination circuit within adifferential I/O pair. Not availableon Input-only pairs.µAAdd IHS IRPU3.06.012.5kΩAll VCCO levels–10– 10µA–––10pFVCCO 3.3V 10%LVDS 33,MINI LVDS 33,RSDS 3390100115ΩVCCO 2.5V 10%LVDS 25,MINI LVDS 25,RSDS 2590110–ΩNotes:1.2.3.14The numbers in this table are based on the conditions set forth in Table 8.For single-ended signals that are placed on a differential-capable I/O, VIN of –0.2V to –0.5V is supported but can cause increased leakagebetween the two pins. See "Parasitic Leakage" in UG331, Spartan-3 Generation FPGA User Guide .This parameter is based on characterization. The pull-up resistance RPU VCCO / IRPU. The pull-down resistance RPD VIN / IRPD.www.xilinx.comDS529 (v2.1) December 18, 2018

DC and Switching CharacteristicsQuiescent Current RequirementsTable 10: Quiescent Supply Current nQuiescent VCCINT supply currentQuiescent VCCO supply currentQuiescent VCCAUX supply eNotes:1.2.3.4.5.The numbers in this table are based on the co

The Spartan-3A FPGAs are part of the Extended Spartan-3A family, which also include the non-volatile Spartan-3AN and the higher density Spartan-3A DSP FPGAs. The Spartan-3A family builds on the success of the earlier Spartan-3E and Spartan-3 FPGA families. New features improve

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A majority of the pins on a Spartan-3 FPGA are gen-eral-purpose, user-defined I/O pins. There are, however, up to 12 different functional types of pins on Spartan-3 pack-ages, as outlined in Table 1 . In the package footprint draw-ings that follow, the individual pins are color-coded according to pin type as in the table. 0109 Spartan-3 FPGA .

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Spartan-3 Starter Kit Board User Guide www.xilinx.com 7 UG130 (v1.1) May 13, 2005 1-800-255-7778 R Chapter 1 Introduction The Xilinx Spartan-3 Starter Kit provides a low-cost, easy-to-use development and evaluation platform for Spartan-3 FPGA designs. Key Components and Features Figure 1-1 shows the Spartan-3 Starter Kit board, which includes .

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learn essential blues shuffle riffs on guitar. There are 10 riffs in this section, 5 in open position to get you started, and 5 with barre chords to move around the fretboard in different keys. These riffs can be used over any blues song you jam on, which you choose depending on the groove, tempo, and feel of the tune.