High Density Interconnect

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HD IHig h D e n s it y In t e rc o n n e c tO le Kris t ia n Ha m re Sø rlieUiO , 0 2/0 4 -20 19w w w .rd -d a t a re s p o n s .n o1

AGEND A1.2.3.4.5.In t ro d u c t io n t o HD IUs in g HD I in c irc u it d e s ig nUs e o f HD I in a p ro je c tLe s s o n s le a rn e dCo n c lu s io n2

What is HDI? High Density Interconnect Advanced PCB technology Simply put:o Smaller vias, both blind and buriedo Smaller traces Can reduce PCB area and layers needed More reliable Becoming more cost effectiveFrom the HDI Handbook3

History of HDI HP FINSTRATE (1984) 32-bit computer1990sUsed in early Sony camcorders (1996)Rapid growth from 20004

Related IPC standards IPC/JPCA-2315: Design Guide for High-density Interconnect Structures and Microvias IPC-2226: Sectional Design Standard for High-density Interconnect (HDI) Printed Boards IPC/JPCA-4104: Qualification and Performance Specification for Dielectric Materials forHigh-density Interconnect Structures (HDI) IPC-6016: Qualification and Performance Specification for High-density Interconnect(HDI) Structures5

IPC-2226 Definition of HDI PCB with finer lines and spaces 100 um Vias are 150 um and capture pads are 400 um Higher connection pad density than conventional PCB ( 20 pads/cm 2)6

IPC-2226 Definition of Microvia Has a capture pad diameter 350 um Has a plated hole with a diameter 150 um formed either by laser ormechanical drilling Hole with an aspect ratio of 1:1 (normal PTH typically 10:1)7

Via types Plated through hole via (PTH): Outer layer to outer layer Blind via: Outer layer to inner layer Buried via: Inner layer to inner layer Microvias8

Via aspect ratio (AR) Defined as the relationship between the diameter of the hole and its length. Usually in the range of 6:1 to 10:1 for PTH 10:1 is the minimum for PTH (lower reliability) 6:1 recommended for highest reliability Thicker board larger vias9

Microvias AR of 1:1 / 1:0.8 Staggered Copper filled (via-in-pad) Stacked Skip BuriedFrom Interrupt Inside: High Density Interconnect - Haldor Husby10

HDI PCB Fabrication processCore - Hot pressed togetherBuried vias filled- 11

PCB fabrication costs Blind Vias ( 20% to 40% fabrication cost) Buried Vias ( 25% to 60% fabrication cost) Micro Vias ( 30% fabrication cost) Back-drilled Vias ( 10% fabrication cost) Via-In-Pad ( 30% fabrication cost) Extra Layers ( 20% fabrication cost (per every two layers)Cost estimates from Xilinx12

IPC-2226 HDI Type I and II Type I: One HDI layer on top and/or bottom withthrough-vias from surface to surface. Type II: One HDI layer on top and/or bottom with buriedvias in the core and may have through-vias connectingthe outer layers from surface to surface.13

IPC-2226 HDI Type III Most used type Two or more HDI layers added to through-vias in thecore or from surface to surface Buried vias Stacked microvias Used on the project described in this presentation14

IPC-2226 HDI Type IV, V and VI Less used Type IV: Passive core substrate with no electrical connecting functions. Type V: Coreless constructions using layer pairs. Type VI: Alternate constructions of coreless construction using layer pairs.Type IVType VType VI15

BGA breakout aspects Route density Cost Signal Integrity Power Integrity16

Breakout patterns Adjacent (dog-bone) Partial via-in-pad Via-in-pad (centered)Dog-bonePartial via-in-padVia-in-pad17

PTH vs Microvia breakout Smaller capture pad Routing of multiple traces 10:1 vs 1:0.8 ARFrom IPC-2226From Interrupt Inside: High Density Interconnect - Haldor Husby18

How many signal layers are needed?BGA Pitch 0.8mm - 20 x 20 rowsStandard PTH, dogbone technique“Dogbone” fan out19From the Wurth HDI Webinar

How many signal layers are needed?BGA Pitch 0.8mm - 20 x 20 rowsMicrovia, via in pad allows two tracks between the viasVia in padNote: Example above requires stacked microvias, which adds some additional cost and affects overall reliabilityFrom the Wurth HDI Webinar20

Not just for BGA.QFN with PTHQFN with Microvia (via in pad)From the Wurth HDI Webinar21

High speed / signal integrity HDI instead of expensive high frequency material Via in pads, shorter trace lengths Remove via stubs Avoid backdrilling of viasFrom the Wurth HDI Webinar22

Reliability Vias especially important Ranked most robust to least:1. Micro via2. Staggered microvia3. Through hole via4. Stacked microvia5. Blind via6. Buried viaThermal expansion of PCBmaterial (ie during reflow) - From Haldor Husby Reliability presentation23

Via-in-pad filling Gassing during reflow caused by an unfilled via-in-pad, causing excessive package movement Can be prevented by precise control of flux/solder paste and reflow temperature profile Or by copper/epoxy filling (extra cost)From the Wurth HDI Webinar24

Acoustic sensor project Acoustic data measurement Record and store acoustic data through multiple sensors Continuous operation for several weeks Several terabytes of data Schematic by Data Respons, PCB layout by Asian company25

Functional block diagram Acoustic Data Collection module Xilinx Ultrascale SoC 32 transducers LPDDR4 eMMC, QSPI Ethernet, PCIe26

Proposed floorplan 110mm x 250 mm 5000 components Very high density board Big challenge for Asian company27

PCB Specifications 14 layer FR-4 L1-L2 & L2-L3 and symmetric on bottom layers. Type III HDI No stacked microvia or microvia on buried via(reliability) Outer vias filled and capped (allows via-in-pad) Buried microvias not filled or capped28

SoC BGA Breakout 0.8mm pitch 28x28, 784 pin BGA Ground and VCC pins sprinkled aroundXilinx SoC pinout29

PCB layout process Communication primarily through ConfluenceNo direct contact with PCB manufacturerNCAB HDI PCB design rulesLanguage barrierLayout comments in ConfluenceBGA breakout mix of via-in-pad and buried viasOverworked layout designersTop LayerLayer 3Layer 430

Asian PCB manufacturing issues Chinese HDI manufacturers overloaded (bitcoin craze) Small prototype runs was a low priority 5 weeks lead time Failed to meet the required10% accuracy of impedance All boards scrapped without question.31

NCAB manufacturing issues European (Macedonia) vendor 10 days production time Fault in the final step of the manufacturing process Wrong parameters on the laser drilling of the microvias caused short circuits between layers Even when following NCABs own design rules, the manufacturing process still failed Second attempt succeeded32

Lessons learned PCB manufacturing capabilities needed Running dialog with layout designer and PCB manufacturer is vital Dense and complex PCB, but in theory not difficult to produce Even fairly conservative designs can fail The HDI standard is not yet standard Each manufacturer have their own processes33

Conclusion The HDI process is under development Close cooperation between schematic designer, layout designer and PCBmanufacturer is needed to decrease cost and improve reliability34

Recommended reading The HDI Handbook - Happy Holden et. al HDI Webinars - Wurth BGA Breakouts and Routing - Charles Pfeil HDI Design Guidelines - NCAB HDI Layer Stackups for Large Dense PCBs - Happy Holden & Charles Pfeil IPC-2226 and other HDI related IPC standards35

0.5mm, 0.4mm, 0.3mm.0.4mm is becoming more and more common, with 0.3mm on the horizon(0.3mm already used in telecom industry.)0402 footprint - 36

Smartphone trendIphone 1 (2007)Iphone X (2018)37

Sources Unfilled via-in-pads: http://www.ti.com/lit/an/spraav1b/spraav1b.pdf PTH vs Microvia: https://www.eetimes.com/author.asp?section id 36&doc id 1320862 Iphone 1 vs Iphone X: phone-x-original-iphone/ 0.3mm BGA pitch: https://www.hotwires.net/?tag 0-3mm-bga Wurth HDI Design Guidelines: ia/04 leiterplatte/2017 2/dg poster 2/170125 WE DesignGuide HDI Poster EN web.pdf Microvia image: https://www.lpkfusa.com/products/microvia drilling/ Via types: https://www.allpcb.com/pcb/vias.html HDI in the Iphone X: ce-iphone-x/ A11 InFO stacked chip: -iphone-7/ Wurth HDI webinar series: nare/archiv/microvia hdi webinar/webinar archiv 16.php HDI PCB manufacturing: cuit-boards.html38

Q u e s t io n s ?39

A smarter solution starts from insidew w w .rd -d a t a re s p o n s .n o40

Design Guide for High-density Interconnect Structures and Microvias IPC-2226: Sectional Design Standard for High-density Interconnect (HDI) Printed Boards IPC/JPCA-4104: Qualification and Performance Specification for Dielectric Materials for High-density Interconnect Structures (HDI) IPC-6016:

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