UEFI Debug With Intel Architectural Event Trace

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presented byUEFI Debug with Intel ArchitecturalEvent TraceUEFI 2021 Virtual PlugfestFebruary 25, 2021Presented by Alan Sguigna, ASSET InterTech, Inc.www.uefi.org1

Debug vs Trace Debug (Static)– Run-control (Break, Halt, Go)– Code Walking (stepping andrunning to a break) Trace (Dynamic)– Root causing more obscure (hardto find) bugs– These are the few bugs that reallyblow up the schedule– Finding these bugs is where Traceshineswww.uefi.org4

“New” Intel Trace Features Instruction Trace (Intel Processor Trace) Event Trace (Intel Trace Hub)www.uefi.org5

Intel Trace Hub Logic that comprises trace sources, aglobal hub with timestamp, tracedestinations, and a trigger unit A sink for writes from cores and anyother trace sources Acts as a PCI device, and alignedwith industry standards Trace destinations include:– MTB (8kB, out of reset)– System Memory (after MRC)– Direct Connect Interface (out ofreset, supports streaming trace)www.uefi.org6

AETEvent TypeHW/SW InterruptIRETExceptionMSRPower ManagementIOSGXCODE BPDATA BPFIXED INTSW POWERWBINVDEvent SubTypesHW INTRIRETExceptionRDMSR, WRMSRPOWER ENTRY, POWER EXITPORT IN, PORT OUT, PORT IN ADDRAEX, EENTER, ERESUME, EEXITCODE BPDATA BPSMI, RSM, NMIMONITOR/MWAITWBINVD BEGIN, WBINVD ENDwww.uefi.orgDescriptionHW interrupt traceIRET traceException, fault, trap traceMSR tracePower managementIO traceSGX traceCode breakpoint traceData breakpoint“Fixed” interrupt traceMONITOR/MWAIT traceWrite-back invalidate trace7

AET Tips #1 Probe-mode (JTAG) needed to initialize AET – use outside ofprobe mode (i.e. BIOS, device driver) causes #GP. AET is implemented in CPU microcode and does not modify thearchitectural behavior* of the processors – no need toinstrument code!– * Enabling CODE/DATA BP changes the behavior of normalbreakpoints – causes a trace event rather than a debug exception.Great for critical sections of code, concurrency issues, debuggingmemory accesses, etc. This is event trace, not instruction trace - source code/ symbolsnot required (but it’s great if you have them!)www.uefi.org8

AET Tips #2 A Last Branch Record (LBR) instruction trace stack can be added to allevent traces – a fast way to trace back 160 instructions Intel Processor Trace and AET can run concurrently LBR uses MSRs to track from address and to address pairs, so operates out of reset –no need for system memoryIPT places trace data in system memoryOn Ice Lake processors, both AET LBR tracing and Intel Processor Tracecan be enabled at the same timeAET using XDP access became available initially on Skylake Client andServerAET Streaming through DCI (USB) first became available on Ice Lake Client(not available on Purley or Whitley platforms)www.uefi.org9

Other Trace Hub Trace SW/FW Trace– Replacement for printf– Avoids backpressurefrom serial port– Great for “Heisenbugs” CSME (ManagementEngine) All timestamped andcorrelated*www.uefi.orgSW/FW Trace timestamp correlation onlyavailable on later silicon.10

Demo ConfigurationSourcePoint debugger“Special” USB cableIntel DesignInToolsIce Lake Clientwww.uefi.org11

Demowww.uefi.org12

Call to Action Take advantage of open source UEFIlearning/ development opportunities– Debugging Intel Firmware using DCI & USB3.0– Advanced Capabilities of ArchitecturalEvent Tracewww.uefi.org13

Questions?www.uefi.org14

More Questions?Following today’s webinar, join the live, interactiveWebEx Q&A for the opportunity to chat with thepresenterVisit this link to attend: https://bit.ly/38JIx9RMeeting number (access code): 126 016 9253Meeting password: UEFIForum (83343678 from phonesand video systems)www.uefi.org15

Thanks for attending the UEFI 2021 Virtual PlugfestFor more information on UEFI Forum and UEFISpecifications, visit http://www.uefi.orgpresented bywww.uefi.org16

Intel Processor Trace and AET can run concurrently IPT places trace data in system memory On Ice Lake processors, both AET LBR tracing and Intel Processor Trace can be enabled at the same time AET using XDP acces

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