Combinational Circuit Design: Practice 1. Derivation Of .

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Outline1.2.3.4.5.Combinational Circuit Design:PracticeRTL Hardware Designby P. ChuChapter 71Derivation of efficient HDL descriptionOperator sharingFunctionality sharingLayout-related circuitsGeneral circuitsRTL Hardware Designby P. Chu Circuit complexity of VHDL operatorsvaries Arith operators– Research to find an efficient design(“domain knowledge”)– Develop VHDL code that accuratelydescribes the design– Large implementation– Limited optimization by synthesis software “Optimization” can be achieved by“sharing” in RT level coding Wrong way:– Operator sharing– Functionality sharing– Write a C program and covert it to HDLRTL Hardware Designby P. ChuChapter 72Sharing1. Derivation of efficient HDL description Think “H”, not “L”, of HDL Right way:Chapter 73An example 0.55 um standard-cellCMOS implementationRTL Hardware Designby P. ChuChapter 742. Operator sharing– “value expressions” in priority network andmultiplexing network are mutually exclusively:– Only one result is routed to output– Conditional sig assignment (if statement)sig name value expr 1 when boolean expr 1 elsevalue expr 2 when boolean expr 2 elsevalue expr 3 when boolean expr 3 else.value expr n;RTL Hardware Designby P. ChuChapter 75RTL Hardware Designby P. ChuChapter 761

Example 1– Selected sig assignment (case statement) Original code:with select expression selectsig name value expr 1 when choice 1,value expr 2 when choice 2,value expr 3 when choice 3,.value expr n when choice n;RTL Hardware Designby P. ChuChapter 7r a b when boolean exp elsea c; Revised code:src0 b when boolean exp elsec;r a src0;7RTL Hardware Designby P. ChuChapter 78Example 2 Original code:Area: 2 adders, 1 muxDelay:RTL Hardware Designby P. Chuprocess(a,b,c,d,.)beginif boolean exp 1 thenr a b;elsif boolean exp 2 thenr a c;elser d 1;end ifend process;Area: 1 adder, 1 muxDelay:Chapter 79RTL Hardware Designby P. ChuChapter 710 Revised code:process(a,b,c,d,.)beginif boolean exp 1 thensrc0 a;src1 b;elsif boolean exp 2 thensrc0 a;src1 c;elsesrc0 d;src1 "00000001";end if;end process;r src0 src1;RTL Hardware Designby P. ChuChapter 7Area:2 adders, 1 inc, 2 mux11RTL Hardware Designby P. ChuArea:1 adder, 4 muxChapter 7122

Example 3 Original code:with sel selectr a b when "00",a c when "01",d 1 when others; Revised code:with sel exp selectsrc0 a when "00" "01",d when others;with sel exp selectsrc1 b when "00",c when "01","00000001" when others;r src0 src1;RTL Hardware Designby P. ChuChapter 7Area:2 adders, 1 inc, 1 mux13RTL Hardware Designby P. ChuArea:1 adder, 2 muxChapter 714Example 4 Original code:process(a,b,c,d,.)beginif boolean exp thenx a b;y (others '0');elsex (others '1');y c d;end if;end process;RTL Hardware Designby P. ChuChapter 7Area:2 adders, 2 mux15RTL Hardware Designby P. ChuChapter 716 Revised code:beginif boolean exp thensrc0 a;src1 b;x sum;y (others '0');elsesrc0 c;src1 d;x (others '1');y sum;end if;end process;sum src0 src1;RTL Hardware Designby P. Chu Area: 1 adder, 4 mux Is the sharing worthwhile?– 1 adder vs 2 mux– It depends . . .Chapter 717RTL Hardware Designby P. ChuChapter 7183

Summary3. Functionality sharing– A large circuit involves lots of functions– Several functions may be related and havecommon characteristics– Several functions can share the same circuit.– Done in an “ad hoc” basis, based on theunderstanding and insight of the designer (i.e.,“domain knowledge”)– Difficult for software it since it does not know the“meaning” of functions Sharing is done by additional routingcircuit Merit of sharing depends on thecomplexity of the operator and the routingcircuit Ideally, synthesis software should do thisRTL Hardware Designby P. ChuChapter 719e.g., add-sub circuitRTL Hardware Designby P. ChuChapter 7RTL Hardware Designby P. ChuChapter 720 Observation: a – b can be done by a b’ 121RTL Hardware Designby P. ChuChapter 72223RTL Hardware Designby P. ChuChapter 724 Manual injection of carry-in: Append an additional bit in right (LSB):RTL Hardware Designby P. ChuChapter 74

e.g., sign-unsigned comparatorRTL Hardware Designby P. ChuChapter 7Binary wheel25RTL Hardware Designby P. ChuChapter 72627RTL Hardware Designby P. ChuChapter 72829RTL Hardware Designby P. ChuChapter 730 Observation:– Unsigned: normal comparator– Signed: Different sign bit: positive number is larger Same sign: compare remaining 3 LSBsThis works for negative number, too!E.g., 1111 (-1), 1100 (-4), 1001(-7)111 100 001– The comparison of 3 LSBs can be sharedRTL Hardware Designby P. ChuChapter 7e.g., Full comparatorRTL Hardware Designby P. ChuChapter 75

Read 7.3.3 and 7.3.5RTL Hardware Designby P. ChuChapter 7314. Layout-related circuitsRTL Hardware Designby P. ChuChapter 732– Silicon chip is a “square”– “Two-dimensional” shape (tree or rectangular) isbetter than one-dimensional shape (cascadingchain)– Conditional signal assignment/if statement forma single “horizontal” cascading chain– Selected signal assignment/case statement forma large “vertical” mux– Neither is ideal– After synthesis, placement and routing willderive the actual physical layout of a digitalcircuit on a silicon chip.– VHDL cannot specify the exact layout– VHDL can outline the general “shape”RTL Hardware Designby P. ChuChapter 733RTL Hardware Designby P. ChuChapter 734RTL Hardware Designby P. ChuChapter 735RTL Hardware Designby P. ChuChapter 7366

e.g., Reduced-xor circuitRTL Hardware Designby P. ChuChapter 737RTL Hardware Designby P. ChuChapter 738RTL Hardware Designby P. ChuChapter 739RTL Hardware Designby P. ChuChapter 740e.g., Reduced-xor-vector circuit Comparison of n-input reduced xor– Cascading chain : Area: (n-1) xor gates Delay: (n-1) Coding: easy to modify (scale)– Tree: Area: (n-1) xor gates Delay: log2n Coding: not so easy to modify– Software should able to do theconversion automaticallyRTL Hardware Designby P. ChuChapter 741RTL Hardware Designby P. ChuChapter 7427

Functionality Sharing Direct implementationRTL Hardware Designby P. ChuChapter 743 Direct tree implementationRTL Hardware Designby P. ChuChapter 7RTL Hardware Designby P. ChuChapter 744 “Parallel-prefix” implementation45RTL Hardware Designby P. ChuChapter 746 Comparison of n-input reduced-xor-vector– Cascading chain Area: (n-1) xor gates Delay: (n-1) Coding: easy to modify (scale)– Multiple trees Area: O(n2) xor gates Delay: log2n Coding: not so easy to modify– Parallel-prefix Area: O(nlog2n) xor gates Delay: log2n Coding: difficult to modify– Software is not able to convert cascadingchain to parallel-prefixRTL Hardware Designby P. ChuChapter 747RTL Hardware Designby P. ChuChapter 7488

e.g., Shifter (rotating right) Direct implementationRTL Hardware Designby P. ChuChapter 749RTL Hardware Designby P. ChuChapter 75051RTL Hardware Designby P. ChuChapter 752 Better implementationRTL Hardware Designby P. ChuChapter 7 Comparison for n-bit shifter5. General examples– Direct implementation n n-to-1 mux vertical strip with O(n2) input wiring Code not so easy to modify– Gray code counter– Signed addition with status– Simple combinational multiplier– Staged implementation n*log2n 2-to-1 mux Rectangular shaped Code easier to modifyRTL Hardware Designby P. ChuChapter 753RTL Hardware Designby P. ChuChapter 7549

e.g., Gray code counterRTL Hardware Designby P. ChuChapter 7 Direct implementation55RTL Hardware Designby P. Chu56 binary to gray Observation– Require 2n rows– No simple algorithm for gray code increment– One possible method Gray to binary Increment the binary number Binary to grayRTL Hardware Designby P. ChuChapter 7Chapter 7 gray to binary57RTL Hardware Designby P. ChuChapter 758e.g., signed addition with status Adder with– Carry-in: need an extra bit (LSB)– Carry-out: need an extra bit (MSB)– Overflow: two operands has the same sign but the sum has adifferent sign– Zero– Sign (of the addition result)RTL Hardware Designby P. ChuChapter 759RTL Hardware Designby P. ChuChapter 76010

e.g., simple combinational multiplierRTL Hardware Designby P. ChuChapter 761RTL Hardware Designby P. ChuChapter 762RTL Hardware Designby P. ChuChapter 763RTL Hardware Designby P. ChuChapter 76411

RTL Hardware Design by P. Chu Chapter 7 4 Sharing Circuit complexity of VHDL operators varies Arith operators – Large implementation – Limited optimization by synthesis software “Optimization” can be achieved by “sharing” in RT level coding – Operator sharing – Functionality sharing RTL Hardware Design by P. Chu .

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