C Chapter 2: Machines, Machine S D Languages, And Digital .

CSDA2/eChapter 2: Machines, MachineLanguages, and Digital LogicInstruction sets, SRC, RTN, and the mapping of registertransfers to digital logic circuitsComputer Systems Design and Architecture Second Edition 2004 Prentice Hall

CSDA2/eChapter 2 Topics 2.1 Classification of Computers and Instructions2.2 Kinds and Classes of Instruction Sets2.3 Informal Description of the Simple RISC Computer, SRC Students may wish to consult Appendix C, Assembly andAssemblers for information about assemblers and assembly.2.4 Formal Description of SRC using Register Transfer Notation(RTN)2.5 RTN Description of Addressing Modes2.6 Register Transfers and Logic Circuits: from Behavior toHardware Students may wish to consult Appendix A, Digital Logic foradditional information about Digital Logic circuits.Computer Systems Design and Architecture Second Edition 2004 Prentice Hall

CSWhat are the components of an ISA?DA2/e Sometimes known as The Programmers Model of the machine Storage cells The Machine Instruction Set The instruction set is the entire repertoire of machine operationsMakes use of storage cells, formats, and results of the fetch/execute cyclei. e. Register TransfersThe Instruction Format General and special purpose registers in the CPUMany general purpose cells of same size in memoryStorage associated with I/O devicesSize and meaning of fields within the instructionThe nature of the Fetch/Execute cycle Things that are done before the operation code is knownComputer Systems Design and Architecture Second Edition 2004 Prentice Hall

CFig. 2.1 Programmer’s Models of VariousSMachinesDA2/eWe saw in Chap. 1 a variation in number and type of storage cellsComputer Systems Design and Architecture Second Edition 2004 Prentice Hall

CSDA2/e What Must an Instruction Specify?Data FlowWhich operation to perform: add r0, r1, r3In CPU registers, memory cells, I/O locations, or part of instructionPlace to store result Ans: Op code: add, load, branch, etc.Where to find the operand or operands add r0, r1, r3add r0, r1, r3Again CPU register or memory cellLocation of next instructionadd r0, r1, r3br endloopThe default is usually memory cell pointed to by program counter—PC:the next instruction in sequenceSometimes there is no operand, or no result, or no next instruction. Canyou think of examples?Computer Systems Design and Architecture Second Edition 2004 Prentice Hall

CS Fig. 2.2 Accessing Memory—Reading from MemoryDA2/eFor a Memory Read:CPU applies desired address to Address lines A0-An-1CPU issues Read command, RMemory returns the value at that address on Data lines D0-Db-1 and assertsthe COMPLETE signalComputer Systems Design and Architecture Second Edition 2004 Prentice Hall

CS Figure 2.2 Accessing Memory—Writing to MemoryDA2/eFor a Memory Write:CPU applies desired address to Address lines A0-An-1 and and data to be written onData lines D0-Db-1CPU issues Write command, WMemory asserts the COMPLETE signal when the data has been written to memory.Computer Systems Design and Architecture Second Edition 2004 Prentice Hall

CSInstructions Can Be Divided into 3 ClassesDA2/e Data movement instructions Arithmetic and logic (ALU) instructions Move data from a memory location or register to another memory locationor register without changing its formLoad—source is memory and destination is registerStore—source is register and destination is memoryChanges the form of one or more operands to produce a result stored inanother locationAdd, Sub, Shift, etc.Branch instructions (control flow instructions) Any instruction that alters the normal flow of control from executing thenext instruction in sequenceBr Loc, Brz Loc2,—unconditional or conditional branchesComputer Systems Design and Architecture Second Edition 2004 Prentice Hall

CSDA2/eTbl. 2.1 Examples of Data MovementInstructionsInst ruct .MOV A, BMeaningMove 16 bits from mem. loc. A to loc. BMachineVAX11lwz R3, AMove 32 bit s from mem. loc. A to reg. R3 PPC601li 3, 455Load the 32 bit integer 455 int o reg. 3MIPS R3000mov R4, doutMove 16 bits from R4 to out port doutDEC PDP11IN, AL, KBDLoad a byt e from in port KBD to accum.Intel PentiumLEA.L (A0), A2 Load address pointed to by A0 into A2 M68000Lots of variation, even with one instruction typeNotice differences in direction of data flow left-to-right or right-to-leftComputer Systems Design and Architecture Second Edition 2004 Prentice Hall

CSDA2/eTbl 2.2 Examples of ALU(Arithmetic and Logic Unit) InstructionsInstructionMULF A, B, Cnabs r3, r1ori 2, 1, 255DEC R2SHL AX, 4Meaningmultiply the 32-bit floating point values atmem loc’ns. A and B, store at CStore abs value of r1 in r3Store logical OR of reg 1 with 255 into reg 2Decrement the 16-bit value stored in reg R2Shift the 16-bit value in reg AX left by 4 bitsMachineVAX11PPC601MIPS R3000DEC PDP11Intel 8086 Notice again the complete dissimilarity of both syntax and semanticsComputer Systems Design and Architecture Second Edition 2004 Prentice Hall

CSDA2/eTbl 2.3 Examples of Branch InstructionsInstructionBLSS A, Tgtbun r2beq 2, 1, 32SOB R4, LoopJCXZ AddrMeaningMachineBranch to address Tgt if the least significantVAX11bit of mem loc’n. A is set (i.e. 1)Branch to location in R2 if result of previousPPC601floating point computation was Not a Number (NAN)Branch to location (PC 4 32) if contentsMIPS R3000of 1 and 2 are equalDecrement R4 and branch to Loop if R4 0DEC PDP11Jump to Addr if contents of register CX 0.Intel 8086Computer Systems Design and Architecture Second Edition 2004 Prentice Hall

CSDA2/eCPU Registers Associated with Flow ofControl—Branch Insts. Program counter usually contains the address of, or "points to" thenext instructionCondition codes may control branchBranch targets may be contained in separate registersProcessor StateC N V ZProgram CounterCondition Cod Branch TargetsComputer Systems Design and Architecture Second Edition 2004 Prentice Hall

CHLL Conditionals Implemented by Control FlowSChangeDA2/e Conditions are computed by arithmetic instructionsProgram counter is changed to execute only instructionsassociated with true conditionsC languageif NUM 5 then SET 7Computer Systems Design and Architecture Second EditionAssembly languageCMP.W #5, NUMBNEL1MOV.W #7, SETL1 .;the comparison;conditional branch;action if true;action if false 2004 Prentice Hall

CSDA2/eCPU Registers may have a “personality” Architecture classes are often based on how where the operandsand result are located and how they are specified by theinstruction.They can be in CPU registers or main ral PurposeRegisters Push PopTopSecond St ack MachineAccumulat orComputer Systems Design and Architecture Second EditionMachineGeneral Regist erMachine 2004 Prentice Hall

CS3, 2, 1, & 0 Address InstructionsDA2/e The classification is based on arithmetic instructions that have two operands and one resultThe key issue is “how many of these are specified by memoryaddresses, as opposed to being specified implicitly”A 3 address instruction specifies memory addresses for both operandsand the result: R Op1 op Op2A 2 address instruction overwrites one operand in memory with theresult: Op2 Op1 op Op2A 1 address instruction has a register, called the accumulator registerto hold one operand & the result (no address needed):Acc Acc op Op1A 0 address uses a CPU register stack to hold both operands andthe result: TOS TOS op SOS where TOS is Top Of Stack, SOS isSecond On Stack)The 4-address instruction, hardly ever seen, also allows the address ofthe next instruction to specified explicitly.Computer Systems Design and Architecture Second Edition 2004 Prentice Hall

CSDA2/eFig. 2.3 The 4 Address Instruction Explicit addresses for operands, result & next instructionExample assumes 24-bit addresses Discuss: size of instruction in bytesComputer Systems Design and Architecture Second Edition 2004 Prentice Hall

CSDA2/e Fig 2.4 The 3 Address InstructionAddress of next instruction kept in a processor state register—the PC(Except for explicit Branches/Jumps)Rest of addresses in instruction Discuss: savings in instruction word sizeComputer Systems Design and Architecture Second Edition 2004 Prentice Hall

CSDA2/e Fig. 2.5 The 2 Address InstructionBe aware of the difference between address, Op1Addr, and data stored at that address,Op1.Result overwrites Operand 2, Op2, with result, ResThis format needs only 2 addresses in the instruction but there is less choice in placing dataComputer Systems Design and Architecture Second Edition 2004 Prentice Hall

CSDA2/eFig. 2.6 1 Address InstructionsWe now needinstructions to loadand storeoperands:LDA OpAddrSTA OpAddr Special CPU register, the accumulator, supplies 1 operand and stores resultOne memory address used for other operandComputer Systems Design and Architecture Second Edition 2004 Prentice Hall

CSDA2/e Fig. 2.7 The 0 Address InstructionUses a push down stack in CPUArithmetic uses stack for both operands. The result replaces them on the TOSComputer must have a 1 address instruction to push and pop operands to andfrom the stackComputer Systems Design and Architecture Second Edition 2004 Prentice Hall

CSDA2/eExample 2.1 Expression evaluation for 3-0address instructions.Evaluate a (b c)*d-e for 3- 2- 1- and 0-address machines. # of instructions & # of addresses both varyDiscuss as examples: size of code in each caseComputer Systems Design and Architecture Second Edition 2004 Prentice Hall

CSDA2/e Fig. 2.8 General Register MachinesIt is the most common choice in today’s general purpose computersWhich register is specified by small “address” (3 to 6 bits for 8 to 64 registers)Load and store have one long & one short address: 1 1/2 addresses2-Operand arithmetic instruction has 3 “half” addressesComputer Systems Design and Architecture Second Edition 2004 Prentice Hall

CSDA2/eReal Machines are Not So Simple Most real machines have a mixture of 3, 2, 1, 0, 1 1/2 addressinstructionsA distinction can be made on whether arithmetic instructionsuse data from memoryIf ALU instructions only use registers for operands and result,machine type is load-store Only load and store instructions reference memoryOther machines have a mix of register-memory and memorymemory instructionsComputer Systems Design and Architecture Second Edition 2004 Prentice Hall

CSDA2/e Addressing ModesAn addressing mode is hardware support for a useful way ofdetermining a memory addressDifferent addressing modes solve different HLL problems Some addresses may be known at compile time, e.g. global vars.Others may not be known until run time, e.g. pointersAddresses may have to be computed: Examples include: Record (struct) components: Array components: variable base(full address) const.(small)const. base(full address) index var.(small)Possible to store constant values w/o using another memory cell bystoring them with or adjacent to the instruction itself.Computer Systems Design and Architecture Second Edition 2004 Prentice Hall

CSDA2/e HLL Examples of Structured AddressesC language: rec - count CountRec C language: v[i] rec is a pointer to a record: full address variablecount is a field name: fixed byte offset, say 24v is fixed base address of array: full address constanti is name of variable index: no larger than array sizeVariables must be contained in registers or memory cellsSmall constants can be contained in the instructionResult: need for “address arithmetic.” V[i]V E.g. Address of Rec - Count is address of Rec offset ofcount.Computer Systems Design and Architecture Second Edition 2004 Prentice Hall

CSDA2/eFig 2.9 Common Addressing Modes a-dComputer Systems Design and Architecture Second Edition 2004 Prentice Hall

CSDA2/eFig 2.9 Common Addressing Modes e-gComputer Systems Design and Architecture Second Edition 2004 Prentice Hall

CSDA2/eFig. 2.10a Example Computer, SRCSimple RISC Computer 32 general purpose registers of 32 bits32 bit program counter, PC and instruction reg., IR232 bytes of memory address spaceComputer Systems Design and Architecture Second Edition 2004 Prentice Hall