Assessment Of Thermal Behavior And Development Of Thermal .
Assessment of Thermal Behavior and Development ofThermal Design Guidelines for Integrated PowerElectronics ModulesByYing Feng PangDissertation submitted to the faculty of the Virginia Polytechnic Institute and StateUniversity in partial fulfillment of the requirements for the degree ofDoctor of PhilosophyInMechanical EngineeringDr. Elaine P. Scott, ChairDr. Robert L. West, Committee MemberDr. Jan Helge Bøhn, Committee MemberDr. Scott T. Huxtable, Committee MemberDr. Jacobus Daniel van Wyk, Committee MemberDr. Marwan U. Bikdash, Committee MemberJanuary 20, 2005Blacksburg, VirginiaKeywords: thermal analysis, thermal modeling, thermal management, integrated cooling,integrated power electronics moduleCopyright 2005, Ying Feng Pang
Assessment of Thermal Behavior and Development of ThermalDesign Guidelines for Integrated Power Electronics ModulesYing Feng PangAbstractWith the increase dependency on electricity to provide correct form of electricityfor lightning, machines, and home and office appliances, the need for the introduction ofhigh reliability power electronics in converting the raw form of electricity into efficientelectricity for these applications is uprising. One of the most common failures in powerelectronics is temperature related failure such as overheating. To address the issue ofoverheating, thermal management becomes an important mission in the design of thepower electronics to ensure the functional power electronics.Different approaches are taken by academia and industry researchers to provideefficient power electronics.In particular, the Center for Power Electronics System(CPES) at Virginia Tech and four other universities presented the IPEM approach byintroducing integrated power electronics modules (IPEM) as standardized units that willenable greater integration within power electronics systems and their end-use application.The IPEM approach increases the integration in the components that make up a powerelectronics system through novel a packaging technique known as Embedded Powertechnology.While the thermal behavior of commonly used packages such as pin grid arrays(PGA), ball grid array (BGA), or quad flat pack (QFP) are well-studied, the influence ofthe Embedded Power packaging architecture on the overall thermal performance of theIPEMs is not well known.This motivates the presentation of this dissertation indeveloping an in-depth understanding on the thermal behavior of the Embedded Powermodules. In addition, this dissertation outlines some general guidelines for the thermalmodeling and thermal testing for the Embedded Power modules. Finally, this dissertationsummarizes a few thermal design guidelines for the Embedded Power modules. Hence,
this dissertation aims to present significant and generalized scientific findings for theEmbedded Power packaging from the thermal perspective.Both numerical and experimental approaches were used in the studies. Threedimensional mathematical modeling and computational fluid dynamics (CFD) thermalanalyses were performed using commercial numerical software, I-DEAS. Experimentswere conducted to validate the numerical models, characterize the thermal performanceof the Embedded Power modules, and investigate various cooling strategies for theEmbedded Power modules. Validated thermal models were used for various thermalanalyses including identifying potential thermal problems, recognizing critical thermaldesign parameters, and exploring different integrated cooling strategies.This research quantifies various thermal design parameters such as thegeometrical effect and the material properties on the thermal performance of theEmbedded Power modules. These parameters include the chip-to-chip distance, thecopper trace area, the polyimide thickness, and the ceramic materials.Since theEmbedded Power technology utilizes metallization bonding as interconnection, specificdesign parameters such as the interconnect via holes pattern and size, the metallizationthickness, as well as the metallization materials were also explored to achieve best resultsbased on thermal and stress analyses.With identified potential thermal problems and critical thermal design parameters,different integrated cooling strategies were studied. The concept of integrated cooling isto incorporate the cooling mechanisms into the structure of Embedded Power modules.The results showed that simple structural modifications to the current Embedded Powermodules can reduce the maximum temperature of the module by as much as 24%.Further improvement can be achieved by employing double-sided cooling to theEmbedded Power modules.Based on the findings from the thermal analyses, general design guidelines weredeveloped for future design of such Embedded Power modules. In addition, thermalmodeling and testing guidelines for the Embedded Power modules were also outlined inthis dissertation.iii
To My ParentsKong Pang and Sz Wui Lee who sow in me the value of education and loveme unconditionallyiv
AcknowledgmentFirst and foremost, I would like to express my deepest gratitude to my academicadvisor and mentor Prof. Elaine Scott for providing me with a great research opportunity.Without her unconditional support in guiding me to conduct and complete this research,this dissertation would never have come into existence. I am grateful to have Dr. RobertWest, Dr. Jan Helge Bøhn, Dr. Scott Huxtable, Dr. Daan van Wyk, and Dr. MarwanBikdash from North Carolina Agriculture and Technical State University as my doctoralcommittee members.I owe them a special note of appreciation for their constantencouragement and expertise throughout my graduate studies.I am indebted to the National Science Foundation and Center for PowerElectronics Systems (CPES) at Virginia Tech for funding this research (under awardnumber EEC-9731677) and providing research facilities.I wish to thank all thecolleagues and friends at CPES including the wonderful staffs for their insightfuldiscussions, guidance, and helps during my stay at CPES. I will always cherish ourfriendships. Special thanks are due to Ben Poe, Jamie Archual, Cathy Hill, and EloiseMcCoy, as well as the friends in Thermal Inversion Computational and Optimization Lab(TICOL): Dion Minter, Sandra Smith, Marie Madden, Scott Gayzik, Caroline Comas,Manu Mital, and Ashvin Mudalia.Many thanks to all the people I have come to know at Virginia Tech andBlacksburg, especially Bob and Esther Youngs, whose friendship and companionship Iwill always enjoy. I owe my sincere appreciation to my family and relatives who havesupported and encouraged me over the years. I am grateful to Ming Luo for his inspiredlove during all these years. Finally, I want to extend my profound appreciation to mybeloved parents for their love, affection, and invaluable support.v
Table of ContentsAbstract .iiDedication .ivAcknowledgment .vTable of Contents .viNomenclature .viiiAcronyms .ixList of Figures .xList of Tables .xiv1. Introduction .11.1. Background—Roles of Power Electronics .11.2. Motivation .21.3. Current Packaging Technology for Power Electronics .91.4. Research Goal and Approach .111.5. Dissertation Outline .132. Literature Review .152.1Packaging Technology for Multi-chip Modules .152.2Component Level Cooling Technologies .222.3Tools for Thermal Prediction and Thermal Test Method .282.4Thermal Design Rules for Multi-chip Modules .302.5Summary .313. Thermal Modeling of IPEMs .323.1IPEM Structure and Packaging Scheme .333.2Basic Finite Element Thermal Modeling of IPEM .363.3Finite Element Models for Numerical Validation .403.4Experimental Setup for Validation of Numerical Models .403.5Evaluation of Numerical Results Against Experimental Data .454. Thermal Behavior Assessment of Integrated Power Electronics Modules (IPEMs).484.1Study I—Thermal Characterizations .484.2Study II—Effect of Chip-to-chip Distance and the Copper Trace Area .52vi
4.3Study III—Selection of DBC Ceramic and Ceramic Carrier Materials .554.4Study IV—Metallization Layer .574.5Study V—Significance of Polyimide Layer .614.6Study VI—Evaluation of Integrated Cooling Mechanisms for IPEMs .625. Results and Discussions .715.1Thermal Characterization .715.2Effect of Chip-to-chip Distance and the Copper Trace Area .755.3Selection of DBC Ceramic and Ceramic Carrier Materials .785.4Metallization Layer .785.5Significance of Polyimide Layer .865.6Evaluation of Integrated Cooling Mechanisms for IPEMs .875.7Summary .1046. Thermal Design Guidelines for IPEMs .1066.1Design for Thermal Performance Concept .1066.2Types of Design Guidelines .1106.3Design Guidelines for Thermal Modeling of Heat Transfer in EmbeddedPower Modules .1126.4Testing Guidelines and Procedures .1166.5Thermal Design Guidelines for Embedded Power Modules .1196.6Summary .1227. Conclusion .1247.1. Contributions .1247.2. Recommendations .130Bibliography .132Appendix A: Thermal Couplings in ESC .139A.1 DC/DC IPEM .140A.2 PFC IPEM .142Appendix B: Publications .145Appendix C: Data Sheet for Papst-Motoren Axial Fan .148Vita .149vii
NomenclatureAarea, m2ttime, sIcurrent, ATtemperature, CKthermal Conductivity, W/m-KVvoltage, Vlthickness, mX sensitivity CoefficientQpower loss, Wβmodel ParameterRresistance, C/Wσuncertainty, CSubscriptsMmeasuredNnominalPpredictedSperturbed (for sensitivity analysis) ambientviii
AcronymsACalternative currentCFDcomputational fluid dynamicsCPEScenter for power electronics systemsCTEcoefficient of thermal expansionDBCdirect bonded copperDCdirect currentESCelectronic system coolingIGBTinsulated gate bipolar transistorIPEMintegrated power electronics moduleIPMintelligent power moduleMOSFETmetal oxide semiconductor field effect transistorPFCpower factor correctionSiCsilicon carbideix
List of FiguresFigure 1.1Functionality, Size, and Cost Driving the Development of ConsumerElectronics .3Figure 1.2Moore’s Law .4Figure 1.3Power Trend for Intel Microprocessor .5Figure 1.4Heat Density Trends and Projections for Information Technology Products.6Figure 1.5Thermal Power Dissipation Summary for Current and Future AutomotiveElectronic Systems .7Figure 1.6Heat Flow in Conventional Multi-chip Package .10Figure 1.7Structural Schematic of Embedded Power Module .11Figure 1.8Increased Performance with the Diversity and Number of Componentsthrough Integration and Miniaturization .13Figure 2.1Different Package Schematic .16Figure 2.2Schematic of Pin Grid Array Package and Its Heat Paths .17Figure 2.3Schematic of Ball Grid Array Package and Its Heat Paths .17Figure 2.4Interconnection Schematic for (a) Wire-bonding and (b) Flipped ChipTechnology .19Figure 2.5Concept of Embedded Power Technology .22Figure 2.6Three Major Phases of Heat Transfer at Component Level .23Figure 3.1Conceptual Structure of Embedded Power Module .33Figure 3.2Pictures of DC/DC and PFC IPEM .36Figure 3.3Solid Models of (a) DC/DC IPEM and (b) PFC IPEM with Location ofInterfaces Modeled as Equivalent Thermal Resistances .39Figure 3.4Numerical Model for Validation Purposes .41Figure 3.5Illustration of Experimental Setup .44Figure 3.6Schematic Symbol for a Generic MOSFET Chip .44Figure 3.7Electrical Terminals for (a) DC/DC IPEM and (b) PFC IPEM .45Figure 3.8Different Effect for Parallel Connection of Parasitic Diodes and MOSFET.45x
Figure 3.9Thermography Images and Simulated Temperature Distributions forDC/DC and PFC IPEM .47Figure 4.1Layout for Case 1-6 Studying the Effect of the Chip-to-chip Distance .53Figure 4.2Study on Copper Trace Layout for Case 7-9 with 6 mm Chip-to-chipDistance .54Figure 4.3Layouts on Chips Locations for Case 10 and Case 11 with 6 mm Chip-tochip Distance .54Figure 4.4Schematic of ALOX Substrate .56Figure 4.5Stress Model and Boundary Conditions for Stress Simulations .58Figure 4.6Three Studied Interconnect Patters: (a) 6 Interconnect Via Holes, (b) 9Interconnect Via Holes, and (c) Rectangular Interconnect Pattern .59Figure 4.7Illustration of Structural Enhancement of PFC IPEM .63Figure 4.8Illustration of Double-sided Cooling for an Active IPEM .64Figure 4.9Schematic of Thermal Clad Substrate .65Figure 4.10Prototypes for Double-sided Cooling Experiments .66Figure 4.11Locations of Thermocouples on the Prototype .67Figure 4.12Placement of the Module during Experiment .68Figure 4.13Illustration of Copper Cap for the PFC IPEM .69Figure 4.14Illustration of Channels on Top of Hotspots for the PFC IPEM .70Figure 5.1Thermal Characterization of DC/DC IPEM .72Figure 5.2Thermal Characterization of PFC IPEM .73Figure 5.3Results for Case 2-6 in Study 1 Compared with Case 1 (Baseline) .76Figure 5.4Thermal Improvements for Case 7-9 in Study 2 Compared to Case 1(Baseline) .76Figure 5.5Thermal Improvements for Case 10 and Case 11 in Study 3 Compared toCase 1 (Baseline) .77Figure 5.6Temperature Contour for Case 9 in Study 2 on Table 4 .77Figure 5.7Results Comparison for Different Ceramic Materials .79Figure 5.8Temperature Rise and Maximum von Mises Stress for Three DifferentInterconnect Patterns .79xi
Figure 5.9Stress Distribution on Top of the Silicon Die and Bottom of Metallization.80Figure 5.10Temperature Distribution on the Metallization for 6 Holes Pattern .81Figure 5.11Temperature Rise and Maximum von Mises Stress for DifferentMetallization Thicknesses .82Figure 5.12von Mises Stress Distributions on Metallization for Baseline Thickness, 4xThickness, and 16x Thickness .82Figure 5.13Trade-offs Between Thermal Performance and ThermomechanicalBehavior for Different Materials .83Figure 5.14Possible Locations for Restraints Specificati
electronics system through novel a packaging technique known as Embedded Power technology. While the thermal behavior of commonly used packages such as pin grid arrays (PGA), ball grid array (BGA), or quad flat pack (QFP) are well-studied, the influence of the Embedded Power packaging architecture on the overall thermal performance of the
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