Verilog-A Language Reference Manual

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Verilog-ALanguage Reference ManualAnalog Extensions to Verilog HDLVersion 1.0August 1, 1996Open Verilog International

No part of this work covered by the copyright hereon may be reproduced or used in any form or by any means -- graphic, electronic, or mechanical, including photocopying, recording, taping, or information storage andretrieval systems --- without the prior written approval of Open Verilog International.Additional copies of this manual may be purchased by contacting Open Verilog International at the addressshown below.NoticesThe information contained in this draft manual represents the definition of the Verilog-A hardware descriptionlanguage as proposed by OVI (Analog TSC) as of January, 1996. Open Verilog International makes no warranties whatsoever with respect to the completeness, accuracy, or applicability of the information in this draft manual to a user’s requirements. This language is not yet fully defined and is subject to change. It is suitable forlearning how to do analog modeling and as a vehicle for providing feedback to the standards committee. VerilogA should not be used for production design and development.Open Verilog International reserves the right to make changes to the Verilog-A hardware description languageand this manual at any time without notice.Open Verilog International does not endorse any particular simulator or other CAE tool that is based on the Verilog-A hardware description language.Suggestions for improvements to the Verilog hardware description language and/or to this manual are welcome.They should be sent to the address below.Information about Open Verilog International and membership enrollment can be obtained by inquiring at theaddress below.Published as:Published by:Verilog-A Language Reference ManualVersion 1.0, August 1, 1996.Open Verilog International15466 Los Gatos Blvd., #109071Los Gatos, CA 95032Phone: (408) 358-9510Fax: (408) 358-3910Printed in the United States of America.Verilog is a registered trademark of Cadence Design Systems, Inc.

The following people contributed to the creation, editing and review of this document.Ramana AisolaMotorolaaisola@analog-dse.sps.mot.comKevin CameronMeta-Softwarekevinc@metasw.comDan FitzPatrickApteqdkf@apteq.comVassilios GerousisMotorolagerousis@chdasic.sps.mot.comIan GetreuAnalogyiang@analogy.comKim HaileyMeta Softwarekimh@metasw.comKen KundertCadencekundert@cadence.comOskar LeutholdGEC Plessyleuthold@sv.gpsemi.comS. Peter LiebmannMeta Softwarepeterl@metasw.comIra MillerMotorolamiller@analog-dse.sps.mot.comTom ReederViewlogictreeder@viewlogic.comSteffen RochelAnacad/Mentorsteffen rochel@mentorg.comJames SpotoCadencespoto@cadence.comRichard TrihyCadencetrihy@cadence.comYatin TrivediSEVA Technologiestrivedi@seva.comAlex ZamfirescuVeribesta.zamfirescu@ieee.org

Table of ContentsVerilog-A HDL OverviewOverview . 1-1Systems . 1-1Conservative systems . 1-2Kirchhoff’s laws . 1-3Signal-flow systems . 1-4Mixed systems . 1-5Natures, disciplines and nodes . 1-7Conventions used in this document . 1-8Contents . 1-9Lexical TokensLexical tokens . 2-1White space . 2-1Comments . 2-1Operators . 2-2Numbers . 2-2Integer constants . 2-2Real constants . 2-3Units for real constants . 2-4Conversion . 2-4Identifiers, keywords, and system names . 2-5Escaped identifiers . 2-5Keywords . 2-5Version 1.0Verilog-A Language Reference Manualv

System tasks and functions . 2-7Compiler directives . 2-7Data TypesInteger and real datatypes . 3-1Operators and real numbers . 3-2Conversion . 3-2Parameters . 3-2Type Specification . 3-4Value Range Specification . 3-4Nodes . 3-5Natures . 3-5Disciplines . 3-9Node Declaration . 3-11Implicit Nodes . 3-13Node Compatibility . 3-13Branches . 3-15Branch Declaration . 3-15Accessing Node and branch Signals and Attributes . 3-16Namespace . 3-17Nature and Discipline . 3-17Node . 3-17Branch . 3-18ExpressionsOperators . 4-1Operators with real operands . 4-2Binary operator precedence . 4-2Expression evaluation order . 4-3Arithmetic operators . 4-4Relational operators . 4-4Equality operators . 4-5Logical operators . 4-5Version 1.0Verilog-A Language Reference Manualvi

Bit-wise operators . 4-6Shift operators . 4-7Conditional operator . 4-7Event or . 4-7Built-In Mathematical Functions . 4-7Standard Mathematical Functions . 4-8Transcendental Functions . 4-8Environment Parameters . 4-9Error Handling . 4-9Signal Access Functions . 4-9Analog Operators . 4-10Restrictions on analog operators . 4-11Analog Operators and Tolerances . 4-11Time Derivative Operator . 4-11Time Integral Operator . 4-12Delay Operator . 4-13Transition Filter . 4-13Slew Filter . 4-16Laplace Transform Filters . 4-17Z-Transform Filters . 4-19Limited Exponential . 4-22Analysis Dependent Functions . 4-22Analysis . 4-22AC Stimulus . 4-23Noise . 4-24User defined functions . 4-25Defining a function . 4-25Returning a value from a function . 4-27Calling a function . 4-27SignalsAnalog Signals . 5-1Access Functions . 5-1Probes and Sources . 5-2Version 1.0Verilog-A Language Reference Manualvii

Examples . 5-3Port Branches . 5-6Switch Branches . 5-7Unassigned Sources . 5-8Contribution statements . 5-8Branch Contribution Statements . 5-8Indirect Branch Assignments . 5-9Analog BehaviorAnalog procedural block . 6-1Null statement . 6-2Block statement . 6-2Block names . 6-3Procedural assignment . 6-3Conditional statement . 6-4If-else-if Construct . 6-5Case statement . 6-5Constant expression in case statement . 6-6Looping statements . 6-6Generate statement . 6-7Analog events . 6-8Event detection . 6-9Event OR operator . 6-9Global events . 6-10Monitored events . 6-11Announcing Discontinuity . 6-13Time related functions . 6-15Bounding the time step . 6-15Last Crossing Function . 6-16Hierarchical StructuresModules . 7-1Top-level modules . 7-2Version 1.0Verilog-A Language Reference Manualviii

Module instantiation . 7-3Overriding module parameter values . 7-5Defparam statement . 7-5Module instance parameter value assignment by order . 7-6Module instance parameter value assignment by name . 7-7Parameter override precedence . 7-7Parameter dependence . 7-8Ports . 7-8Port association . 7-8Port declarations . 7-9Connecting module ports by ordered list . 7-10Connecting module ports by name . 7-11Port connection rules . 7-11Inheriting Port Natures . 7-12Multi-disciplinary example . 7-12Hierarchical names . 7-13Scope rules . 7-15Scheduling SemanticsOpen IssuesSyntaxKeywordsSystem Tasks and FunctionsCompiler DirectivesStandard DefinitionsGlossaryIndexVersion 1.0Verilog-A Language Reference Manualix

Version 1.0Verilog-A Language Reference Manualx

OverviewVerilog-A HDL OverviewSection 1Verilog-A HDL Overview1.1OverviewThis Verilog-A Hardware Description Language (HDL) language reference manualdefines a behavioral language for analog systems. Verilog-A HDL is derived from theIEEE 1364 Verilog HDL specification. This document is intended to cover the definitionand semantics of Verilog-A HDL as proposed by Open Verilog International (OVI).The intent of Verilog-A HDL is to let designers of analog systems and integrated circuitscreate and use modules that encapsulate high-level behavioral descriptions as well asstructural descriptions of systems and components. The behavior of each module can bedescribed mathematically in terms of its terminals and external parameters applied to themodule. The structure of each component can be described in terms of interconnectedsub-components. These descriptions can be used in many disciplines such as electrical,mechanical, fluid dynamics, and thermodynamics.Verilog-A HDL is defined to be applicable to both electrical and non-electrical systemsdescription. It supports conservative and signal-flow descriptions by using theterminology for these descriptions using the concepts of nodes, branches, and ports. Thesolution of analog behaviors which obey the laws of conservation fall within thegeneralized form of Kirchhoff’s Potential and Flow laws (KPL and KFL). Both of theseare defined in terms of the quantities associated with the analog behaviors.1.2SystemsA system is considered to be a collection of interconnected components that are actedupon by a stimulus and produce a response. The components themselves might also besystems, in which case a hierarchical system is defined. If a component does not haveany sub-components, then it is considered a primitive component. Each primitivecomponent connects to one or more nodes. The behavior of each component is definedin terms of signal values at each node.The components connect to nodes through ports to build hierarchy as shown infigure 1-1.Version 1.0Verilog-A Language Reference Manual1-1

SystemsVerilog-A HDL OverviewPortsModuleNodeModuleModuleFigure 1-1: Components connect to nodes through ports.In order to simulate systems, it is necessary to have a complete description of the systemand all of its components. Descriptions of systems are given structurally. That is, thedescription of a system contains instances of components and how they areinterconnected. Descriptions of primitive components are given behaviorally. That is, amathematical description is given that relates the signals at the ports of the component.1.2.1Conservative systemsAn important characteristic of conservative systems is that there are two valuesassociated with every node (and hence every terminal) - the potential (also known as theacross value, or the voltage in electrical systems) and the flow (the through value, or thecurrent in electrical systems). The potential of the node is shared with all terminalsconnected to the node in such a way that all terminals see the same potential. The flowis shared such that flow from all terminals at a node must sum to zero. In this way, thenode acts as an infinitesimal point of interconnection in which the potential is the sameeverywhere on the node and on which no flow can accumulate. Thus, the node embodiesKirchhoff's Potential and Flow Laws (KPL and KFL). When a component connects to anode through a conservative terminal, it may either affect, or be affected by, either thepotential at the node, and/or the flow onto the node through the terminal.With conservative systems it is also useful to define the concept of a branch. A branchis a path of flow between two nodes through a component. Every branch has anassociated potential (the potential difference between the two nodes) and flow.A behavioral description of a conservative component is constructed as a collection ofinterconnected branches. The constitutive equations of the component are formulated asto relate the branch potentials and flows. In the probe/source approach, the branchpotential or flow is specified as a function of branch potentials and flows. If the branchpotential and flow are left unspecified, then the branch acts as a probe. In this case, if thebranch flow is used in an expression, the branch potential is forced to zero. Otherwisethe branch flow is assumed to be zero and the branch potential is available for use in anexpression. Using both the potential and flow of a 'probe' branch in an expression is notVersion 1.0Verilog-A Language Reference Manual1-2

SystemsVerilog-A HDL Overviewallowed. Nor is specifying both the branch potential

Verilog-A HDL Overview 1.1 Overview This Verilog-A Hardware Description Language (HDL) language reference manual defines a behavioral language for analog systems. Verilog-A HDL is derived from the IEEE 1364 Verilog HDL specification. This document is intended to cover the definition and semantics of Verilog-A HDL as proposed by Open Verilog .

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