HDL Coder Modeling Guidelines (R2015b)

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HDL Coder Modeling Guidelines (R2015b)0. Introduction0.1 About this guideThis is a set of recommended guidelines for creating Simulink models, MATLAB function blocks, and Stateflow chartsfor use with HDL Coder. Because HDL Coder generates code that will target hardware, some amount of hardwarearchitectural guidance must be provided as part of the design. There are additional guidelines for optimizing thespeed and area of the design implemented in hardware. Where noted, the guidelines also reflect industry-standardHDL guidelines such as those from STARC.0.1 Recommended HDL Coder design workflowMATLAB /Simulink1.Reference modeldesignDesign and verify the floating-point functional algorithm.2.Implementationmodel creationAdd hardware awareness, being mindful of clocking, datatypes, resource mapping. Use HDL-supported blocks.Typically Simulink is the top-level and primary entry pointfor this model, though MATLAB function blocks andStateflow charts may be onvert floating point data to fixed-point for hardwareimplementation. Fixed-Point Designer utilizes simulation toprovide feedback and guidance on error tolerance andmin/max values.HDL Coder4.HDL generationproperties andpreferencesSet optimization preferences such as pipelining or resourcesharing.5.HDL generationreadiness checkChecks the model for compliance and consistency withHDL code generation rules.6.HDL generationGenerates VHDL or Verilog.HDL Verifier EDA verification7.HDL simulation andverificationValidate that the fully-timed bit-accurate HDL still meetsfunctional requirements.EDA synthesisand place & route8.FPGA/ASICimplementationImplement the generated HDL on the target hardware.0.2 Target languageHDL Coder generates synthesizable VHDL or Verilog. VHDL is the default. The target language can be set a numberof different ways, the most common being Simulink Configuration Parameters HDL Code Generation pane or theSimulink HDL Workflow Advisor as follows:

0.3 Definition of termsSubsystems: Atomic subsystem Variant subsystem Enabled Subsystem Triggered Subsystem Virtual subsystemNon-virtual subsystemDesign concepts: Base rate DUT Registers/Flip-Flops Global reset type Local resetSignals: Matrix signal Bus signal Vector signal Frame-based signalModels: Model Variant Model referencing Validation model Generated Model Cosimulation model HDL modelparameters HDL block properties HDL-supported blocks Configuration parameterImplementation: Floating-point to fixed-point conversion Floating-point mapping Sharing Streaming Pipelining DSPslice/block0.4 Guideline categoriesThe guidelines are categorized by level of compliance requirements:MandatoryDefinitionImpactNot following this rulewill result in an errorand code cannot begenerated.Code generation orlogic synthesis cannotbe performed.Strongly RecommendedCode can be generatedbut it will likely mapinefficiently to hardwareor may not match thehigh-level functionality.Poor quality of resultsRecommendedInformativeImproves quality,readability, or ease ofimplementation.Guideline to provideadditionalinformation.May impact efficiencyor ease-of-usedownstream.None

Index of HDL Coder Modeling GuidelinesID1.1.1Title1.3.2Architecture DesignBasic settingsAppropriate use of Simulink, Stateflow, MATLAB Function,BlackBox, Model Reference and HDL Cosimulation blockUse the hdlsetup command to set model configurationparameters and HDL model propertiesAvoid using double-byte charactersConsider resource sharing impact during model creationDocument block name, block features, authors, etc., insubsystem block propertiesTerminate unconnected block outputs with TerminatorblocksProper usage of commenting out blocksAdjust sizes of constant and gain blocks so thatparameters can be identifiedDisplay parameters that will affect HDL code generationChange block parameters by using find system andset paramSubsystem and Model HierarchyWhen the DUT is not at the top level of the model, set theDUT as a non-virtual subsystemType of subsystem and hierarchical design for a DUTDo not connect constant blocks to ports directly crossingsubsystem boundariesFor testbenches that use blocks in continuous solvermode, make the DUT a model reference with a discretesolver.Generate re-usable HDL code from identical subsystemsGenerate parameterized HDL code for gain and constantblocksInsert handwritten code for a block into the generatedcode for the DUTOnly use numerical values and string data types for maskparameters for user-defined subsystemsSignal typesSerialize 2D matrix signals into a 1D signal before it entersan HDL subsystem, and vice versa for the outputUsing a signal bus to improve readability1.3.3Design considerations for vector al vectors created by Delay, Mux, andConstant blocks generate HDL with ascending bit orderManually write HDL control logic for bidirectional portsClock and ResetCreating a frequency-divided clock from the Simulinkmodel’s base sample rateUse master-clock division or a clock multiple for propermulti-rate modelingUse Dual Rate Dual Port RAM for non-integer multiplesample times in a multi-rate yAll1.1.4.6All2.1.6.1

1.4.4Use global reset type best suited for your target hardware2.2.12.2Block SettingsDiscontinuitiesDiscreteAppropriate use of various types of delay blocks asregistersMap large delays to FPGA block RAM instead of registersto reduce areaHDL OperationsUse a Bit Concat block instead of a Mux block for bitconcatenation in VHDLDesign considerations for RAM Block accessHDL FIFO block usage considerationsParallel -- Serial conversionLogic and bit operationsLogical vs. arithmetic bit shift operationsLogical Operator, Bitwise Operator, and Bit Reduce forlogic operationsUse Boolean data type for the output of the Compare toConstant/Zero and the Relational Operator blocksLookup tablesSet the number of Lookup Table data entries to a power of2 to avoid generation of a division operator .4.32.52.5.12.5.2Generating FPGA block RAM from a Lookup Table block2.6Math operationsInput vector with Mux block to multi-input adder, multiinput product, and multi-input Set ConstMultiplierOptimization to 'auto' for a Gain block2.6.3Use the Bit Shift block or the bitshift function forcomputations of the power of 2 (ASIC)RecommendedASIC2.6.4Use Gain block for computations of the power of 2 (FPGA)RecommendedFPGA(Altera/Xilinx)2.6.5Use a Gain block for constant multiplication and nt multiplier design for targeting Altera DSP blockRecommended2.6.7Efficient multiplier design for targeting Xilinx DSP48 slicesConsider speed/area priority and DSP mapping whenmodeling complex multiplicationModel the delay of blocks that will be auto-pipelined(Divide, Sqrt, Trigonometric Function, CascadeAdd/Product, Viterbi Decoder)Use Divide blocks in reciprocal mode with a RecipNewtonor RecipNewtonSingleRate architecture for more optimalHDLConsider the additional latency impact of differentimplementation architectures for the Sqrt andReciprocalSqrt blocksRecommendedFPGA(Altera)FPGA .1.32.1.6.1

102.122.12.12.12.2Tradeoffs for Sin/Cos calculation using TrigonometricFunction, Lookup Table, Sine/Cosine, and NCO HDLOptimized blockUse only conj, hermitian, or transpose in a Math FunctionblockHDL code generation compatible Math Operations forcomplex number computationPorts and subsystemsBlock settings for Triggered Subsystems/EnabledSubsystemsProper usage of a Unit Delay Enabled block versus anenabled subsystem with a Delay blockSignal attributesRate conversion blocks and usageSignal routingChoosing the right block for extracting a portion of a vectorsignalBlock parameter setting for the Multiport Switch BlockAdd 1 to index signals when describing a selector circuit ina MATLAB Function blockUse a MATLAB Function block to select indices whenextracting portions of a very large constant vectorWriting to individual elements of a vector signal using theAssignment blockProper usage of Goto/From blocksAscending bit ordering for 1-D arrays may cause warningsfrom HDL rule checkersSource blocksDo not use a sample time of inf for a Constant blockMATLAB Function blocksProper usage of dsp.Delay as a registerUpdate persistent variables at the end of a MATLABfunctionExplicitly define data types for constants used inexpressionsUse Delay blocks to break feedback loops in MATLABFunction blocksDo not use logical operators in conditional statementswhen initializing persistent variablesUse X(:) X 1; when input and output data types are thesame in MATLAB code expressionsAvoid unintended latch inference by performing arithmeticoperations outside of if/else branchesAvoid generating always @* Verilog code for Xilinx Virtex4 and 5Using MATLAB code for [M, N] matrix operationsUse a single for loop for element-by-element operations toreduce areaStateflowChoosing Mealy vs Moore for Stateflow state machinetypeStateflow Chart block dAllMandatoryFPGA 1.1.1

2.12.32.12.42.12.52.12.62.12.7Do not use absolute time for temporal logical logic (after,before and every)Consider desired state order in generated HDL whennaming statesUsing a chart output as an input via a feedback loopInsert an unconditional transition state to create an elsestatement in the generated HDLAvoid unintended latch inference by performing arithmeticoperations outside of truth tables2.12.8Hardware considerations when designing an FSM2.13DSP System ToolboxUse the DSP System Toolbox Delay block if the number ofsamples to delay might be 0Changing the phase offset of a Downsample blockUse the NCO HDL Optimized block for sine and cosinecomputation and signal generationBlock settings for FIR filter blocksIIR Filter blocksOthersUse case restrictions when importing user-defined HDLcode with an HDL Cosimulation blockDefine clock and block name to match user-defined HDLsettings when using an HDL Cosimulation blockData type settingsBasic data type settingsUse fixed binary point scaling up to 128-bit for 52.142.14.12.14.233.13.1.13.1.2Trading off rounding error vs processing expense3.1.33.23.2.23.2.33.3Restrictions for data type overrideSimulink data type settingUse Boolean for logical data and use ufix1 for numericaldataDefine the data type of a Gain block explicitlyRestrictions for using enumerated valuesData type setting for MATLAB code3.3.1Using a fi object in a MATLAB Function block3.3.23.3.33.4Use like or cast to inherit data types in MATLAB codeUse True/False instead of Boolean data in MATLAB codeData type setting for Stateflow chartsUse a fi object when the Stateflow action language isMATLABOptimization of speed and areaResource sharingResource sharing requirementsUse StreamingFactor for resource sharing of 1D vectorsignal processingResource sharing of Gain blocksResource sharing of Product blocksResource sharing of mmendedRecommendedAllAllAll

peline insertionDesign considerations for pipelining and delay balancingRecommendedClock-rate pipeliningInformativeRecommended distributed pipelining settingsRecommendedApply distributed pipelining to adders, products, min/max,Informativeand dot products with vector inputsAppendixConsiderations in HDL code writing for ASIC/FPGA designSynchronous circuit design overview and recommendationsRecommended use of registers at outputs of hierarchical structuresFollow naming conventionsHDL-supported blocksCompatibility check for HDL code generationSetting global clock and reset signals in for HDL code generationAdd comments for generating readable HDL codeAllAllAllAll

1. Architecture Design1.1Basic settings1.1.1 Appropriate use of Simulink, Stateflow, MATLAB Function, BlackBox, Model Reference and HDL CosimulationblockWhen creating a hardware implementation model, there are recommended applications for Simulink blocks, MATLABfunction blocks and Stateflow charts. These can be mixed within a single subsystem to create a complete model asshown in the following figure:The recommended application for each type of block is as follows: Simulink block: Arithmetic algorithm containing numerical processing or feedback loop. MATLAB Function block: Control logic, conditional branch (If/Else statement), simple state machine, and IPwritten with MATLAB code. Stateflow:oState chart (Chart, State Transition Table block): Mode logic or state machine which control anoutput by logic of the past and the presentoFlow chart (Chart block): Multiple conditional branch (If/Else)oTruth table (Truth Table block): Multiple conditional branch (If/Else)The algorithm modeled by Stateflow uses logic as main elements, and when complicated operation isincluded, describe that the calculated result of Simulink block is changed in the logic of Stateflow. Becauseexplicit pipeline processing cannot be described in Stateflow and change of the timing by pipelining insertionis unclear. BlackBox: For subsystems that don’t need simulation, or that will use imported HDL code. This is anarchitecture property that can be applied to a subsystem or a referenced model (for example, an interfacecircuit for an A/D converter, an SDRAM controller, etc.) It is also possible to use the BlackBox property toincorporate handwritten code into a cosimulation model. Model reference: For re-using models as sub-blocks in other models. This is useful for partitioning a designto be worked on by multiple engineers in parallel. For more on HDL code generation from a referencedmodel, see the documentation.Note that since a referenced model is treated the same as an Atomic subsystem, an algebraic loop mayoccur which will prevent HDL code generation. These can be fixed in the design, or possibly by setting theMinimize algebraic loop occurrences in the Model Referencing pane of Configuration Parameters.

HDL Cosimulation: For simulating HDL code for the DUT in Mentor Questa or ModelSim , or Cadence Incisive , connected to the Simulink environment via HDL Verifier.1.1.2 Use the hdlsetup command to set model configuration parameters and HDL model propertieshdlsetup('modelname') sets the parameters of the model specified by modelname to common default values forHDL code generation.Example: myhdlsetup.m1.1.3 Avoid using double-byte charactersDouble-byte characters, which are used for Japanese and Chinese characters, are typically not supported bydownstream logic synthesis and simulation tools. Therefore HDL code generation does not support them in modeland block names.It is also recommended to avoid using double-byte characters in comments as well, since comments are propagatedinto the generated code. It is good practice to use English for comments.1.1.4 Consider resource sharing impact during model creationSee 4.1 Resource Sharing.1.1.5 Document block name, block features, authors, etc., in subsystem block propertiesTo improve management of the generated HDL, it is good practice to document reference information in thesubsystem block properties since these will be generated as comment headers in the HDL. For example:This generates code with a header that looks like this:-- Simulink subsystem description for vector fft implementation example/Vector FFT:--- Created by: John Simulink-- Function: Vector FFT-- This model shows.-- Revision 1.0-- Revision 1.1 added functionality to.--- ----------LIBRARY IEEE;USE IEEE.std logic 1164.ALL;USE IEEE.numeric std.ALL;ENTITY Vector FFT IS

1.1.6 Terminate unconnected block outputs with Terminator blocksHDL code generation will fail and generate an error when output ports of blocks are unconnected. For output blocksthat are intentionally not connected to downstream logic, connect them to a Terminator block. The followingillustrates:Example: AD015 outTerminate.slx1.1.7 Proper usage of commenting out blocksCode generation will fail if a block has been tagged as a “comment through” pass-through.Code can be generated for a block that is commented out. The generated code will assign a constant value of 0 tothe signal that would have been connected to its output. For instance the following example:Generates the following HDL:VHDL generated from the subsystem containing acommented-out blockENTITY Generated ISPORT( In1 : INOut1 : OUT);END Generated;std logic vector(15 DOWNTO 0);std logic vector(15 DOWNTO 0)ARCHITECTURE rtl OF Generated ISSIGNAL TmpGroundAtDT DupIn1 out1 : signed(15 DOWNTOVerilog generated from the subsystem containing acommented-out blockmodule Generated(In1,Out1);inputoutputsigned [15:0] In1;signed [15:0] Out1;

0);BEGINTmpGroundAtDT DupIn1 out1 to signed(16#0000#,16);wire signed [15:0] TmpGroundAtDT DupIn1 out1;assign TmpGroundAtDT DupIn1 out1 16'sb0000000000000000;assign Out1 TmpGroundAtDT DupIn1 out1;Out1 std logic vector(TmpGroundAtDT DupIn1 out1);endmoduleEND rtl;1.1.8 Adjust sizes of constant and gain blocks so that parameters can be identifiedFor constant blocks and gain blocks that use parameter values, in order to increase readability it is good practice toadjust the size of the block so that the parameter value can be displayed. For instance:1.1.9 Display parameters that will affect HDL code generationCertain block parameters such as pipelining and resource sharing can significantly affect HDL code generation.Therefore if these parameters are set, it is good practice to display them in the Simulink diagram. It also helps to usedelimiters such as “--------“ to separate the annotation from the block name. For example:

Example: BS013 blockAnnotation.slx, showHdlBlockParams.mThe sample file showHdlBlockParams.m attaches a delimiter and annotation automatically to the block to which thefollowing HDL block properties are set: BalanceDelays DistributedPipelining ConstrainedOutputPipeline InputPipeline, OutputPipeline StreamingFactor SharingFactorIn order to attach an annotation of the above property via the command-line: showHdlBlockParams ( blockname and 'on -- ')To delete the

Implement the generated HDL on the target hardware. 0.2 Target language HDL Coder generates synthesizable VHDL or Verilog. VHDL is the default. The target language can be set a number of different ways, the most common being Simulink Configuration Parameters HDL Code Generation pane or the Simulink HDL Workflow Advisor as follows:

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