Microprocessors And Interfacing (A1423) Unit I Introduction
2/20/2015Microprocessors and Interfacing (A1423)Unit – I IntroductionDepartment of Electronics and Communication EngineeringVARDHAMAN COLLEGE OF ENGINEERINGShamshabad, Hyderabad – 501218, India.Microprocessors and Interfacing (A1423)Pre-requisitesDigital Logic Design (A1404)Computer Architecture and Organization (A1509)220 February 20151
2/20/2015Microprocessors and Interfacing (A1423)Text Books Douglas V. Hall (2007), Microprocessors and InterfacingProgramming and Hardware, 2nd Edition, Tata McGraw Hill,New Delhi. A. K. Ray, K. M. Bhurchandi, Advanced Microprocessorsand Peripherals, 2nd Edition, Tata McGraw Hill, New Delhi.20 February 20153Microprocessors and Interfacing (A1423)Reference Books Walter A. Triebel, Avtar Singh (2003), The 8088 and 8086Microprocessors, 4th Edition, Prentice Hall of India, NewDelhi. Barry B. Brey (2001), The Intel Microprocessors8086/8088, 80186/80188, 80286, 80386, 80486, Pentium,and Pentium Pro Processor, Architecture, Programming,and Interfacing, 4th Edition, Prentice Hall of India, NewDelhi. Kenneth J. Ayala (2008), The 8086 Microprocessor:Programming & Interfacing the PC, Cengage Learning,New Delhi.420 February 20152
2/20/2015Microprocessors and Interfacing (A1423)Unit - I Number Systems and Digital Logic Review Overview of Microcomputer Structure and Operation Evolution of Microprocessors 8086 Microprocessor Architecture Register Organization 8086 Pin Diagram and Signal Description 8086 Minimum Mode and Its Timing Diagram 8086 Maximum Mode and Its Timing Diagram Addressing Modes20 February 20155Microprocessors and Interfacing (A1423)Microprocessor Interface620 February 20153
2/20/2015Microprocessors and Interfacing (A1423)Evolution of Microprocessors Based on the Word Length (Number of binary bits in data processing) 4-bit, 8-bit, 16-bit, 32-bit, and 64-bit400480088080808580868028680386PentiumPentium Pro20 February 20157Microprocessors and Interfacing (A1423)INTEL 4004 Built in 1971 4 Bit Micro-processor Initial clock speed 108 KHz No of transistors used 2300 Developed on P-MOS technology4
2/20/2015Microprocessors and Interfacing (A1423)INTEL 80081) Built in 19722) 8 bit Micro-processor3) Initial clock speed of 500-800 KHz4) No of transistors used were 35005)Also developed on PMOS technologyMicroprocessors and Interfacing (A1423)INTEL 80801)2)3)4)5)6)Built in 19748 Bit MicroprocessorInitial clock speed 500-800 KHzNo of transistors used 4500Developed using NMOS TechnologyDrawbacks: It required 3 power supplies5
2/20/2015Microprocessors and Interfacing (A1423)INTEL 80851)2)3)4)5)Built in 19775 in 8085 means 5 volt supplyInitial clock speed of about 3MHzApprox. 6500 transistors were used8 Bit µ-Processor using NMOS technologySPECIAL FEATURESExtension to support new interrupts :- Maskable (RST 7.5,RST6.5,RST 5.5) Non-Maskable (TRAP) and externally servicedInterrupt (INTR).2) 8085 can itself drive piezoelectric crystal directly connected to it.3) Through 8 bit Microprocessor but it can also load 16 bit data(Through pairs BC DE HL).1)Microprocessors and Interfacing (A1423)INTEL 80861)2)3)4)5)Built in 197916 bit MicroprocessorIt has 20 bit address bus and 1 MB addressing spaceInitial clock speed of 5 MHz,8 MHz and 10 MHzNo of transistors used were 29,000SPECIAL FEATURES1) Memory divided into odd and even banks2) Can read upto 16 bits of data in one cycle6
2/20/2015Microprocessors and Interfacing (A1423)INTEL 80286ProcessorINTEL 803861) It is a 16 bit x861) It is a 32 bit x862)3)4)5)processorProvides Memorymanagement &protectionInitial clock speed 8 MHz24 bit address bus givesthe capacity to access16 MB storageAbout 134,000transistors were usedProcessor2)3)4)5)processorIt has 32 bit address busand 32 bit data busClock speeds between12-40 MHzIt can access upto 4GBof physical memoryAbout 275,000transistors were usedMicroprocessors and Interfacing (A1423)Intel Pentium Processor:1) Built in 19932) Clock speed 66 MHz3) Approx. 31 Lakhs transistors were used4) 112 million commands per second could be executedper second.Pentium Series Advancement:(Pentium 2 to Pentium 4 processor)1) Clock speed was increased from 66 MHz to 1.7 GHz2) No of transistors were also increased from 31 Lakhs to5.5 Crore7
2/20/2015Microprocessors and Interfacing (A1423)INTEL CORE 2 DUO AND DUAL COREPROCESSORS:1) Built in 2006 and 2007 respectively2) Clock speed varies from 1.6 GHz to 2.6 Ghz3) In built cache memory of 2MB to 6 MB4) Both are 64 bit microprocessors5) Both were mainly media centred and provided HDdisplay qualityMicroprocessors and Interfacing (A1423)INTEL CORE 2 DUO AND DUAL COREPROCESSORS:1) Built in 2006 and 2007 respectively2) Clock speed varies from 1.6 GHz to 2.6 Ghz3) In built cache memory of 2MB to 6 MB4) Both are 64 bit microprocessors5) Both were mainly media centred and provided HDdisplay quality8
2/20/2015Microprocessors and Interfacing (A1423)INTEL CORE SERIES (i3,i5,i7, i7extreme)1) Core are more powerful variants of the sameprocessors sold as Celeron and Pentium2) They are made mainly for multitasking3) These processors were made available to publicfrom January 20104) Clock speed varies from 1.7GHz (slowest) and3.5GHz (fastest)Microprocessors and Interfacing (A1423)8086 Microprocessor Architecture es a 16-bit ALU a set of 16-bit registers segmented memory addressing capability a rich instruction set powerful interrupt structure fetched instruction queue for overlapped fetchingandexecution etc.18S. Rajendar20 February 20159
2/20/2015Microprocessors and Interfacing (A1423)8086 Microprocessor ArchitectureCont To improve the performance by implementing the19parallel processing concept the CPU of the 8086 isdivided into two independent sections. They are Bus Interface Unit (BIU) and Execution Unit (EU) The BIU sends out addresses, fetches instructions,read data from ports and memory and writes data toports and memory, i.e., the BIU handles all transfersof data and addresses on the buses required by theExecution Unit whereas the Execution Unit tells theBIU where to fetch instructions or data from, decodesthe instructions and executes the instructions.S. Rajendar20 February 2015Microprocessors and Interfacing (A1423)8086 Microprocessor ArchitectureCont The BIU contains the circuit for physical address calculationsa predecoding instruction byte queue (6 byteslong) four 16-bit segment registers (ES, CS, SS, DS) 16-bit instruction pointer (IP) The EU contains control circuitry, instruction decoder and ALU 16-bit flag registers four 16-bit general purpose registers (AX, BX,CX, DX) 16-bit pointer registers (SP, BP) and 16-bit index registers (SI, DI)20S. Rajendar20 February 201510
2/20/2015Microprocessors and Interfacing (A1423)8086 Microprocessor ArchitectureCont 21S. Rajendar20 February 2015Microprocessors and Interfacing (A1423)8086 Microprocessor ArchitectureCont Execution Unit:Control Circuitry, Instruction Decoder and ALU: The EU contains control circuitry which directsinternal operations. A decoder in the EU translates instructions fetchedfrom memory into a series of actions which the EUcarries out. The EU has a 16-bit arithmetic logic unit which canadd, subtract, AND, OR, XOR, increment, decrement,complement, or shift binary numbers.22S. Rajendar20 February 201511
2/20/2015Microprocessors and Interfacing (A1423)8086 Microprocessor ArchitectureCont Flag Registers: The 8086 16-bit flag register contents indicate theresults of computations in the ALU. It also containssome flag bits to control the CPU operations. A flag is a flip-flop that indicates some conditionproduced by the execution of an instruction orcontrols certain operations of the EU.General Purpose Registers: The registers AX, BX, CX and DX are the generalpurpose 16-bit registers .23S. Rajendar20 February 2015Microprocessors and Interfacing (A1423)8086 Microprocessor ArchitectureCont Pointer Registers: The 16-bit pointer registers usually contains offsetaddress within the particular segments.Index Registers: The 16-bit index registers are used as generalpurpose registers as well as for offset storage.24S. Rajendar20 February 201512
2/20/2015Microprocessors and Interfacing (A1423)8086 Microprocessor ArchitectureCont Bus Interface Unit:The Queue: While the EU is decoding an instruction or executing aninstruction which does not require use of the buses, the BIUfetches up to six instruction bytes for the following instructions. The BIU stores these prefetched bytes in a first-in-first-outregister set called a queue. When the EU is ready for its next instruction, it simply reads theinstruction byte(s) for the instruction from the queue in the BIU. This is much faster than sending out an address to the systemmemory and waiting for memory to send back the nextinstruction byte or bytes. Fetching the next instruction while the current instructionexecutes is called pipelining.25S. Rajendar20 February 2015Microprocessors and Interfacing (A1423)8086 Microprocessor ArchitectureCont Segment Registers: The 8086 BIU sends out 20-bit addresses, so it canaddress any of 220 or 1,048,576 bytes in memory.However, at any given time the 8086 works with only four65,536 byte (64Kbyte) segments within this 1,048,576 byte(1 Mbyte) range. Four segment registers in the BIU are used to hold theupper 16 bits of the starting addresses of four memorysegments that the 8086 is working with at a particular time. The four segment registers are the code segment (CS)register, the stack segment (SS) register, the extrasegment (ES) register, and the data segment (DS) register.26S. Rajendar20 February 201513
2/20/2015Microprocessors and Interfacing (A1423)8086 Microprocessor ArchitectureCont Instruction Pointer: The instruction pointer register holds the 16-bitaddresses, or offset, of the next code byte within thiscode segment.27S. Rajendar20 February 2015Microprocessors and Interfacing (A1423)Memory Segmentation:28S. Rajendar20 February 201514
2/20/2015Microprocessors and Interfacing (A1423)Register organization of 8086 8086 has a powerful set of registers known asgeneral purpose and special purpose registers. All of them are 16-bit registers.29S. Rajendar20 February 2015Microprocessors and Interfacing (A1423)Register Organization of 8086General Purpose RegistersSegment RegistersFlag RegisterPointers and Index Registers30S. DHDLDataCSCode SegmentSSStack SegmentDSData SegmentESExtra SegmentFLAGS/PSWSPStack PointerBPBase PointerSISource IndexDIDestination PointerInstruction PointerIP20 February 201515
2/20/2015Microprocessors and Interfacing (A1423)General Purpose Registers The registers AX, BX, CX and DX are the generalpurpose 16-bit registers. The general purpose registers, can be used as either8-bit registers or 16-bit registers. These registers are referred to as the accumulatorregister (A), the base register (B), the count register(C), and the data register (D). General purpose registers, can be used for holdingdata, variables and intermediate results temporarily orfor other purposes like a counter or for storing offsetaddress for some particular addressing modes etc.31S. Rajendar20 February 2015Microprocessors and Interfacing (A1423)General Purpose RegistersRegisterOperationsAXWord multiply, word divide, word I/OALByte multiply, byte divide, byte I/O, translate, decimalarithmeticAHByte multiply, byte divideBXTranslateCXString operations, loopsCLVariable shift and rotateDXWord multiply, word divide, indirect I/OTable : Dedicated Register Functions32S. Rajendar20 February 201516
2/20/2015Microprocessors and Interfacing (A1423)Special Purpose Registers Segment Registers Pointers and Index Registers Flag Register The special purpose registers are used as segmentregisters, pointers, index registers or as offset storageregisters for particular addressing modes.33S. Rajendar20 February 2015Microprocessors and Interfacing (A1423)Segment Registers 8086 addresses a segmented memory. The complete 1MB memory, which the 8086addresses, is divided into 16 logical segments. Each segment thus contains 64KB of memory. There are four segment registers, viz. Code Segment Register (CS) Data Segment Register (DS) Extra Segment Register (ES) Stack Segment Register (SS)34S. Rajendar20 February 201517
2/20/2015Microprocessors and Interfacing (A1423)Segment Registers Cont Code segment register is used for addressing amemory location in the code segment of the memory,where the executable program is stored. The data segment register points to the data segmentof the memory, where the data is resided. The extra segment also refers to a segment whichessentially is another data segment of the memory.Thus, the extra segment also contains data. The stack segment register is used for addressingstack segment of memory, i.e, memory which is usedto store stack data. The CPU uses the stack fortemporarily storing important data, e.g. the contents ofthe CPU registers which will be required at a laterstage.35S. Rajendar20 February 2015Microprocessors and Interfacing (A1423)Pointer RegistersStack Pointer Register: A stack is a section of memory set aside to storeaddresses and data while subprogram is executing. The 8086 allows you to set aside an entire 64Kbytesegment as a stack. The data segment register points to the data segment ofthe memory, where the data is resided. The extra segment also refers to a segment whichessentially is another data segment of the memory. Thus,the extra segment also contains data. The stack segment register is used for addressing stacksegment of memory, i.e, memory which is used to storestack data. The CPU uses the stack for temporarily storingimportant data, e.g. the contents of the CPU registerswhich will be required at a later stage.36S. Rajendar20 February 201518
2/20/20158086 MicroprocessorArchitectureExecution Unit (EU)Bus Interface Unit (BIU)EU executes instructions that havealready been fetched by the BIU.BIU fetches instructions, reads datafrom memory and I/O ports, writesdata to memory and I/ O ports.BIU and EU functions separately.378086 MicroprocessorArchitectureBus Interface Unit (BIU)Dedicated Adder to generate20 bit addressFour 16-bit segmentregistersCode Segment (CS)Data Segment (DS)Stack Segment (SS)Extra Segment (ES)Segment Registers 3819
2/20/20158086 MicroprocessorArchitectureBus Interface Unit (BIU)SegmentRegisters8086’s 1-megabytememory is dividedinto segments of upto 64K bytes each.The 8086 can directlyaddressfoursegments(256 K bytes within the 1M byte of memory) at aparticular time.Programs obtain accessto code and data in thesegments by changingthesegmentregistercontent to point to thedesired segments.398086 MicroprocessorSegmentRegistersArchitectureBus Interface Unit (BIU)Code Segment Register16-bitCS contains the base or start of the current code segment;IP contains the distance or offset from this address to thenext instruction byte to be fetched.BIU computes the 20-bit physical address by logicallyshifting the contents of CS 4-bits to the left and thenadding the 16-bit contents of IP.That is, all instructions of a program are relative to thecontents of the CS register multiplied by 16 and then offsetis added provided by the IP.4020
2/20/20158086 MicroprocessorSegmentRegistersArchitectureBus Interface Unit (BIU)Data Segment Register16-bitPoints to the current data segment; operands for mostinstructions are fetched from this segment.The 16-bit contents of the Source Index (SI) orDestination Index (DI) or a 16-bit displacement are usedas offset for computing the 20-bit physical address.418086 MicroprocessorSegmentRegistersArchitectureBus Interface Unit (BIU)Stack Segment Register16-bitPoints to the current stack.The 20-bit physical stack address is calculated from theStack Segment (SS) and the Stack Pointer (SP) for stackinstructions such as PUSH and POP.In based addressing mode, the 20-bit physical stackaddress is calculated from the Stack segment (SS) and theBase Pointer (BP).4221
2/20/20158086 MicroprocessorSegmentRegistersArchitectureBus Interface Unit (BIU)Extra Segment Register16-bitPoints to the extra segment in which data (in excess of64K pointed to by the DS) is stored.String instructions use the ES and DI to determine the 20bit physical address for the destination.438086 MicroprocessorSegmentRegistersArchitectureBus Interface Unit (BIU)Instruction Pointer16-bitAlways points to the next instruction to be executed withinthe currently executing code segment.So, this register contains the 16-bit offset address pointingto the next instruction code within the 64Kb of the codesegment area.Its content is automatically incremented as the executionof the next instruction takes place.4422
2/20/20158086 MicroprocessorArchitectureBus Interface Unit (BIU)Instruction queueA group of First-In-FirstOut (FIFO) in which up to6 bytes of instructioncode are pre fetchedfrom the memory aheadof time.This is done in order tospeed up the n.This mechanism is knownas pipelining.458086 MicroprocessorExecution Unit (EU)ArchitectureEU decodes andexecutes instructions.A decoder in the EUcontrol systemtranslates instructions.16-bitALUforperforming arithmeticand logic operationFour general purposeregisters(AX, BX, CX, DX);Pointer registers (StackPointer, Base Pointer);andIndex registers (SourceIndex, Destination Index)each of 16-bitsSome of the 16 bit registers can beused as two 8 bit registers as :AX canBX canCX canDX canbe usedbe usedbe usedbe usedasasasasAH andBH andCH andDH andALBLCLDL4623
2/20/20158086 MicroprocessorEURegistersArchitectureExecution Unit (EU)Accumulator Register (AX)Consists of two 8-bit registers AL and AH, which can becombined together and used as a 16-bit register AX.AL in this case contains the low order byte of the word,and AH contains the high-order byte.The I/O instructions use the AX or AL for inputting /outputting 16 or 8 bit data to or from an I/O port.Multiplication and Division instructions also use the AX orAL.478086 MicroprocessorEURegistersArchitectureExecution Unit (EU)Base Register (BX)Consists of two 8-bit registers BL and BH, which can becombined together and used as a 16-bit register BX.BL in this case contains the low-order byte of the word,and BH contains the high-order byte.This is the only general purpose register whose contentscan be used for addressing the 8086 memory.All memory references utilizing this register content foraddressing use DS as the default segment register.4824
2/20/20158086 MicroprocessorEURegistersArchitectureExecution Unit (EU)Counter Register (CX)Consists of two 8-bit registers CL and CH, which can becombined together and used as a 16-bit register CX.When combined, CL register contains the low order byte ofthe word, and CH contains the high-order byte.Instructions such as SHIFT, ROTATE and LOOP use thecontents of CX as a counter.Example:The instruction LOOP START automatically decrementsCX by 1 without affecting flags and will check if [CX] 0.If it iszero, 8086 executes the next instruction;otherwise the 8086 branches to the label START.498086 MicroprocessorArchitectureExecution Unit (EU)EURegisters5025
2/20/20158086 MicroprocessorEURegistersArchitectureExecution Unit (EU)Stack Pointer (SP) and Base Pointer (BP)SP and BP are used to access data in the stack segment.SP is used as an offset from the current SS duringexecution of instructions that involve the stack segment inthe external memory.SP contents are automatically updated (incremented/decremented) due to execution of a POP or PUSHinstruction.BP contains an offset address in the current SS, which isused by instructions utilizing the based addressing mode.518086 MicroprocessorEURegistersArchitectureExecution Unit (EU)Source Index (SI) and Destination Index (DI)Used in indexed addressing.In
2/20/2015 6 Microprocessors and Interfacing (A1423) INTEL 8085 1) Built in 1977 2) 5 in 8085 means 5 volt supply 3) Initial clock speed of about 3MHz 4) Approx. 6500 transistors were used 5) 8 Bit µ-Processor using NMOS technology SPECIAL FEATURES 1) Extension to support new interrupts :- Maskable (RST 7.5,RST 6.5,RST 5.5) Non-Maskable (TRAP) and externally serviced
LECTURE NOTES ON MICROPROCESSORS AND INTERFACING DEVICES III B. Tech II semester (JNTUH-R15) . Signal descriptions of 8086-common function signals, Minimum and . The control bus carries synchronization signal
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4.6 More Projects on LED Interfacing to Microcontrollers 51 4.6.1 Running LEDs 51 4.6.2 Running Bicolor LED 51 4.6.3 Interfacing 6 LEDs Using 3 Microcontroller Pins by 51 4.6.4 The LED Dimmer Demoboard 51 4.6.5 Fading RGB LED 52 4.6.6 LED Moving Font 52 4.7 DIP Switch Interfacing: Getting Input to Your Embedded System 52 4.8 LCD Interfacing 54
Computer Organization and Microprocessors Page 2 Background and Acknowledgements This material is intended for the second course in digital systems focus on Computer Organization and Microprocessors. The content is derived from the author’s educational, engineering and management career, and teaching experience.
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INTRODUCTION TO MICROPROCESSORS COURSE OUTLINE Topic Class notes Ford & Topp, 2nd Ed. Informational (1 lecture) a. Course syllabus b. grading policies c. CWRUnet ethics code d class notes e. CWRUnet 1. connecting via PPP 2. connecting to the Kern Lab f. Where microprocessors came from 1-4 5 6-8 9 10 11 Number systems and computer math (3 lectures)
approaches to the subject of reconstruction in archaeological illustration, and other media i.e. films. Method(s) of teaching: The module comprises: A weekly practical session (2hrs) where tutor will introduce different materials and recorded graphic data to be drawn. 1 x lecture Visit and meet with archaeological illustrators and graphic designers in their workplace Method of assessment: The .
