VERIFICATION OF I2C DUT USING SYSTEMVERILOG

International Journal of Advanced Engineering TechnologyE-ISSN 0976-3945Research ArticleVERIFICATION OF I2C DUT USING SYSTEMVERILOG1Purvi Mulani, 2Jignesh Patoliya, 3Hitesh Patel, 4Dharmendra Chauhan1,2,3Address for CorrespondenceDept.of Electronics and Communication Engg.Charotar University of Science and Technology, Changa,Anand,Gujarat-388421(India)4Electronics and Communication Dept S.P.B.Patel Engineering College, LinchMehsana - Ahmadabad Highway.1purvi.mulani@gmail.com, 2jigneshpatoliya@ecchanga.ac.in, 3hiteshpatel.ec@ecchanga.ac.in,4chauhan ec@yahoo.co.inABSTRACTVerification is the process used to demonstrate the functional correctness of a design prior to its fabrication. The lackof flexible verification environments that allow verification components reuse across ASIC design projects keep theverification cost very high. Design engineers have made design reuse central in bringing the design effort’s complexityback to a manageable size and to reduce development time and effort. Considering the fact that verification consumesmore resources than design does in a typical design project, it would be of great value to build verification componentsthat are modular and reusable. This paper describes the verification of I2C DUT using System Verilog. The DUT hasbeen verified for all four possible configurations, which are: Master TX, Master Rx, Slave TX, and Slave Rx. Theverification environment is designed in System Verilog for verifying the DUT which acts as master if DUT isconfigured as slave and acts as slave if DUT is configured as master. The verification environment designed isreusable for any I2C DUT.KEYWORDS: ASIC, DUT, I2C, SoC, System Verilogas cycles, tri-state values, wires, just like VerilogI. INTRODUCTIONThe tremendous progress of VLSI technologyenables the integration of more than severalmillion transistors in a single chip to make a SoC(System-on-Chip). This has made verification themost critical bottleneck in the chip design flow.Roughly 70 to 80 percent of the design cycle isspentinfunctionalverification.[1]SystemVerilog is a special hardware verificationlanguage to be used in function verification. Itprovides the high-level data structures availablein object-oriented languages, such as C . Thesedatastructuresenableahigherlevelofabstraction and modeling of complex data types.The System Verilog also provides constructsnecessary for modeling hardware concepts suchIJAET/Vol.I/ Issue III/Oct.-Dec.,2010/130-134hardware languages. So System Verilog can beused to simulate the HDL design and verify themby high level test case. I2C is one module in thisSoC and it has been verified for all possibleconfigurations. During verifying the SoC, a greatdeal of visual simulation waveform inspection isrequired. The Simvision waveform viewer is usedand the observed waveforms are also discussed inthis paper.II.VERIFICATIONENVIRONMENTARCHITECTUREThe architecture of verification environmentdeveloped for I2C protocol is shown in thefigure 1. The different modules of environmentare explained.

International Journal of Advanced Engineering TechnologyE-ISSN 0976-3945Figure 1. I2C verification environment architectureA).Top moduleand monitor, while passive component containsThis is test case which is class of system Verilogonly Monitor. Agent will also pass the interface ofwhich contains instances of I2C Env, master agentthe DUT to each of the sub-sequent component.and slave agent.F). i2c master agent configB). i2c envMaster agent config has all the parameters likeThis is I2C component, containing Agent (masterfrequency of the master, timing parameters for theand slave).masterIn addition, agent should belikedelay to drive sda,configurable for passive/active. All checkers anddelay to sample sda,coverage are configurable to disable/enable.scl low width, the duration for which glitchC). i2c env configneeds to be generated. These parameters can beThis env config class contains the configurableconfigured at run time for the component. Itparameters like number of masters, number ofcontains two methods:scl high width,slaves present in the environment.(1) i2c ferq update: to change the frequencyD). i2c transferaccording to user.This is the basic transfer class, which will have all(2) i2c scl pulse width: calculates scl pulserequiredwidth according to frequency.parametersforI2Clikeaddress,read/write access, data size, etc.E) .i2c master agentMaster agent is configurable either as a active oras a passive. Active contains Driver, SequencerIJAET/Vol.I/ Issue III/Oct.-Dec.,2010/130-134G). i2c master monitorMaster Monitor collects all the data from interfaceand makes a transaction. It also stores this dataand emits an event for score-boarding. Based on

International Journal of Advanced Engineering TechnologyE-ISSN 0976-3945the collected transfer, it makes functionalN). i2c slave seqcoverage and also does a data checking.This will contain the sequences, which are goingH). i2c master driverto be used for verification. By this, the test caseDriver makes use of “i2c transfer” as a basic itemcan become shorten and easier.and does connect the sequences with this basicItitem. This will also contain the provision to makeslave agent config and slave interface.directed and random test selection.O). i2c slave seq libraryI). i2c master seqThis file contains the different sequences whichThis will contain the sequences, which are goingare used in test cases to generate differentto be used for verification. By this, the test casescenarios. Each sequence is a class.can become shorten and easier.It containsinstances of monitor, master agent config andmaster interface.J). i2c master seq libraryThis file contains the different sequences whichare used in test cases to generate differentscenarios. Each sequence is a class.K). i2c slave agentSlave agent is configurable as either active orcontainsinstancesofmonitor,III. TESTCASESA).DUT can work in following four modes.Mater TX:DUT is master and is in transmit mode. Sowe have used slave part of our verificationenvironment and we have to configure it inRX mode to receive data transmitted byDUT.Mater RX:passive. Active contains driver, sequence andDUT is master and is in receive mode. So wemonitor while passive component contains onlyhave used slave part of our verificationMonitor. Agent will also pass the interface of theenvironment and we have to configure it inDUT to each of the sub-sequent component.TX mode to transmit data to DUT.L). i2c slave agent configSlave TX:Slave agent config has all the parameters likeDUT is slave and is in transmit mode. So weaddress of the Slave, Glitch period to be detectedhave used master part of our verificationon SDA and SCL line, busy bit to be set by slave.environment and we have to configure it inThis parameters can be configured at run time forRX mode to receive data transmitted bythe component.DUT.M). i2c slave monitorSlave RX:Slave Monitor collects all the data from interfaceDUT is slave and is in receive mode. So weand makes a transaction. It also stores this datahave used master part of our verificationand emits an event for score-boarding. Based onenvironment and we have to configure it inthe collected transfer, it makes functionalTX mode to transmit data to DUT.coverage and also does data checking.Testcases are written for these four modes toverify the DUT.IJAET/Vol.I/ Issue III/Oct.-Dec.,2010/130-134

International Journal of Advanced Engineering TechnologyE-ISSN 0976-3945Figure 2. Environment with DUT configured as slaveFigure 3. Environment with DUT configured as masterB). i2c slave rx test.sv:address is received by DUT and then DUT willDUT has been configured as slave and it issendconfigured as a receiver. To verify the DUT, theenvironmentverification environment is developed which isacknowledgement, Verification environment willmaster and it transmits the data which is receivedsend data to DUT on the pin sig sda which willby DUT which is shown in figure 3. Verificationbe received by slave DUT on sda in iic pin.environment asa master will generate clock andThen after data transfer has been finished,start condition. After that, it will send address ofverification environment as a master willthe slave to which it wants to communicate whichgenerateis shown by signal sda in iic in figure. Thiscompletion of transfer.IJAET/Vol.I/ Issue ndicates

International Journal of Advanced Engineering TechnologyFigure 4. i2c slave rx testIV. CONCLUSIONIn this paper, we have used System Verilog to putup a verification intellectual property which isreusable to verify any I2C DUT. By using thisverification environment the DUT has beenverified for its functionality.REFERENCES1.2.3.4.5.Han Ke, Deng Zhongliang, Shu Qiong“Verification of AMBA Bus Model UsingSystemVerilog” in The Eighth InternationalConference on Electronic Measurement andInstrumentsSystemVerilog 3.1a Language ReferenceManual Accellera’s Extensions to VerilogUM10204 I2C-bus specification and usermanual Rev. 03 — 19 June 2007Micro computer control small area networkspecialistsI2C bus Inter Integrated Circuits bus byPhilips Semiconductors TomášMatoušektmd.havit.czIJAET/Vol.I/ Issue III/Oct.-Dec.,2010/130-134E-ISSN 0976-3945

(System-on-Chip). This has made verification the most critical bottleneck in the chip design flow. Roughly 70 to 80 percent of the design cycle is spent in functional verification. [1]System Verilog is a special hardware verification language to be used in function verification. It provides the high-level data structures available