Circuit And PD Challenges At The 14nm Technology Node

Circuit and PD Design Challengesat the14nm Technology NodeJim WarnockSession: Advanced Technologies and Design for ManufacturabilityISPD 2013IBM Systems and Technology Grouppage 1 of 29

Outline Introduction Classical CMOS Scaling: The End of the Road New Device Structures What do these structures mean for circuit designers? Wire Interconnects Reliability Conclusionspage 2 of 29

Introduction 14nm technology will pose many challenges, for many typesof designs This talk will focus on: High-frequency digital CMOS design, ie for high-performancemicroprocessorsNew PD issuesCircuits, wires, reliability, variability Issues related to manufacturing, yield, etc: not covered here Why is 14nm so difficult? What will designers be facing at the 14nm technology node?page 3 of 29

Outline Introduction Classical CMOS Scaling: The End of the Road New Device Structures What do these structures mean for circuit designers? Wire Interconnects Reliability Conclusionspage 4 of 29

CMOS Supply Voltage Scaling Difficulties10Voltage (V)Classical DennardScaling RegimeHigh-performance voltage1Voltage“gap”Scaled voltage14nmRegime0.10.010.11Feature pitch (microns)page 5 of 29

Voltage Scaling Difficulties “The End is Near” ish Maybe not the end, but things are sure getting tough Voltage scaling for high-performance designs is limited Limited by leakage issues: can’t reduce threshold voltages Limited by variability, esp VT variability Need steeper sub-threshold slopes Need to minimize random dopant fluctuations (RDF) Limited by gate oxide thickness Some relief from high-K materials (postpones the problem for acouple of generations) Limited voltage scaling decreasing feature sizes Increasing electric fields page 6 of 29New device structures needed (short channel control)Reliability challenges (devices and wires)

CMOS Power-performance ScalingRelative Performance Metric(Const power density)Where this curve is flat, can only improve chip freq by:a) pushing core/chip to higher power density (tough these days )b) design power efficiency improvements (low-hanging fruit all gone)100When scalingwas good 14nmRegime100.010.11Feature pitch (microns)page 7 of 2910

From IEEE ISSCC 2013 Supplement:page 8 of 29

Lithography Scaling1Rayleigh Factor (k1)Conventional lithographyOPC, OAI,ComputationalLithographyk1 (resolution)*NAlDouble patterning14nmRegime0.10.010.1Feature pitch (microns)page 9 of 291

Outline Introduction Classical CMOS Scaling: The End of the Road New Device Structures What do these structures mean for circuit designers? Wire Interconnects Reliability Conclusionspage 10 of 29

Multigate/FinFET DevicesGFinFET dual-gate cross sectionSGate ElectrodeDFinFET tri-gate cross sectionGate Electrodepage 11 of 29

Trigate/FinFET Devices The good news: Expect improved subthreshold slopeExpect improved RDF-induced variabilityAbove could help to enable lower voltage operation What designers have to worry about: New sources of variability Some of the same old variability issues (continuing to worsen ) Gate line-edge roughening (LER), channel length variabilityMay be exacerbated by 3D effects“Quantization” of device widths Fin width will have a significant impact on VT: Expect global, localand random effects/correlationsFin height - width variability: can’t amortize over wider fingers Can only have integer numbers of finsChanges in device parasitic R, C compared to usual expectations page 12 of 29G-S cap (Miller cap), S, D contact resistance

Trigate/FinFET Devices: Variabilitys[VT], mV40PlanarReduced RDF-relatedVT variability for FINFETs30Bulk FinFET( 25-50% depending on design)20eg. M. Jurczak et al,10000551/ (WL) (mm-1)100s[VTsat], mVpFET50Proc. 2009 IEEE Int, SOI Conf.SOI FinFET10101 finLER-relatedVT variability for FINFETs2 fins20,10,5 finsnFETeg. E. Baravelli et al,IEEE T. Nanotechnol. 7,p. 291 (2008).01/ (number of fins)Warning: considerable spread in reported literature: your mileage may varypage 13 of 29

Trigate/FinFET Devices: QuantizationDevice Strength (arb Units)finFET DevicesConventional Devices10.8Example: min size finFET INVLower VT(more perf.)Can have p:n ratio 1, 0.5, 2(nothing in between)0.6Also, even a “wide” device willalways be just a collectionof very narrow devices 0.40.2Higher VT(less leakage)0Plus, expect difficulty to createmultiple VT offerings in afully depleted device scenario0 1 2 3 4 5 6 7 8 9DeviceWidth(ratio(Units ofwidthdevice)DeviceWidthtoMinminwidthdevice) Likely to create most difficulty for SRAM, register file designs Also small feedback devices, keepers, etc. Issue for any device tuner, other tools expecting continuous width rangespage 14 of 29

Trigate/FinFET Devices: Parasitics Resistance in contacts to fins might be tricky: assume it can be handledby device engineers! What about G-S cap?SDGGSD Expect increase in Cgs comparedto planar structures Details will depend on fin vs trigate,fin pitch, height, thickness, etc. Might have to watch out for certaintypes of noise issues Might decrease static timingaccuracypage 15 of 29

Trigate/FinFET Devices: PD Issues Sea-of-fins technology is attractive: offers tightest fin pitch Additional constraint on PD cell image Vertical: Fin, metal pitches Horizontal: gate, metal pitchesMetal PitchGate PitchFin PitchMetal Pitchpage 16 of 29Example:12:16

FinFET PD Implications Higher fins - more current drive per unit area But technology minimum device width growsQuantization issues tougher to deal with Finer fin pitch - more current drive per unit area Can trade off shorter fin height with finer fin pitchSea-of-fins constraints, other litho-related constraints Net: stronger technology - PD interaction Library cell definition likely to be dependent on technology fin pitchWill need to find gear ratios (metal pitch vs fin pitch) that work welltogetherpage 17 of 29

Outline Introduction Classical CMOS Scaling: The End of the Road New Device Structures What do these structures mean for circuit designers? Wire Interconnects Reliability Conclusionspage 18 of 29

Wire Interconnect Scaling (or lack thereof ) Assume all logic scales with litho shrink factor Wire lengths then also would scaleBest case scenario: RC stays constant (“perfect scaling”) This is already painful, chip area generally hasn’t been shrinking! Data below shows expectations that wire delays will growsignificantly, even in scaled designs.Relative RC, scaled21.81.6ITRS data,but 1.4ITRSdata1.21050100M1 Metal Pitch (nm)page 19 of 29150

Wire Scaling Implications High-performance designs will not be able to tolerate suchlarge RC increases Will need coarser-pitch, faster wires (ie non-scaled wires) But also need fine-pitched wires to leverage technology density Result: push for more wiring interconnect layers (coarse-pitch) Will still need some number of fine-pitch layers as well for shortrun local connections Improved DA tools (routers) needed Optimize wire plane usage to limit technology complexityNegotiate through special design rules for the finest levelsVia optimization, especially at driver endTricky performance vs wireability tradeoffsMany wires will need “special” treatment page 20 of 29Increase width, push higher, add buffers, etc.

14nm Wires: PD Implications Complications from double-patterning lithography!X High-performance fat wires lead to local disruption Stitch Need to understand coloring for proper analysis Cap increasesMisalignmentCap constantCap decreasespage 21 of 29

14nm Wires: DPL How to make sure designs can be colored properly? Rules to guarantee colorability complicated, non-localColoring solution may be subject to external factors Need color-aware analysis for highest accuracy Correlated capacitance shifts Solution: color-aware toolset & design methodology Build in coloring info as design is constructedCorrect, DPL-aware solutions, by constructionpage 22 of 29

Outline Introduction Classical CMOS Scaling: The End of the Road New Device Structures What do these structures mean for circuit designers? Wire Interconnects Reliability Conclusionspage 23 of 29

Interconnect Reliability Reliability will become a significant focus item for designers in14nm technology Parameters below taken from ITRS, plotted WRT 2009 dataAssume constant voltage, const frequency for me atconstantcurrentdensity0.1Lifetime withexpectedcurrent (nm)Metal PitchPitch (nm)page 24 of 291150RelativeRelativeCurrentcurrent Densitydensity

Interconnect Reliability New materials likely needed for the finest-pitch planes Resistance increases likelyMore impetus to push signal wires higher in the stack TDDB concerns likely to push technology to higher K materials TTF (Arb Units Higher dielectric constant materials tend to have better reliabilityWire cap increase drives higher power, increased RCConcern again for finest-pitch planes 1E 09DielectricTEOSConstant4.23.62.92.21E 071E 051E 031E 01Ogawa et al,2003 IRPS1E-01024681012E (MV/cm) LER, defect-narrowing likely to exacerbate EM concernspage 25 of 29

Interconnect Reliability: Implications Will need efficient design tool solutions for robust reliability Likely many elements with current pushing close to reliability limitsMay need detailed understanding of local switching factors Local thermal effects likely significant for high-frequency logic IR heating by currents in fine wiresEM effects very sensitively dependent on temperatureWhat happens when hot wires are placed in close proximity? Answer: they get even hotter (and they heat up the surroundings)Need design tools to help avoid bad thermal situationsNeed thermal analysis tools to detect problematic local situations Increased overhead from error checking & recovery expected For high-reliability systems, checking alone is not enough!Need to be able to recover from hard errorsAbility to take processor cores offline gracefully page 26 of 29Replace with spare core?

Outline Introduction Classical CMOS Scaling: The End of the Road New Device Structures What do these structures mean for circuit designers? Wire Interconnects Reliability Conclusionspage 27 of 29

Conclusions Breakdown in scaling is pushing technology in new directions Limited voltage scaling for high-performance chips Power/power-density limited performanceMore constraints from lithography (DPL) FinFET device structures new circuit/PD design challenges VT variability still likely to be a challenge Constraints from fin pitch, width quantization Biggest challenges for high-performance designs: wires Non-scaling RCReliabilityDPL makes everything tougher Circuit/system-level check/recovery features will need extraemphasis for high-reliability systemspage 28 of 29

Acknowledgements Thanks to L. Sigal, L. Liebmann for reviewing and commentingon material for this presentationpage 29 of 29

FinFET device structures new circuit/PD design challenges VT variability still likely to be a challenge Constraints from fin pitch, width quantization Biggest challenges for high-performance designs: wires Non-scaling RC Reliability DPL makes everything tougher Circuit/system-level check/recovery features will need extra