UM10462 LPC11Uxx User Manual - Strawberry-linux
UM10462LPC11Uxx User manualRev. 2.1 — 13 January 2012User manualDocument informationInfoContentKeywordsLPC11Uxx, ARM Cortex-M0, microcontroller, LPC11U12, LPC11U14,LPC11U13, USB, LPC11U23, LPC11U24AbstractLPC11Uxx User manual
UM10462NXP SemiconductorsLPC11Uxx User manualRevision historyRevDateDescription2.120120113LPC11Uxx User manualModifications: 220111214Description of PIOPOR1CAP register updated (see Table 34).LPM register added (Table 201).LPC11Uxx User manualModifications:120110414 Parts LPC11U2x added. Register bit description of PINTSEL registers corrected (see Section 3.5.33). Smart card application example updated (Section 12.6.2).Chapter 22 added.Part LPC11U14FHI33/201 added.Bit 10 (TD) changed to reserved for PIO0 4 and PIO0 5 registers (Table 65, Table 66).Register PIO1 29, bit description of FUNC bit updated: 0x0 PIO1 29 (Table 114).Section 20.16.4.7 “Algorithm and procedure for signature generation” updated.Update description of ISP command Blank check sectors (Table 346).Description of ISP Go command updated in Table 344.Description of SYSMEMREMAP register updated in Table 7.Requirement to enable the USART clock before the USART pins removed (seeChapter 3 and Section 12.2.Update the description of the address offset in for USB endpoint commands inTable 210.Chapter 10 added.Explanation of clock synchronization steps expanded in Section 17.6.Use of pins PIO0 3 and PIO0 1 clarified in Table 116.Description of power profiles updated (Section 5.3).LPM mode added in Chapter 11.Description of LOCK bit corrected in Table 315.Description of SYSRSTSTAT register updated (Table 15).Initial versionContact informationFor more information, please visit: http://www.nxp.comFor sales office addresses, please send an email to: salesaddresses@nxp.comUM10462User manualAll information provided in this document is subject to legal disclaimers.Rev. 2.1 — 13 January 2012 NXP B.V. 2012. All rights reserved.2 of 479
UM10462Chapter 1: LPC11Uxx Introductory informationRev. 2.1 — 13 January 2012User manual1.1 IntroductionThe LPC11Uxx are an ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for8/16-bit microcontroller applications, offering performance, low power, simple instructionset and memory addressing together with reduced code size compared to existing 8/16-bitarchitectures.The LPC11Uxx operate at CPU frequencies of up to 50 MHz. Equipped with a highlyflexible and configurable full-speed USB 2.0 device controller, the LPC11Uxx bringunparalleled design flexibility and seamless integration to today's demanding connectivitysolutions.The peripheral complement of the LPC11Uxx includes up to 32 kB of flash memory, up to8 kB of SRAM data memory, one Fast-mode Plus I2C-bus interface, one RS-485/EIA-485USART with support for synchronous mode and smart card interface, two SSP interfaces,four general purpose counter/timers, a 10-bit ADC, and up to 54 general purpose I/O pins.1.2 Features System:– ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.– ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).– Non Maskable Interrupt (NMI) input selectable from several input sources.– System tick timer. Memory:– Up to 32 kB on-chip flash program memory.– In-System Programming (ISP) and In-Application Programming (IAP) via on-chipbootloader software.– Total of 6 kB (4 kB main SRAM and 2 kB USB SRAM) SRAM data memory(LPC11U1x) or up to 10 kB (8 kB main SRAM and 2 kB USB SRAM) SRAM datamemory (LPC11U2x).– 16 kB boot ROM.– LPC11U2x only: Up to 4 kB on-chip EEPROM data memory; byte erasable andbyte programmable; on-chip API support. ROM based drivers:– Power profiles.– 32-bit integer division routines.– LPC11U2x only: ROM-based USB drivers. Flash updates via USB supported.Supports Human-Interface Device (HID) class, Mass Storage Device Class (MSC),and Communication Device Class (CDC).– LPC11U2x only: IAP EEPROM drivers.UM10462User manualAll information provided in this document is subject to legal disclaimers.Rev. 2.1 — 13 January 2012 NXP B.V. 2012. All rights reserved.3 of 479
UM10462NXP SemiconductorsChapter 1: LPC11Uxx Introductory information Debug options:– Standard JTAG test interface for BSDL.–Serial Wire Debug. Digital peripherals:– Up to 54 General Purpose I/O (GPIO) pins with configurable pull-up/pull-downresistors, repeater mode, and open-drain mode.– Up to eight GPIO pins can be selected as edge and level sensitive interruptsources.– Two GPIO grouped interrupt modules enables an interrupt based on aprogrammable pattern of input states of a group of GPIO pins.– High-current source output driver (20 mA) on one pin (P0 7).– High-current sink driver (20 mA) on true open-drain pins (P0 4 and P0 5).– Four general purpose counter/timers with a total of 4 capture inputs and 13 matchoutputs.– Programmable windowed WatchDog Timer (WDT) with a dedicated, internallow-power WatchDog Oscillator (WDO). Analog peripherals:– 10-bit ADC with input multiplexing among eight pins. Serial interfaces:– USB 2.0 full-speed device controller.– USART with fractional baud rate generation, internal FIFO, a full modem controlhandshake interface, and support for RS-485/9-bit mode and synchronous mode.USART supports an asynchronous smart card interface (ISO 7816-3).– Two SSP interfaces with FIFO and multi-protocol capabilities.– I2C-bus interface supporting the full I2C-bus specification and Fast-mode Plus witha data rate of up to 1 Mbit/s with multiple address recognition and monitor mode. Clock generation:– Crystal Oscillator with an operating range of 1 MHz to 25 MHz (system oscillator).– 12 MHz Internal high-frequency RC oscillator (IRC) that can optionally be used asa system clock.– Internal low-power, low-frequency WatchDog Oscillator (WDO) with programmablefrequency output.– PLL allows CPU operation up to the maximum CPU rate with the system oscillatoror the IRC as clock sources.– A second, dedicated PLL is provided for USB.– Clock output function with divider that can reflect the crystal oscillator, the mainclock, the IRC, or the watchdog oscillator. Power control:– Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deeppower-down.– Power profiles residing in boot ROM allow optimized performance and minimizedpower consumption for any given application through one simple function call.UM10462User manualAll information provided in this document is subject to legal disclaimers.Rev. 2.1 — 13 January 2012 NXP B.V. 2012. All rights reserved.4 of 479
UM10462NXP SemiconductorsChapter 1: LPC11Uxx Introductory information– Processor wake-up from Deep-sleep and Power-down modes via reset, selectableGPIO pins, watchdog interrupt, BOD interrupt, or USB port activity.– Processor wake-up from Deep power-down mode using one special function pin.– Integrated PMU (Power Management Unit) to minimize power consumption duringSleep, Deep-sleep, Power-down, and Deep power-down modes.– Power-On Reset (POR).– Brownout detect with four separate thresholds for interrupt and forced reset. Unique device serial number for identification.Single 3.3 V power supply (1.8 V to 3.6 V).Temperature range 40 C to 85 C.Available as LQFP64, LQFP48, TFBGA48 packages, and as HVQFN33 in twopackage sizes: 5 x 5 x 0.85 mm and 7 x 7 x 0.85 mm. Pin-compatible to the ARM Cortex-M3 based LPC134x series.1.3 Ordering informationTable 1.Ordering informationType 01HVQFN33plastic thermal enhanced very thin quad flat package; no leads; 33terminals; body 7 7 0.85 mmn/aLPC11U12FBD48/201LQFP48plastic low profile quad flat package; 48 leads; body 7 7 1.4 mmSOT313-2LPC11U13FBD48/201LQFP48plastic low profile quad flat package; 48 leads; body 7 7 1.4 mmSOT313-2LPC11U14FHN33/201HVQFN33plastic thermal enhanced very thin quad flat package; no leads; 33terminals; body 7 7 0.85 mmn/aLPC11U14FHI33/201HVQFN33HVQFN: plastic thermal enhanced very thin quad flat package; noleads; 33 terminals; body 5 5 0.85 mmn/aLPC11U14FBD48/201LQFP48plastic low profile quad flat package; 48 leads; body 7 7 1.4 mmSOT313-2LPC11U14FET48/201TFBGA48plastic thin fine-pitch ball grid array package; 48 balls; body 4.5 4.5 0.7 mmSOT1155-2LPC11U23FBD48/301LQFP48plastic low profile quad flat package; 48 leads; body 7 7 1.4 mmSOT313-2LPC11U24FHI33/301HVQFN33plastic thermal enhanced very thin quad flat package; no leads; 33terminals; body 5 5 0.85 mmn/aLPC11U24FBD48/301LQFP48plastic low profile quad flat package; 48 leads; body 7 7 1.4 mmSOT313-2LPC11U24FET48/301LQFP48plastic low profile quad flat package; 48 leads; body 7 7 1.4 mmSOT313-2LPC11U24FHN33/401HVQFN33plastic thermal enhanced very thin quad flat package; no leads; 33terminals; body 7 7 0.85 mmn/aSOT313-2LPC11U24FBD48/401LQFP48plastic low profile quad flat package; 48 leads; body 7 7 1.4 mmLPC11U24FBD64/401LQFP64plastic low profile quad flat package; 64 leads; body 10 10 1.4 mm SOT314-2UM10462User manualAll information provided in this document is subject to legal disclaimers.Rev. 2.1 — 13 January 2012 NXP B.V. 2012. All rights reserved.5 of 479
UM10462NXP SemiconductorsChapter 1: LPC11Uxx Introductory informationTable 2.Part ordering optionsPart NumberFLASH(kB)MAIN USBSRAM SRAM(kB)(kB)EEPROM USB I2C/(kB)Fast SSP 267x7 N/A1128265x5 HVQFN33LPC11U14FHN33/2013242N/A1128267x7 21112840LQFP48LPC11U24FHI33/301326221128265x5 28267x7 BD64/40132824112854LQFP64UM10462User manualAll information provided in this document is subject to legal disclaimers.Rev. 2.1 — 13 January 2012 NXP B.V. 2012. All rights reserved.6 of 479
UM10462NXP SemiconductorsChapter 1: LPC11Uxx Introductory information1.4 Block diagramSWD, JTAGXTALIN XTALOUTLPC11U12/13/14RESETSYSTEM OSCILLATORCLOCKGENERATION,POWER CONTROL,SYSTEMFUNCTIONSIRC, WDOTEST/DEBUGINTERFACEBODPORARMCORTEX-M0PLL0system busFLASH16/24/32 kBslaveGPIO ports 0/1HIGH-SPEEDGPIOCLKOUTROM16 kBSRAM6 kBslaveUSB PLLmasterslaveslaveAHB-LITE BUSslaveUSB DPUSB DMUSB VBUSUSB FTOGGLE,USB CONNECTUSB DEVICECONTROLLERslaveRXDTXDDCD, DSR(1), RI(1)CTS, RTS, DTRSCLKCT16B0 MAT[1:0]CT16B0 CAP0CT16B1 MAT[1:0]CT16B1 CAP0CT32B0 MAT[3:0]CT32B0 CAP0CT32B1 MAT[3:0]CT32B1 CAP[1:0](2)AHB TO APBBRIDGEUSART/SMARTCARD INTERFACEAD[7:0]10-bit ADCSCL, SDAI2C-BUS16-bit COUNTER/TIMER 0SSP0SCK0, SSEL0,MISO0, MOSI0SSP1SCK1, SSEL1,MISO1, MOSI116-bit COUNTER/TIMER 132-bit COUNTER/TIMER 0IOCON32-bit COUNTER/TIMER 1SYSTEM CONTROLWINDOWED WATCHDOGTIMERGPIO pinsGPIO INTERRUPTSGPIO pinsGPIO GROUP0 INTERRUPTSGPIO pinsGPIO GROUP1 INTERRUPTSPMU002aaf885(1) Function not available on the HVQFN33 package.(2) CT32B1 CAP1 is only available on the TFBGA48 package.Fig 1.Block diagram (LPC11U1x)UM10462User manualAll information provided in this document is subject to legal disclaimers.Rev. 2.1 — 13 January 2012 NXP B.V. 2012. All rights reserved.7 of 479
UM10462NXP SemiconductorsChapter 1: LPC11Uxx Introductory informationSWD, JTAGXTALIN XTALOUTLPC11U2xSYSTEM OSCILLATORTEST/DEBUGINTERFACEBODGPIO ports 0/1CLKOUTPORPLL0EEPROM1/2/4 kBFLASH24/32 kBslaveHIGH-SPEEDGPIOCLOCKGENERATION,POWER CONTROL,SYSTEMFUNCTIONSIRC, WDOARMCORTEX-M0system busRESETROM16 kBSRAM8/10 kBslaveUSB PLLmasterslaveslaveAHB-LITE BUSslaveUSB DPUSB DMUSB VBUSUSB FTOGGLE,USB CONNECTUSB DEVICECONTROLLERslaveRXDTXDDCD(1), DSR(1), RI(1)CTS, RTS, DTRSCLKCT16B0 MAT[1:0]CT16B0 CAP0CT16B1 MAT[1:0]CT16B1 CAP0CT32B0 MAT[3:0]CT32B0 CAP0CT32B1 MAT[3:0]CT32B1 CAP[1:0](2)AHB TO APBBRIDGEUSART/SMARTCARD INTERFACEAD[7:0]10-bit ADCSCL, SDAI2C-BUS16-bit COUNTER/TIMER 0SSP0SCK0, SSEL0,MISO0, MOSI0SSP1SCK1, SSEL1,MISO1, MOSI116-bit COUNTER/TIMER 132-bit COUNTER/TIMER 0IOCON32-bit COUNTER/TIMER 1SYSTEM CONTROLWINDOWED WATCHDOGTIMERGPIO pinsGPIO INTERRUPTSGPIO pinsGPIO GROUP0 INTERRUPTSGPIO pinsGPIO GROUP1 INTERRUPTSPMU002aag333Fig 2.Block diagram (LPC11U2x)UM10462User manualAll information provided in this document is subject to legal disclaimers.Rev. 2.1 — 13 January 2012 NXP B.V. 2012. All rights reserved.8 of 479
UM10462Chapter 2: LPC11Uxx Memory mappingRev. 2.1 — 13 January 2012User manual2.1 How to read this chapterSee Table 3 for the memory configuration of the LPC11Uxx parts.Table 3.LPC11Uxx memory configurationPartFlashMain SRAMUSB SRAMEEPROMReferenceLPC11U12FHN33/20116 kB4 kB2 kBn/aFigure 3LPC11U12FBD48/20116 kB4 kB2 kBn/aFigure 3LPC11U13FBD48/20124 kB4 kB2 kBn/aFigure 3LPC11U14FHN33/20132 kB4 kB2 kBn/aFigure 3LPC11U14FHI33/20132 kB4 kB2 kBn/aFigure 3LPC11U14FBD48/20132 kB4 kB2 kBn/aFigure 3LPC11U14FET48/20132 kB4 kB2 kBn/aFigure 3LPC11U23FBD48/30124 kB6 kB2 kB1 kBFigure 4LPC11U24FHI33/30132 kB6 kB2 kB2 kBFigure 4LPC11U24FBD48/30132 kB6 kB2 kB2 kBFigure 4LPC11U24FET48/30132 kB6 kB2 kB2 kBFigure 4LPC11U24FHN33/40132 kB8 kB2 kB4 kBFigure 4LPC11U24FBD48/40132 kB8 kB2 kB4 kBFigure 4LPC11U24FBD64/40132 kB8 kB2 kB4 kBFigure 42.2 Memory mapThe LPC11Uxx incorporates several distinct memory regions, shown in the followingfigures. Figure 3 shows the overall map of the entire address space from the userprogram viewpoint following reset.The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals.The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals.Each peripheral of either type is allocated 16 kB of space. This allows simplifying theaddress decoding for each peripheral.UM10462User manualAll information provided in this document is subject to legal disclaimers.Rev. 2.1 — 13 January 2012 NXP B.V. 2012. All rights reserved.9 of 479
UM10462NXP SemiconductorsChapter 2: LPC11Uxx Memory mapping4 GBLPC11U12/13/140xFFFF FFFFreserved0xE010 0000private peripheral bus0xE000 0000reservedAPB peripherals0x5000 4000GPIO25 - 31 reserved0x5000 0000reserved0x4008 4000USB1 GBGPIO GROUP1 INT23GPIO GROUP0 INT22SSP10x4008 0000APB peripherals20 - 21 reserved0x4000 000019GPIO interrupts18system control0x2000 480017IOCON0x2000 40001615SSP0flash controller14PMUreserved2 kB USB RAM0.5 GB24reserved0x2000 0000reserved0x4008 00000x4006 40000x4006 00000x4005 C0000x4005 80000x4004 C0000x4004 C0000x4004 80000x4004 40000x4004 00000x4003 C0000x4003 800010 - 13 reserved0x1FFF 400016 kB boot ROM0x4002 80000x1FFF 00009reserved8reserved0x4002 00007ADC0x4001 C000632-bit counter/timer 10x4001 80000x1000 1000532-bit counter/timer 00x4001 40000x1000 0000416-bit counter/timer 10x4001 0000316-bit counter/timer 00x4000 C0002USART/SMART CARD0x4000 800010WWDT0x4000 4000I2C-bus0x4000 0000reserved4 kB SRAMreserved0x0000 800032 kB on-chip flash (LPC11U14)0x0000 600024 kB on-chip flash (LPC11U13)0x0000 400016 kB on-chip flash (LPC11U12)0x4002 40000x0000 00C0active interrupt vectors0x0000 00000x0000 00000 GB002aaf891SSP1 available on 48-pin packages only.Fig 3.LPC11U1x memory mapUM10462User manualAll information provided in this document is subject to legal disclaimers.Rev. 2.1 — 13 January 2012 NXP B.V. 2012. All rights reserved.10 of 479
UM10462NXP SemiconductorsChapter 2: LPC11Uxx Memory mapping4 GBLPC11U23/240xFFFF FFFFreserved0xE010 0000private peripheral bus0xE000 0000reservedAPB peripherals0x5000 4000GPIO25 - 31 reserved0x5000 0000reserved0x4008 4000USB1 GBGPIO GROUP1 INT23GPIO GROUP0 INT22SSP10x4008 0000APB peripherals20 - 21 reserved0x4000 000019GPIO interrupts18system control0x2000 480017IOCON0x2000 40001615SSP0flash/EEPROM controller14PMUreserved2 kB USB RAM0.5 GB24reserved0x2000 0000reserved0x4006 40000x4006 00000x4005 C0000x4005 80000x4004 C0000x4004 C0000x4004 80000x4004 40000x4004 00000x4003 C0000x4003 800010 - 13 reserved0x1FFF 400016 kB boot ROM0x4002 80000x1FFF 00009reserved8reserved0x4002 00007ADC0x4001 C000632-bit counter/timer 10x4001 80000x1000 1800532-bit counter/timer 00x4001 40000x1000 0000416-bit counter/timer 10x4001 0000316-bit counter/timer 00x4000 C0002USART/SMART CARD0x4000 800010WWDT0x4000 4000I2C-bus0x4000 0000reserved0x1000 20008 kB SRAM (LPC11U2x/301)6 kB SRAM (LPC11U2x/401)reserved0x0000 800032 kB on-chip flash (LPC11U24)0x0000 60000x4002 40000x0000 00C0active interrupt vectors24 kB on-chip flash (LPC11U23)0 GB0x4008 00000x0000 00000x0000 0000002aag594Fig 4.LPC11U2x memory mapUM10462User manualAll information provided in this document is subject to legal disclaimers.Rev. 2.1 — 13 January 2012 NXP B.V. 2012. All rights reserved.11 of 479
UM10462Chapter 3: LPC11Uxx System control blockRev. 2.1 — 13 January 2012User manual3.1 How to read this chapterThe system control block is identical for all LPC11Uxx parts.3.2 IntroductionThe system configuration block controls oscillators, some aspects of the powermanagement, and the clock generation of the LPC11Uxx. Also included in this block is aregister for remapping flash, SRAM, and ROM memory areas.3.3 Pin descriptionTable 4 shows pins that are associated with system control block functions.Table 4.Pin summaryPin namePindirectionPin descriptionCLKOUTOClockout pinPIO0 and PIO1 pinsIEight pins can be selected as external interruptpins from all available GPIO pins (see Table 39).3.4 Clocking and power controlSee Figure 5 for an overview of the LPC11Uxx Clock Generation Unit (CGU).The LPC11Uxx include three independent oscillators. These are the system oscillator, theInternal RC oscillator (IRC), and the Watchdog oscillator. Each oscillator can be used formore than one purpose as required in a particular application.Following reset, the LPC11Uxx will operate from the Internal RC oscillator until switchedby software. This allows systems to operate without an external crystal and the bootloadercode to operate at a known frequency.The SYSAHBCLKCTRL register gates the system clock to the various peripherals andmemories. USART and SSP have individual clock dividers to derive peripheral clocksfrom the main clock.The main clock, and the clock outputs from the IRC, the system oscillator, and thewatchdog oscillator can be observed directly on the CLKOUT pin.UM10462User manualAll information provided in this document is subject to legal disclaimers.Rev. 2.1 — 13 January 2012 NXP B.V. 2012. All rights reserved.12 of 479
UM10462NXP SemiconductorsChapter 3: LPC11Uxx System control blockSYSTEM CLOCKDIVIDERCPU, system control,PMUsystem clocknmemories,peripheral clocksSYSAHBCLKCTRLn(AHB clock enable)IRC oscillatormain clockSSP0 PERIPHERALCLOCK DIVIDERSSP0USART PERIPHERALCLOCK DIVIDERUARTSSP1 PERIPHERALCLOCK DIVIDERSSP1USB 48 MHz CLOCKDIVIDERUSBCLKOUT PIN CLOCKDIVIDERCLKOUT pinwatchdog oscillatorMAINCLKSEL(main clock select)IRC oscillatorSYSTEM PLLsystem oscillatorSYSPLLCLKSEL(system PLL clock select)USB PLLsystem oscillatorUSBPLLCLKSEL(USB clock select)USBUEN(USB clock update enable)IRC oscillatorsystem oscillatorwatchdog oscillatorCLKOUTUEN(CLKOUT update enable)IRC oscillatorWDTwatchdog oscillatorCLKSEL(WDT clock select)002aaf892Fig 5.LPC11Uxx CGU block diagram3.5 Register descriptionAll system control block registers are on word address boundaries. Details of the registersappear in the description of each function.UM10462User manualAll information provided in this document is subject to legal disclaimers.Rev. 2.1 — 13 January 2012 NXP B.V. 2012. All rights reserved.13 of 479
UM10462NXP SemiconductorsChapter 3: LPC11Uxx System control blockIn addition to the system control block registers described in Table 5, the flash accesstiming register, which can be re-configured as part the system setup, is described inTable 6. This register is not part of the system configuration block.All address offsets not shown in Table 5 and Table 6 are reserved and should not bewritten.Table 5.Register overview: system control block (base address 0x4004 8000)NameAccessOffsetDescri
For sales office addresses, please send an email to: salesaddresses@nxp.com NXP Semiconductors UM10462 LPC11Uxx User manual Revision history Rev Date Description 2.1 20120113 LPC11Uxx User manual Modifications: Description of PIOPOR1CAP register updated (see Table 34). LPM register added (Table 201 ). 2 20111214 LPC11Uxx User manual .
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The principal parts of the strawberry flower are shown in Fig. 9. Sepals are the small green leaflike structures below the white petals – they enclose the flower at the bud stage, and later on this leaflike tissue is referred to as the berry’s calyx, or “cap.” The strawberry flower has 5 sepals.
v Dedication The Strawberry Production Guide for the Northeast, Midwest, and Eastern Canada is dedicated to Dr. Gene Galletta, strawberry breeder at the United States Department of Agriculture–Agricult
Organic strawberry production systems generally share five common characteristics, described in the Strawberry Production Guide for the Northeast, Midwest, and Eastern Canada, NRAES-88: 1. Several years elapse between successive strawberry crop
The American Petroleum Institute (API) 617 style compressors are typically found in refinery and petrochemical applications. GE strongly recommends the continuous collection, trending and analysis of the radial vibration, axial position, and temperature data using a machinery management system such as System 1* software. Use of these tools will enhance the ability to diagnose problems and .
