AN2871 Application Note - STMicroelectronics
AN2871Application noteSPC560Pxx/SPC56APxx HW design guidelineIntroductionThis application note is intended for hardware designers. It gives hardware designreferences on SPC560Pxx/SPC56APxx microcontroller. Four topics are covered: Voltage Regulator (VREG) Main oscillator Supply pins Reference Reset circuitSeptember 2013Doc ID 15304 Rev 31/25www.st.com
ContentsAN2871Contents1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52On-chip voltage regulator (VREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62.12.234VREG design guideline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62.1.1Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62.1.2Circuit architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.1.3Recommended transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Frequency-modulated phase-locked loop (FMPLL) . . . . . . . . . . . . . . . . . 12Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143.1Reference oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143.2Approved crystals and resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.3Oscillator and electromagnetic compatibility (EMC) . . . . . . . . . . . . . . . . . 16Supply pins and decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174.1Supply pins description and circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174.1.1Internal supply decoupling capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . 184.1.2Specific supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204.1.3Power-on current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204.1.4Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215Unused pin management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226Reference reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242/25Doc ID 15304 Rev 3
AN2871List of tablesList of tablesTable 1.Table 2.Table 3.Table 4.Table 5.Table 6.Table 7.Table 8.Approved NPN ballast transistor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8ON Semiconductor datasheet: BCP68 electrical characteristics at 25 C . . . . . . . . . . . . . . 8NXP datasheet: BC817-25 electrical characteristics at 25 C . . . . . . . . . . . . . . . . . . . . . . . 9Zetex datasheet: BCX68-25 electrical characteristics at 25 C . . . . . . . . . . . . . . . . . . . . . 10Approved Crystals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Approved Resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Supply pins on SPC560P50XX LQFP144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Doc ID 15304 Rev 33/25
List of figuresAN2871List of figuresFigure 1.Figure 2.Figure 3.Figure 4.Figure 5.Figure 6.Figure 7.Figure 8.Figure 9.4/25External NPN ballast connections configuration forSPC560P60xx/SPC56AP60xx/SPC560P40xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7External NPN ballast connections configuration for SPC560P50xx . . . . . . . . . . . . . . . . . . . 7ON Semiconductor BCP68 datasheet: example of temperature response. . . . . . . . . . . . . . 9Example of temperature response from NXP BC817-25 . . . . . . . . . . . . . . . . . . . . . . . . . . 10Reference oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Decoupling of 1.2 V rail. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Pin supply circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Reference reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Doc ID 15304 Rev 3
AN28711OverviewOverviewSPC560Pxx/SPC56APxx microcontrollers are members of a family of microcontrollers builton Power Architecture technology. The device is supplied externally with a single voltagesupply, which can be either 5 V or 3.3 V depending on application requirements. Internally,the chip operates with two supply voltages, namely the main supply (5 V or 3.3 V) and thecore logic supply (1.2 V).Doc ID 15304 Rev 35/25
On-chip voltage regulator (VREG)2AN2871On-chip voltage regulator (VREG)The SPC560Pxx device can be supplied with 5 V 10% or 3.3 V 10 % (4.5 – 5.5 V or3.0 – 3.6 V, respectively) to suit different applications. Additionally, the on-chip linear voltageregulator generates a reference voltage enabling the regulation of the 1.2 V via an externalballast transistor (with a specified tolerance 1.15 – 1.32 V) from the external 3.3 V/5 Vvoltage supply (VDD HV REG supply pin).The on-chip voltage regulator module provides the following features: Uses external NPN (Negative-Positive-Negative) transistor Regulates external 3.3 V–5.0 V down to 1.2 V for the core logic Low voltage detection on the internal 1.2 V and I/O voltage 3.3 V2.1VREG design guideline2.1.1Voltage regulatorThe on-chip voltage regulator module regulates the external 3.3 V–5.0 V supply down to1.2 V for the core logic. The nominal target output is 1.2 V. Due to variations the actualoutput will be in the range of 1.15–1.32 V in the full current load range (0–200 mA) afterfactory trimming.The internal voltage regulator requires an external NPN ballast transistor, approvedtransistor list available in Table 1, to be connected as shown in Figure 1 for SPC560P40xx,SPC560P60xx/SPC56AP60xx and Figure 2 for SPC560P50xx. Capacitances, CDEC1,CDEC2,CDEC3, should be placed on the board as near as possible to the associated pins.Care should also be taken to limit the serial inductance of the board to less than LREG asdescribed in the device datasheet.The device cannot be used with an external 1.2 V supply. Always use the external ballasttransistor to generate the 1.2 V supply to the core.6/25Doc ID 15304 Rev 3
AN2871On-chip voltage regulator (VREG)Figure 1.External NPN ballast connections configuration forSPC560P60xx/SPC56AP60xx/SPC560P40xxVDD HV REGSPC56xxCDEC3BJTBCTRLVDD LV CORCDEC2Figure 2.CDEC1External NPN ballast connections configuration for SPC560P50xxVDD HV REGSPC56xxCDEC3BJTBCTRLRBVDD LV CORCDEC22.1.2CDEC1Circuit architectureThe VREG circuit is a classic emitter-follower configuration controlled voltage source. Thestabilization of the output voltage is achieved using an external capacitance of several µF(see Section 4).The BCTRL (voltage regulator external NPN ballast base control pin) controls the current onthe base of the transistor. Current is increased to raise the voltage on VDD. Current isdecreased to lower the voltage. The gain of the transistor controls the maximum currentavailable on VDD from the supply.The gain should be high enough to allow start-up and low enough to prevent the VREGbecoming instable.Doc ID 15304 Rev 37/25
On-chip voltage regulator (VREG)2.1.3AN2871Recommended transistorsTransistor specifications give the minimum and maximum gain. The worst case is usuallysignificantly lower than the nominal figure on the transistor datasheet cover page. Moreover,the datasheet values are usually given at room temperature.The required gain should be calculated at cold temperature, because a bipolar transistorhas minimum gain at low temperature. The worst case gain at cold temperature can beobtained from the transistor manufacturer or can be estimated using the graphs given in thetransistor datasheet.The Table 1 lists the recommended ballast transistors.Table 1.Approved NPN ballast transistorPartManufacturerApproved derivatives(1)ON 25STBCP56-16InfineonBCP56-10;BCP56-16ON SemiBCP56-10BCP56NXPBCP56-10;BCP56-161. For automotive applications please check with the appropriate transistor vendor for automotive gradecertificationIn the following, as example, are shown parameters of BCP68 and BC817 transistors.BCP68 NPN bipolar 1 A/1.5 W SOT223This transistor is available from several semiconductor makers.Table 2.ON Semiconductor datasheet: BCP68 electrical characteristics at 25 CSymbolhFE8/25Parameter—DC current gainIC 5.0 mA; VCE 10 VDCIC 150 mA; VCE 1 VDCIC 1.0 mA; VCE 1 VDCDoc ID 15304 Rev 3MinTypMax508560————375—Unit—
AN2871On-chip voltage regulator (VREG)Figure 3.ON Semiconductor BCP68 datasheet: example of temperature responseFor the example datasheet, the minimum gain at room temperature is 85. At 40 C, thetransistor has an estimated gain of 54.BC817-25 NPN bipolar 0.5A SOT23This transistor is available from several semiconductor maker.Table 3.NXP datasheet: BC817-25 electrical characteristics at 25 CSymbolhFEParameter—DC current gainIC 100 mA; VCE 1 VDCIC 500 mA; VCE 1 VDCDoc ID 15304 Rev 3MinTypMaxUnit16040——400——9/25
On-chip voltage regulator (VREG)Figure 4.Note:AN2871Example of temperature response from NXP BC817-25The BC817-16 variant is also compatible with the SPC560Px voltage regulator.BCX68-25 NPN bipolar 0.5 A SOT89This transistor is available from several semiconductor makers.Table 4.Zetex datasheet: BCX68-25 electrical characteristics at 25 CSymbolhFENote:Parameter—DC current gainIC 500 mA; VCE 1 VDCMinTypMaxUnit160—400—BCX68-16 and BCX68-10 variants are also compatible with the SPC560Px voltageregulator.Summary of proposed ballast transistorsThe transistors list of Table 1 has been validated by simulations. To offer several options toECU designers, various packages are proposed: SOT223 for BCP68 SOT89 for BCX68-25, BCX68-16, and BCX68-10 SOT23 for BC817-25 and BC817-16Please note that the SOT23 package has a high thermal resistance and is not suited for thefull automotive temperature range.BC817-25 is also offered in the SC74 package, which has a better thermal resistance butthat still does not allow using this transistor in the full temperature range.The SOT23 and SC74 packages should be considered for applications such as airbags.10/25Doc ID 15304 Rev 3
AN2871On-chip voltage regulator (VREG)External transistor power dissipationThe power dissipation required by the bypass transistor is dependent upon the voltage dropacross it, the core current and the selected supply range.The worst case power dissipation of the ballast transistor is with a 5 V supply. Assuming theCPU draws 100 mA (please check figure according to your configuration in the latestSPC560Pxx/SPC56APxx datasheet), the worst case voltage drop with 5 V 10% supply is4.35 V (that is, 5.5 V 1.15 V 4.35 V). This leads to about 0.435 W of power dissipation.Ballast transistor junction temperatureThe ballast transistor maximum junction temperature is typically 150 C, although in sometransistors it may be as high as 165 C.Depending on the maximum ambient temperature, the ballast transistor may have a limitedallowed temperature rise and thus requires adequate heatsinking. Thermal characteristicsof the board and heatsink are required for this calculation.Ballast transistor VCEsatTo reduce the power dissipation in the transistor, it is permissible to add a series resistor thatwill drop the collector voltage. If this is used, the saturation voltage becomes significant; thetransistor must remain out of saturation with the minimum expected supply (5.0 V or 3.3 V)and the maximum expected Vcore rail (that is, 1.32 V).Ballast transistor inductanceThe distance from the ballast transistor's heatsink rail to the microcontroller will lead toinductance in the system (the greater the distance, the higher the inductance). The locationof the transistor will also affect the inductance, due to the lengths of the 1.2 V traces and ofthe BCTRL signal. Those inductances will reduce the phase margin. It is recommended thatthe inductance on BCTRL and on 1.2 V is kept below 15 nH.Due to variations in board type, specific details on trace length specification cannot beprovided; consequently, inductance values have been given.Calculation examplesNote:The following examples demonstrate how ballast transistors can be selected and how chipjunction temperature can be estimated. The data used in the examples are fictional andshould not be taken as specifications for particular systems. For specific calculations, pleaserefer to the device datasheet.Doc ID 15304 Rev 311/25
On-chip voltage regulator (VREG)AN2871Example 1: SPC560P50, 64 MHz in motor control mode PowerMaximum steady state MCU current: 100 mAMaximum collector voltage 5.0 V 10% 5.5 VMinimum emitter voltage: 1.15 VRequired power (5.5 V 1.15 V) * 0.1 435 mWProposed transistor: BCP68 in SOT223 TemperatureTarget system ambient 125 CSOT223 TJC junction-to-case 17 C/WFR4 with thermal vias for SOT223 12 C/WHeatsink to ambient 3 C (depends upon power loading in target system)Junction temperature (125 C 3 C) (12 C/W 17 C/W) * 0.442 W 141 CExample 2: SPC560P50, 64 MHz in airbag mode PowerMaximum steady state MCU current: 66 mAMaximum collector voltage 3.3 V 10% 3.6 VMinimum emitter voltage: 1.15 VRequired power (3.6 V 1.15 V) * 0.066 162 mWProposed transistor: BCP68 in SOT223 TemperatureTarget system ambient 105 CSOT223 TJC junction-to-case 17 C/WFR4 with thermal vias for SOT223 12 C/WHeatsink to ambient 3 C (depends upon power loading in target system)Junction temperature (105 C 3 C) (12 C/W 17 C/W) * 0.131 W 112 C2.2Frequency-modulated phase-locked loop (FMPLL)The FMPLL allows the user to generate high speed system clocks from a 4 MHz to 40 MHzinput clock. Furthermore, the FMPLL supports programmable frequency modulation of thesystem clock.12/25Doc ID 15304 Rev 3
AN2871On-chip voltage regulator (VREG)The PLL has the following major features: Input clock frequency from an 4 MHz to 40 MHz Voltage controlled oscillator (VCO) range from 256 MHz to 512 MHz Reduced frequency divider (RFD) for reduced frequency operation without forcing thePLL to relock Frequency-modulated PLL –Modulation enabled/disabled through software–Triangle wave modulationProgrammable modulation depth ( 0.25% to 4% deviation from center frequency)–Programmable modulation frequency dependent on reference frequency Self-clocked mode (SCM) operation Input supply same as core supply: 1.2 VFMPLL supply is shorted with core, without impact on jitter.At least a couple of 470 pF and 440 nF ceramic capacitors should be placed between theVDD LV COR3/VSS LV COR3 pair (VDD LV COR0/VSS LV COR0 for SPC560P40xx).Doc ID 15304 Rev 313/25
Main oscillator3AN2871Main oscillatorSPC560Pxx devices can run with an external oscillator used as input for the PLLs, andselected also as the system clock source. The main oscillator provides these features:3.1 Frequency range: 4–40 MHz Crystal input mode or Oscillator input mode PLL reference Oscillator supply: for noise immunity reasons, the oscillator supply uses dedicatedsupply pins VDD HV OSC/VSS HV OSC instead of the 1.2 V supplyReference oscillator circuitFigure 5 provides a schematic of the on-chip oscillator. This section describes the key items.Figure 5.Reference oscillator circuitR1 0 C1 22 pFVSS HV OSC0XTALSPC560PxxR2 1 M XTAL 8 MHzVSS HV OSC0EXTALDO NOT POPULATEC2 22 pFThe oscillator circuit provides a reference clock signal to the on-chip PLL. The oscillatorcircuit consists of the following components:Note: Bias resistor (R1) Crystal Two capacitors External bias resistor (R2)The external resistor (R2) is not recommended due to the fact that the oscillator has aninternal bias resistor. However, it is recommended to leave room for an external bias resistorto allow the PCB design to accommodate different crystals.Oscillator hardware recommendations:14/25 Use the lowest frequency crystal possible and set the multiplication factor bits to obtainthe proper system operating frequency which is generated from the PLL. The oscillator circuit has currents flowing at the crystal’s fundamental frequency. Also, ifthe oscillator is clipped, then higher order harmonics will be present as well. In order tominimize the amount of emissions generated from these currents, the oscillator circuitshould be kept as compact as possible.Doc ID 15304 Rev 3
AN2871Main oscillator Also, VSS HV OSC should be connected directly to the ground plane so that returncurrents can flow easily between VSS HV OSC and the two capacitors (C1 and C2). EXTAL Note:–Analog input of the oscillator amplifier circuit, when the oscillator is not in bypassmode–Analog input for the clock generator when the oscillator is in bypass mode.XTAL—Analog output of the oscillator amplifier circuit. Needs to be grounded ifoscillator is used in bypass mode.As the oscillator is an auto-gain version, a serial resistance (R1) is normally notrecommended. Please check with your crystal supplier.Figure 6.Oscillator characteristicsOn-chip Oscillator circuitEquivalent .2C2Approved crystals and resonatorsFollowing is a list of approved crystals and resonators. If you wish to use a crystal not on thislist please work with the crystal manufacturer to ensure compatibility.Table 5.Approved CrystalsCrystalNominalfrequencyNKD escapacitanceresistanceESRShuntCrystalmotionalLoad on xtalin/inductance(LI)C1 C2(pF)(1)(CI) pFxtaloutmHcapacitanceb/wxtalout 49Doc ID 15304 Rev 315/25
Main oscillatorAN28711. The values specified for C1 and C2 are the same as used in simulations. It should be ensured that the testing includes allthe parasitics (from the board, probe, crystal, etc.) as the AC / transient behavior depends upon them.2. The value of C0 specified here includes 2 pF additional capacitance for parasitics (to be seen with bond-pads, package,etc.).The CERALOCK resonators listed below have also been approved for use on allSPC560Pxx devices based on the e200z0 core.Table 6.PartnumberApproved ResonatorsVibrationFa-FrFrFaRaR1L1(dF)[kHz] [kHz][ohm] [ohm] FCSTCR4M00G53-R0Fundamental3929. 4163.0.8444 1.942 15.85 1630.9233.75 372.41 . 4123.0.8824 1.889 15.90 1899.7225.00 465.03 11.380000417537739393.3Oscillator and electromagnetic compatibility (EMC)The following rules and recommendations will help ensure an optimal layout and henceminimize EMC susceptibility:16/25 Avoid other high frequency signals near the oscillator circuitry as they can have anundesirable influence on the oscillator. Lay out/configure the ground supply on the basis of low impedance. Shield the crystal with an additional ground plane underneath the crystal. Do not lay out sensitive signals near the oscillator. Analyze cross-talk between differentlayers. The VSS pin close to the XTAL pi
Application note SPC560Pxx/SPC56APxx HW design guideline Introduction This application note is intended for hardware designers. It gives hardware design references on SPC560Pxx/SPC56APxx microcontroller. Four topics are covered: Voltage Regulator (VREG) Main oscillator Supply pins Reference Reset circuit www.st.com
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