ESP32Hardware Design GuidelinesVersion 3.0Espressif SystemsCopyright 2020www.espressif.com
About This DocumentThe guidelines outline recommended design practices when developing standalone or add-on systems based onthe ESP32 series of products, including ESP32 SoCs, ESP32 modules and ESP32 development boards.Document UpdatesPlease always refer to the latest version on ments.Revision HistoryFor the revision history of this document, please refer to the last page.Documentation Change NotificationEspressif provides email notifications to keep customers updated on changes to technical documentation. Pleasesubscribe at www.espressif.com/en/subscribe. Note that you need to update your subscription to receive notifications of new products you are not currently subscribed to.CertificationDownload certificates for Espressif products from www.espressif.com/en/certificates.Disclaimer and Copyright NoticeInformation in this document, including URL references, is subject to change without notice. THIS DOCUMENT ISPROVIDED AS IS WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, NON-INFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISEARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE.All liability, including liability for infringement of any proprietary rights, relating to use of information in this document is disclaimed. No licenses express or implied, by estoppel or otherwise, to any intellectual property rightsare granted herein. The Wi-Fi Alliance Member logo is a trademark of the Wi-Fi Alliance. The Bluetooth logo is aregistered trademark of Bluetooth SIG.All trade names, trademarks and registered trademarks mentioned in this document are property of their respectiveowners, and are hereby acknowledged.Copyright 2020 Espressif Systems (Shanghai) Co., Ltd. All rights reserved.
Contents1 Overview12 Schematic Checklist22.132.2Power Supply2.1.1 Digital Power Supply32.1.2 Analog Power Supply3Power-on Sequence and System Reset42.2.1 Power-on Sequence42.2.2 Reset52.3Flash (compulsory) and PSRAM (optional)52.4Crystal Oscillator52.4.1 External Clock Source (compulsory)62.4.2 RTC (optional)62.5RF72.6ADC82.7External Capacitor82.8UART92.9SDIO92.10 Touch Sensor103 PCB Layout Design113.111Standalone ESP32 Module3.1.1 General Principles of PCB Layout113.1.2 Positioning an ESP32 Module on a Base Board123.1.3 Power Supply133.1.4 Crystal Oscillator153.1.5 RF163.1.6 Flash & PSRAM173.1.7 External RC173.1.8 UART173.1.9 Touch Sensor183.2ESP32 as a Slave Device203.3Typical Layout Problems and Solutions213.3.1 Q: The current ripple is not large, but the TX performance of RF is rather poor.213.3.222Q: The power ripple is small, but RF TX performance is poor.3.3.3 Q: When ESP32 sends data packages, the power value is much higher or lower than the targetpower value, and the EVM is relatively poor.3.3.4 Q: TX performance is not bad, but the RX sensitivity is low.22224 Hardware Development235 Applications245.124ESP32 Smart Audio Platform
5.1.1 ESP32-LyraT Audio Development Board245.1.2 ESP32-LyraTD-MSC Audio Development Board255.2ESP32 Touch Sensor Application—ESP32-Sense Kit265.3ESP-Mesh Application—ESP32-MeshKit27Revision History28
List of Figures1ESP32 Schematics (ESP32-D0WD used as an example for all illustrations in this section)22ESP32 Digital Power Supply Pins33ESP32 Analog Power Supply Pins44ESP32 Flash and PSRAM55ESP32 Crystal Oscillator66Schematic for ESP32’s External Crystal (RTC)77Schematic of External Oscillator78ESP32 RF Matching Schematics89ESP32 External Capacitor910ESP32 UART911ESP32 PCB Layout1112ESP32 Module Antenna Position on Base Board1213Keepout Zone for ESP32 Module’s Antenna on the Base Board1314ESP32 Power Traces in a Four-layer PCB Design1415Nine-Grid Design for EPAD1416ESP32 Power Traces in a Two-layer PCB Design1517ESP32 Crystal Oscillator Layout1618ESP32 RF Layout in a Four-layer PCB Design1719ESP32 RF Layout in a Two-layer PCB Design1720ESP32 Flash and PSRAM Layout1821ESP32 UART Design1822A Typical Touch Sensor Application1923Electrode Pattern Requirements1924Sensor Track Routing Requirements2025PAD/TV Box Layout2126Top View of ESP32-LyraT2427Bottom View of ESP32-LyraT2528ESP32-LyraTD-MSC2629ESP32-Sense Kit2630ESP32-MeshKit-Light 2731ESP32-MeshKit-Sense Development Board27
1. OverviewESP32 is a single 2.4 GHz Wi-Fi and Bluetooth combo chip designed with TSMC ultra-low-power 40 nm technology. It is designed to achieve the best power and RF performance, robustness, versatility, and reliability in a widevariety of applications and different power profiles.ESP32 is a highly-integrated solution for Wi-Fi Bluetooth applications in the IoT industry with around 20 externalcomponents. ESP32 integrates the antenna switch, RF balun, power amplifier, low noise receive amplifier, filters,and power management modules. As such, the entire solution occupies minimal Printed Circuit Board (PCB)area.ESP32 uses CMOS for single-chip fully-integrated radio and baseband, and also integrates advanced calibrationcircuitries that allow the solution to dynamically adjust itself to remove external circuit imperfections or adjust tochanges in external conditions. As such, the mass production of ESP32 solutions does not require expensive andspecialized Wi-Fi test equipment.The ESP32 series of chips includes ESP32-D0WD-V3, ESP32-D0WDQ6-V3, ESP32-D0WD, ESP32-D0WDQ6,ESP32-D2WD, ESP32-S0WD, and ESP32-U4WDH, among which, ESP32-D0WD-V3, ESP32-D0WDQ6-V3, andESP32-U4WDH are based on ECO V3 wafer. For details of part number and ordering information, please refer toESP32 Datasheet. For details on ECO V3 instructions, please refer to ESP32 ECO V3 User Guide.Espressif Systems1Submit Documentation FeedbackESP32 Hardware Design Guidelines V3.0
2. Schematic ChecklistESP32’s integrated circuitry requires only 20 resistors, capacitors and inductors, one crystal and one SPI flash chip.ESP32 integrates the complete transmit/receive RF functionality including antenna switches, RF balun, power amplifier, low noise receive amplifier, filters, power management module, and advanced calibration circuitries.J11ThecapacitanceC1 design.and C2 ThisvariesESP32’s high integration allows forsimpleperipheral ofcircuitchapter details ESP32 schematics andwith the selection of the crystal.CON1PCB layout design. ESP32 schematic is shown in Figure ND0R 40MHz AP1CAP2VDDAXTAL PXTAL NVDDAGPIO21U0TXDU0RXDGPIO22GNDVDD331C4PCB ANTTBDC15C14TBDTBDGND GNDGNDGND1234C16SENSOR VP 5270pF(NC)67270pF(NC) SENSOR VN8CHIP LNA INVDD3P3VDD3P3SENSOR VPSENSOR CAPPSENSOR CAPNSENSOR VNCHIP PUVDET 1VDET 232K XP32K 24U2GPIO19VDD3P3 CPUGPIO23GPIO18GPIO5SD DATA 1SD DATA 0SD CLKSD CMDSD DATA 3SD DATA 2GPIO17VDD SD2GPIO171VDD DO/WP5SDI/SD12SDO/SD03SWP/SD3J281FLASHGPIO16C18 VDD 15GPIO2GPIO0GPIO4L4GPIO26GPIO27MTMSMTDIVDD3P3 RTCMTCKMTDOGPIO2GPIO0GPIO4GND GND GND 3100pFCON1GND C19CON10.1uFJ351GNDCON1Figure 1: ESP32 Schematics (ESP32-D0WD used as an example for all illustrations in this section)J371CON1Any basic ESP32 circuit design may be broken down into 10 major sections: Power supply Power-on sequence and system reset Flash and PSRAM (optional) Crystal oscillator RF ADC External capacitors UART SDIO Touch SensorEspressif Systems52Submit Documentation Feedback4ESP32 Hardware Design Guidelines V3.03
2.1 Power SupplyFor further details of using the power supply pins, please refer to Section Power Scheme in ESP32 Datasheet.2.1.1 Digital Power SupplyPin19 and pin37 are the power supply pins for RTC and CPU, respectively. The digital power supply operates ina voltage range of 1.8 V 3.6 V. We recommend adding extra filter capacitors of 0.1 µF close to the digital powerThe capacitance of C1 and C2 variessupply pins.with the selection of the crystal.VDD SDIO (pin26) works as the power supply for the related IO, and also for an external device. When VDD SDIO operates at 1.8 V, it can be generated from ESP32’s internal LDO. The maximum currentGNDthis LDO can offer is 40 mA, andthe output voltage range is 1.65 V 2.0 V. When the VDD SDIO outputs1.8 V, the value of GPIO12 should be set to 1 when the chip boots and it is recommended that users add aGND34GNDGND XOUTGNDU12 kΩ ground resistor and a 4.7 µF filtercapacitor close to VDD SDIO.C1 at 3.3 V, it is drivenC2 When VDD SDIO operatesdirectly by VDD3P3 RTC through a 6 Ω resistor, therefore,XINTBDTBDthere will be some voltage drop from VDD3P3 RTC. When the VDD SDIO outputs 3.3 V, the value of GPIO12100pFC202is 0 (default) when the chip boots and it is recommended that users add a 1 µF capacitor close to VDD SDIO.1C3GND1uFR1 be driven20K(5%) by an external power supply. When using VDD SDIO as the power supply pin forVDD SDIOcan alsoR2GNDGNDC5C60R supply40MHz /-10ppmexternal 3.3V flash/PSRAM,thevoltage should be 3.0 V or above, so as to meet the requirements 499Rflash/PSRAM’sworkingvoltage. The schematicforESP32 digital powersupply pins is shown in Figure 2.U0RXDC9GPIO22C4VDD330.1uFU2GPIO19VDD3P3 CPUGPIO23GPIO18GPIO5SD DATA 1SD DATA 0SD CLKSD CMDSD DATA 3SD DATA 2GPIO17VDD SDIOGPIO163837363534333231302928272625VDD IO16C18 VDD IO0GPIO4GNDVDDALNA INVDD3P3VDD3P3SENSOR VPSENSOR CAPPSENSOR CAPNSENSOR VNCHIP PUVDET 1VDET 232K XP32K XNGPIO25GPIO26GPIO27MTMSMTDIVDD3P3 RTCMTCKMTDOGPIO2GPIO0GPIO4TBD1234C16SENSOR VP 5270pF(NC)67270pF(NC) SENSOR VN8CHIP BD8NCVCC0.1uFGNDGNDC214C10GND2.0nHCAP1CAP2VDDAXTAL PXTAL 39GND490.1uF0.1uFGNDFigure 2: ESP32 Digital Power Supply Pins2.1.2 Analog Power SupplyPin1, pin3, pin4, pin43 and pin46 are the analog power supply pins. It should be noted that the sudden increasein current draw, when ESP32 is in transmission mode, may cause a power rail collapse. Therefore, it is highlyEspressif Systems3Submit Documentation FeedbackESP32 Hardware Design Guidelines V3.0
with the selection of the crysGNDrecommended to add another 10 µF capacitor to the power trace, which can work in conjunction with the 0.1 µFGND e schematic for ESP32 analog power supply pins is shown in Figure 3.U1GNDThe inductor’s rated current is preferably 500 mA and above.3GND4capacitor. LC filter circuit needs to be added near the power pin so as to suppress high-frequency .3V(10%)R2GND0R 40MHz /-10ppmR3499RC9C13C12C11C10C2110uFNC1uF0.1uFNCGND GND GND GNDANT12.0nHGNDL5CAP1CAP2VDDAXTAL PXTAL 14039GND490.1uFGND1GPIO192 VDDALNA INVDD3P3 CPU3GPIO234 VDD3P3C15C14C16GPIO18SENSOR VP 5 VDD3P3PCB ANTGPIO5TBDTBD270pF(NC)6 SENSOR VPSD DATA 17 SENSOR CAPPFigure 3: ESP32AnalogSENSOR VNPower SupplyPinsSD DATA 08 SENSOR CAPN270pF(NC)SD CLKGND GNDGNDCHIP PU9 SENSOR VNSD CMDC1710 CHIP PUGPIO34SD DATA 311 VDET 1GPIO35SD DATA 2Notice:12 VDET 2GPIO32GPIO1713 32K XPGPIO3332K XNVDD SDIO The recommended voltage of the power supply for ESP32is 3.3 V, andrecommended output current is 500 mA14 itsGPIO25GPIO25GPIO16TBD It is suggested that users add an ESD protection diode at the power entrance.2.2 Power-on Sequence and System Reset2.2.1 Power-on GPIO15GPIO2GPIO0GPIO4or more.GPIO26GPIO27MTMSMTDIVDD3P3 ESP32 uses a 3.3 V system power supply. The chip should be activated after the power rails have stabilized. Thisis achieved by delaying the activation of CHIP PU (Pin9) after the 3.3 V rails have been brought up. More detailscan be found in Section Power Scheme in ESP32 Datasheet.Notice:To ensure the power supply to the ESP32 chip during power-up, it is advised to add an RC delay circuit at theCHIP PU pin. The recommended setting for the RC delay circuit is usually R 10 kΩ and C 1 µF. However,specific parameters should be adjusted based on the power-up timing of the power supply and the power-up andreset sequence timing of the chip.Espressif Systems4Submit Documentation FeedbackESP32 Hardware Design Guidelines V3.0
2.2.2 ResetCHIP PU serves as the reset pin of ESP32. The input level (VIL nRST ) for resetting the chip should be low enoughand remain so for a period of time. More details can be found in Section Power Scheme in ESP32 Datasheet. Toavoid reboots caused by external interferences, the CHIP PU trace should be as short as possible and routedaway from the clock lines. A pull-up resistor and a ground capacitor are highly recommended.Notice:CHIP PU pin must not be left floating.2.3 Flash (compulsory) and PSRAM (optional)ESP32 can support up to four 16 MB external flash and 8 MB external SRAM. The demo module uses a 4 MBflash by default, in a SOP8 (208 mil) package. The VDD SDIO acts as the power supply pin. Make sure to selectGPIO21499R(1%)the appropriateflash according to the power voltage on VDD SDIO.U0TXDU0RXDGPIO22On PSRAM,all pins except for the CS pin, can be multiplexed with flash.The schematic for ESP32 flash and PSRAM is shown in Figure IO17R170R(5%) FLASH CLKR160R(5%) SRAM CLKVDD SDIOVDD SDIOGPIO16VDD SDIOSHD/SD278/CSCLK/HOLDFLASHDIDOGNDFLASH CLK SDO/SD0SWP/SD341VCCU3SCS/CMDCS#VDDSO/SIO1 SIO3SIO2SCLKVSSSI/SIO08765SHD/SD2SRAM CLKSDI/SD1PSRAM 0%)Figure 4: ESP32 Flash and PSRAMND2.4 Crystal OscillatorSCK/CLKR120R(5%) FLASH CLKThere are two clock sources for the ESP32, that is, an external crystal oscillator clock source and an RTC clocksource.R110R(5%)(NC)GPIO17R13Espressif Systems0R(5%) SRAM CLK5Submit Documentation FeedbackESP32 Hardware Design Guidelines V3.0
C20The capacitance of C1 and C2 varieswith the selection of the D1234SENSOR VP 5F(NC)67F(NC) SENSOR VN8CHIP 1 External Clock Source (compulsory)GNDVDDALNA INVDD3P3VDD3P3SENSOR VPSENSOR CAPPSENSOR CAPNSENSOR VNCHIP PUVDET 1VDET 232K XP32K XNGPIO25C5Currently, the ESP32 Wi-Fi/BT firmware only supports 40 MHz crystal oscillator. In circuit design, capacitors C1 andC2 which connect to the ground are added to the input and output terminals of the crystal oscillator respectively.49R1C63.3nF/6.3V(10%)GNDThe specific capacitive valuesdepend on further testing of, and adjustment to, the overall performance of the wholecircuit. It is recommended that users reserve a series resistor of 0 Ω on the XTAL P clock trace to reduce the drive20K(5%)strength of the crystal, as well as to minimize the impact of crystal harmonics on RF performance. Note that theaccuracy of the selected crystal is 10 ppm. The schematic for crystal oscillator is shown in Figure 5.GNDGNDXINGND1C1TBDR2GND0R 40MHz L PXTAL 3P3 CPUGPIO23GPIO18GPIO5SD DATA 1SD DATA 0SD CLKSD CMDSD DATA 3SD DATA 2GPIO17VDD SDIOGPIO16GND XOUT3837363534333231302928272625Figure 5: ESP32 Crystal SWP/SD3SHD/SD2GPIO17(about 10 pF). XTAL N can be floating. Please make sure that the oscillator output is stable and its accuracy isVDD33GPIO16 If an oscillator is used, its output should be connected to XTAL P on the chip through a DC blocking capacitorwithin 10 ppm. The amplitude into XTAL P can not exceed 1.1 V. It is also recommended that the circuit designfor the oscillator is compatible with the use of crystal, in case that if there is a defect in the circuit design, users canSCS/CMDSCK/CLKSHD/SD2still use the crystal. Defects in the craftsmanship of the crystal oscillators (for example, frequency deviation more than 10 ppm) andunstable operating temperature may lead to the malfunction of ESP32, resulting in a decrease of the overall performance.1672.4.2 RTC(optional)8GNDVCCESP32 supports an external 32.768 kHz crystal or an external 32.768 kHz signal (e.g., an oscillator) to act as theDIDO/WPFLASHVDD SDIO/CSCLK/HOLDU34RTC sleep clock.5SDO/SD0SDI/SD1SWP/SD323Figure 6 shows the schematic for the external 32.768 kHz crystal.J1CON1J4CON1J711ESP32 Hardware Design Guidelines V3.0VD1ESD3.3CHIP PUSENSOR VP11SENSOR VNGPIO34GPIO35GPIO32GPIO33GPIO251111116Submit Documentation CON1J28CON1Espressif Systems
0R(5%)PCB ANTL42.0nH( 0.1nH)C15C142.4pF 0.25pF3.3pF 0.25pFGNDGND234SENSOR VP 567SENSOR VN 8CHIP BD1GNDLNA INVDD3P3VDD3P3SENSOR VPSENSOR CAPPSENSOR CAPNSENSOR VNCHIP PUVDET 1VDET 232K XP32K D3P3 2VDD3P3 CPUGPIO23GPIO18GPIO5SD DATA 1SD DATA 0SD CLKSD CMDSD DATA 3SD DATA 2GPIO17VDD 4Figure 6: Schematic for ESP32’s External Crystal (RTC)GPIO26GPIO27GPIO14GPIO12TBDC18Notice: Please note the requirements for the 32.768 kHz crystal.– Equivalent series resistance (ESR) 70 kΩ.– Load capacitance at both ends should be configured according to the crystal’s specification. The parallel resistor R4 is used for biasing the crystal circuit (5 MΩ R4 10 MΩ). When ESP32-D0WD-V3 connects to an external 32.768 kHz crystal, the parallel resistor must be populated. Forother ESP32 series chips, the resistor can be reserved. If the RTC source is not required, then pin12 (32K XP) and pin13 (32K XN) can be used as GPIOs.Figure 7 shows the schematic of the external signal.32 768 kHz signal32K XNESP3232K XPC1Figure 7: Schematic of External OscillatorThe value of C1 should be larger than 200 pF. The signal should meet the following requirements:32K XN inputAmplitude (Vpp, unit: V)Sine wave or square wave0.6 Vpp VDD2.5 5 RF4The output impedance of the RF pins of ESP32 (QFN 6*6) and ESP32 (QFN 5*5) are (30 j10) Ω and (35 j10) Ω,respectively. A π-type matching network is essential for antenna matching in the circuit design. CLC structure isrecommended for the matching network. The schematic for ESP32 RF circuitry is shown in Figure 8.Espressif Systems373635343332313029282726257Submit Documentation FeedbackESP32 Hardware Design Guidelines V3.0G
ANT112PCB ANT1234C15C14C16SENSOR VP 5TBDTBD270pF(NC)67270pF(NC) SENSOR VN8GND GNDGNDCHIP PU9C1710GPIO3411Figure 8: ESP32 RF MatchingGPIO35Schematics12GPIO32L4TBDVDDALNA INVDD3P3VDD3P3SENSOR VPSENSOR CAPPSENSOR CAPNSENSOR VNCHIP PUVDET 1VDET 2Note:The parameters of the components in the matching network are subject to the actual antenna and PCB layout.2.6 ADCIt is recommended that users add a 0.1 µF filter capacitor to a pad when using the ADC function. Pins SENSOR VP or SENSOR VN will trigger an input glitch lasting for 80 ns once SARADC1, or SARADC2,or Hall sensor is initialized. Pins SENSOR VP or SENSOR VN is recommended for use as ADC. If SENSOR VP and SENSOR VN are u
15 Nine-Grid Design for EPAD 14 16 ESP32 Power Traces in a Two-layer PCB Design 15 17 ESP32 Crystal Oscillator Layout 16 18 ESP32 RF Layout in a Four-layer PCB Design 17 19 ESP32 RF Layout in a Two-layer PCB Design 17 20 ESP32 Flash and PSRAM Layout 18 21 ESP32 UART Design 18 22 A Typical Touch Sensor Application 19 23 Electrode Pattern .
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6 Setup and Hold Times for the Strapping Pin 21 7 Address Mapping Structure 23 8 QFN48 (6x6 mm) Package 48 9 QFN48 (5x5 mm) Package 48 10 ESP32 Part Number 49 Espressif Systems 7 Submit Documentation Feedback ESP32 Series Datasheet v3.5
IT hardware, and only 17 percent actually inventory all IT hardware. On average, about 76 percent of an organiza-tion's IT hardware is inventoried. Any IT hardware that's not inventoried is either intentional (by design) or the result of poorly enforced policies. The scope of IT hardware encompasses a wide range
Guidelines Heuristics (rules that are generally true) –have been developed for various manufacturing technologies. Some DFM guidelines –Guidelines for machining –Guidelines for assembly –Guidelines for injection molding –Guidelines for sheet metal processing –Guidelines for sheet die forming –Guidelines for casting
3. Mounting Hardware: a. Use mounting hardware that came with the TV, or b. If the TV did not come with mounting hardware, select from included Bolts and Washers (see Parts List on page 7). WARNING! To prevent serious injury, do not use hardware that does not match the TV's hardware, that is too long or too short, or overtighten the hardware.
by software. Commodity hardware devices, such as Mel-lanox NICs and P4 Switches, support both putting a hardware counter to every ﬂow and sampling the hardware trafﬁc to software. The cost of using hardware counters for ﬂow rate measurement is very high (more discussion in Section2). If sampling a portion of the hardware trafﬁc to .
Hardware, of course, offers much greater speed than a software implementation, but one must consider the increase in development time inherent in creating a hardware design. Most software designers are familiar with C, but in order to develop a hardware system, one must either learn a hardware design language such
Jeffery was a good introduction to scoping. In appropriate order different bureaucratic levels were tackled, always sensitive to the pressures in each place. The many discussions with Roger proved useful during the field work later. For example, we confronted the problem of finding very large sample sites which were suitable on other parameters. So we discussed how this should be tackled .