MB86R12 Application Note DDR3 Interface PCB Design Guideline
MB86R12 Application NoteDDR3 InterfacePCB Design GuidelineNovember, 2011The 1.0 editionFUJITSU SEMICONDUCTOR CONFIDENTIAL
MB86R12 Application NoteDDR3 Interface PCB Design GuidelinePrefaceThis guideline describes PCB design restrictions related to MB86R12 DDR3 interface signal wiring.· The contents of this document are subject to change without notice.Customers are advised to consult with sales representatives before ordering.· The information, such as descriptions of function and application circuit examples, in this document arepresented solely for the purpose of reference to show examples of operations and uses of FUJITSUSEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does not warrant proper operation of the devicewith respect to use based on such information. When you develop equipment incorporating the device basedon such information, you must assume any responsibility arising out of such use of the information. FUJITSUSEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of theinformation.· Any information in this document, including descriptions of function and schematic diagrams, shall not beconstrued as license of the use or exercise of any intellectual property right, such as patent right or copyright,or any other right of FUJITSU SEMICONDUCTOR or any third party or does FUJITSUSEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other rightby using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of theintellectual property rights or other rights of third parties which would result from the use of informationcontained herein.· The products described in this document are designed, developed and manufactured as contemplated forgeneral use, including without limitation, ordinary industrial use, general office use, personal use, andhousehold use, but are not designed, developed and manufactured as contemplated (1) for use accompanyingfatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public,and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reactioncontrol in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical lifesupport system, missile launch control in weapon system), or (2) for use requiring extremely high reliability(i.e., submersible repeater and artificial satellite).Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for anyclaims or damages arising in connection with above-mentioned uses of the products.· Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage orloss from such failures by incorporating safety design measures into your facility and equipment such asredundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions.· Exportation/release of any products described in this document may require necessary procedures inaccordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or USexport control laws.· The company names and brand names herein are the trademarks or registered trademarks of their respectiveowners.All rights reserved, Copyright FUJITSU SEMICONDUCTOR LIMITED 2011FUJITSU SEMICONDUCTOR CONFIDENTIALi
MB86R12 Application NoteDDR3 Interface PCB Design GuidelineRevision HistoryDate2011/11/29Ver.1.0ContentsNewly issuedFUJITSU SEMICONDUCTOR CONFIDENTIALii
MB86R12 Application NoteDDR3 Interface PCB Design GuidelineContents1. Floor plan . 12. PCB laminating . 23. DDR3 SDRAM specifications . 34. Signal design restrictions (DDR3 interface part) . 44.1. Definition of signal line group . 44.2. General wiring restrictions . 54.3. Resistance. 54.4. Terminal resistance/Damping resistance/Wire length . 64.5. Wiring gap/Crosstalk. 74.6. ZQ/ODT setting . 84.7. Wiring topology . 94.7.1.Wiring topology diagram of MCK Group . 94.7.2.Wiring topology diagram of MDQSx Group. 104.7.3.Wiring topology diagram of MDQx Group .114.7.4.Wiring topology diagram of MCNTL Group/MCMD Group . 125. Power system design restrictions . 135.1.5.2.Number and capacity of bypass capacitor . 13Pull-out wiring condition . 14FUJITSU SEMICONDUCTOR CONFIDENTIALiii
MB86R12 Application NoteDDR3 Interface PCB Design Guideline1.Floor planFigure 1-1 shows the reference example of the floor plan of MB86R12 and connected DDR3 m15.5mm32mmFigure 1-1Reference example of the floor plan of MB86R12 and DDR3 SDRAM devicesFUJITSU SEMICONDUCTOR CONFIDENTIAL1
MB86R12 Application NoteDDR3 Interface PCB Design Guideline2.PCB laminatingThis chapter shows the recommended laminating conditions of the PCB.Insulator 100μm150μm150μm100μmResist thickness 40μmResist 35μm35μm43μmClassificationSIG. (copper foil: 18mm, plating: 25mm)PowerSIG.GNDPowerSIG.GNDSIG. (copper foil: 18mm, plating: 25mm)Insulation material: relative permittivity 4.3 (only the resist part is 3.9)Figure 2-1PCB laminatingSpecified condition of wiring layer L1 and L8 are used as wiring and pull-out wiring layer of CLK.L3 and L6 are used as wiring layer of DQS, DQ, and CMD/ADD.L2 and L5 are used as power layer.L4 and L7 are used as GND layer.FUJITSU SEMICONDUCTOR CONFIDENTIAL2
MB86R12 Application NoteDDR3 Interface PCB Design Guideline3.DDR3 SDRAM specificationsThis chapter shows DDR3 SDRAM that can be used for the DDR3 interface with MB86R12.If an alternative device fulfills the same requirements, it can also used.Please note however, that if you use an alternative device, there may be differences concerning I/O qualitywhich may require your attention. However, all I/O characteristics should be checked as could differ.Even if you use the device(s) listed below, you must refer to the specifications provided by the DRAMmanufacturer for the confirmation of details (e.g. operating temperature conditions etc.).Table 3-1Recommended DDR3 SDRAMManufacturerMicronTechnology, Inc.Product nameMT41J128M16HA-15E(2Gb 1333Mbps)FUJITSU SEMICONDUCTOR CONFIDENTIALIBIS model name Driver strengthRemarksv69a at.ibs34ΩIt has already been verified bythe transmission line analysis.3
MB86R12 Application NoteDDR3 Interface PCB Design Guideline4.Signal design restrictions (DDR3 interface part)This chapter describes the signal wiring design restrictions for the DDR3 interface part.4.1.Definition of signal line groupIn order to make the requirements for wiring configurations described further on in this document easier tounderstand, the DDR3 interface signals are classified into the groups listed below.Table 4-1DDR3 interface signal groupingWiringpreferentialGroup nameorder1MCK Group2Pin name of MB86R12MCK, MXCKMDQS0 GroupMDQS0, MXDQS0MDQS1 GroupMDQS1, MXDQS1MDQS2 GroupMDQS2, MXDQS2MDQS3 GroupMDQS3, MXDQS3MDQ0 GroupMDQ0 MDQ7, MDM0MDQ1 GroupMDQ8 MDQ15, MDM1MDQ2 GroupMDQ16 MDQ23, MDM2MDQ3 GroupMDQ24 MDQ31, MDM34MCNTL GroupMCKE, MXCS, MODT5MCMD GroupMA0 MA14, MBA0 MBA2, MXCAS, MXRAS, MXWE3FUJITSU SEMICONDUCTOR CONFIDENTIAL4
MB86R12 Application NoteDDR3 Interface PCB Design Guideline4.2.General wiring restrictionsThis section describes the general wiring restrictions. It is recommended that signal wiring be designed to have the following characteristic impedance.Single impedance: 50Ω 10%Differential impedance: 100Ω 10% Signal wiring on power layer and GND layer should be sufficient width to guarantee the flow ofreturn current. (Signal line should be wired on the same power group or GND group. It must not crossover other power and GND groups.) Please use parallel wiring for the positive and negative signals of the differential MCK Group andMDQSx Group signals. In addition, also take care that the position and number of layer vias is thesame. The following groups must wire the same layer respectively, and the number of layer transfer viasmust become the same, too.MDQS0 Group and MDQ0 GroupMDQS1 Group and MDQ1 GroupMDQS2 Group and MDQ2 GroupMDQS3 Group and MDQ3 GroupThere are no restrictions to the number of layer transfer vias for other signals, but use a minimumpossible. When using meander wiring layouts for signal delay, crosstalk may occur and the delay value reduced,therefore having wider spacing between wirings is recommended. The recommended wire spacing isabout five times the wiring width.Wire spacingBevelled corners used in order to reduce signal reflectionsFigure 4-1Meander wiringThe recommended conditions and the simulation waveform which are described further on in thisdocument are valid under the above conditions.If your design greatly differs from the above conditions, then please run a simulation on your wiring.4.3.Resistance Resistors described in this guideline should be generally selected from the E12 series.E12 series: 10, 12, 15, 18, 22, 27, 33, 39, 47, 56, 68, 82 The following resistance tolerance values should be used (according to the resistance type):Terminal resistance: under 5%Divider resistance for VREF: under 1%FUJITSU SEMICONDUCTOR CONFIDENTIAL5
MB86R12 Application NoteDDR3 Interface PCB Design Guideline4.4.Terminal resistance/Damping resistance/Wire lengthTable 4-2 shows the recommended resistance value and wire length for each group.The wiring topology diagram relevant to this section is shown in "4.7. Wiring topology".Table 4-2No.Resistance value and wire length listGroup nameExternal terminalresistance value(Rt)1MCK Group39Ω 20.1μF capacitor 1DampingWire length fromresistance value MB86R12 output to(Rd)SDRAM inputInternal group approvedwire length variationN/ARefer to "4.7.1."Meet the conditions of"4.7.1."(Refer to "4.7.1.")2MDQSx GroupN/AN/ARefer to "4.7.2."Meet the conditions of"4.7.2."3MDQx GroupN/AN/ARefer to "4.7.3."Meet the conditions of"4.7.3."4MCNTL Group39ΩN/ARefer to "4.7.4."Meet the conditions of"4.7.4."5MCMD Group39ΩN/ARefer to "4.7.4."Meet the conditions of"4.7.4."FUJITSU SEMICONDUCTOR CONFIDENTIAL6
MB86R12 Application NoteDDR3 Interface PCB Design Guideline4.5.Wiring gap/CrosstalkPlease keep to the wiring configurations shown below in order to avoid malfunctions and deterioratedsignal integrity due to crosstalk.(1) The recommended gap for wiring within MDQx Group and MCMD Group groups should be over300µm.Example:MDQ0Example:MDQ1MA0MA1Over 300μmFigure 4-2Over 300μmGap for wiring within MDQx Group and MCMD Group(2) The gap for wiring with other groups should be over 300µm.Example:MDQ0Example:MA0MDQ0Over 300μmFigure 4-3MDQ8Over 300μmGap for wiring of other signal groups(3) Differential wiring signals of MCK Group and MDQSx Group should use a wiring gap of over 500µmto other signals.If it is difficult to guarantee a gap above 500µm, separate the wire from other signals using a GND area.However, please take the consequent decrease of the wiring impedance into consideration.Example:Example:Other signalsMCKOver 500μmFigure 4-4MDQS0Other signalsOver 500μmGap for wiring between signal in MCK Group/MDQSx Group and other signalsFUJITSU SEMICONDUCTOR CONFIDENTIAL7
MB86R12 Application NoteDDR3 Interface PCB Design Guideline4.6.ZQ/ODT settingTable 4-3 shows the ZQ setting conditions.Table 4-3ZQ setting conditionsGroup nameOutput impedance of MB86R12 I/O (RON)MCK Group40ΩMDQSx Group48ΩMDQx Group48ΩMCNTL Group60ΩMCMD Group60ΩZQ setting of MB86R12Perform the ZQ calibration, and set itautomatically.Table 4-4 shows the recommended ODT setting conditions for MDQSx Group and MDQx Group signals.Table 4-4ODT setting conditionsOperating conditionMB86R12DDR3 SDRAMWrite to DDR3 SDRAMOff60ΩRead from DDR3 SDRAM40ΩOffFUJITSU SEMICONDUCTOR CONFIDENTIAL8
MB86R12 Application NoteDDR3 Interface PCB Design Guideline4.7.Wiring topologyThis section illustrates the recommended wiring topology of each group.4.7.1.Wiring topology diagram of MCK GroupDDR3MB86R12SDRAMFor DQ[15:0]L1 (24.8mm 25.3mm)RON: 40[Ω]L2(15.5mm 15.9mm)Wire length of each CLK signalSignal nameLength of wiring "L1 L2" [mm]MCK/MXCK 40.7 1 (Differential and equal-length)DDR3SDRAMFor DQ[31:16]- In wiring, the L1/L8 layer is assumption.3 9Ω- Wire length doesn't contain the length of the via.0.1μF39ΩNo limitVSSFigure 4-5Wiring topology diagram of MCK GroupFUJITSU SEMICONDUCTOR CONFIDENTIAL9
MB86R12 Application NoteDDR3 Interface PCB Design Guideline4.7.2.Wiring topology diagram of MDQSx GroupDDR3MB86R12SDRAML1RON: 48[Ω]ODT: 40[Ω]Wire length of each DQS signalSignal nameLength of wiring "L1" [mm]MDQS0/MXDQS030.9 3 (Differential and equal-length)MDQS1/MXDQS131.5 3 (Differential and equal-length)MDQS2/MXDQS230.5 3 (Differential and equal-length)MDQS3/MXDQS328.7 3 (Differential and equal-length)Driver strength: 34[Ω]ODT: 60[Ω]- In wiring, the L3/L6 layer is assumption.- Wire length doesn't contain the length of the via.Figure 4-6Wiring topology diagram of MDQSx GroupFUJITSU SEMICONDUCTOR CONFIDENTIAL10
MB86R12 Application NoteDDR3 Interface PCB Design Guideline4.7.3.Wiring topology diagram of MDQx GroupDDR3MB86R12SDRAML1RON: 48[Ω]Driver strength: 34[Ω]ODT: 40[Ω]ODT: 60[Ω]- In wiring, the L3/L6 layer is assumption.- Wire length doesn't contain the length of the via.Wire length of each DQ signalSignalLength of wiring "L1" [mm]SignalnameLength of wiring "L1" [mm]nameMDM0 Wire length of MDQS0 Group (Average value): 3.5 2MDM2 Wire length of MDQS2 Group (Average value): 5.1 2MDQ0 Wire length of MDQS0 Group (Average value): 2.9 2MDQ16 Wire length of MDQS2 Group (Average value): 2.0 2MDQ1 Wire length of MDQS0 Group (Average value): 2.8 2MDQ17 Wire length of MDQS2 Group (Average value): 0.9 2MDQ2 Wire length of MDQS0 Group (Average value): 2.2 2MDQ18 Wire length of MDQS2 Group (Average value): 4.5 2MDQ3 Wire length of MDQS0 Group (Average value): 1.1 2MDQ19 Wire length of MDQS2 Group (Average value): 2.7 2MDQ4 Wire length of MDQS0 Group (Average value): 2.7 2MDQ20 Wire length of MDQS2 Group (Average value): 4.1 2MDQ5 Wire length of MDQS0 Group (Average value): 5.0 2MDQ21 Wire length of MDQS2 Group (Average value): 4.8 2MDQ6 Wire length of MDQS0 Group (Average value): 3.6 2MDQ22 Wire length of MDQS2 Group (Average value): 3.3 2MDQ7 Wire length of MDQS0 Group (Average value): 1.1 2MDQ23 Wire length of MDQS2 Group (Average value): 2.5 2MDM1 Wire length of MDQS1 Group (Average value): 2.5 2MDM3 Wire length of MDQS3 Group (Average value): 4.7 2MDQ8 Wire length of MDQS1 Group (Average value): 4.4 2MDQ24 Wire length of MDQS3 Group (Average value): 3.2 2MDQ9 Wire length of MDQS1 Group (Average value): 3.1 2MDQ25 Wire length of MDQS3 Group (Average value): 1.3 2MDQ10 Wire length of MDQS1 Group (Average value): 1.4 2MDQ26 Wire length of MDQS3 Group (Average value): 5.9 2MDQ11 Wire length of MDQS1 Group (Average value): 3.3 2MDQ27 Wire length of MDQS3 Group (Average value): 3.4 2MDQ12 Wire length of MDQS1 Group (Average value): 2.2 2MDQ28 Wire length of MDQS3 Group (Average value): 6.6 2MDQ13 Wire length of MDQS1 Group (Average value): 2.9 2MDQ29 Wire length of MDQS3 Group (Average value): 3.9 2MDQ14 Wire length of MDQS1 Group (Average value): 4.2 2MDQ30 Wire length of MDQS3 Group (Average value): 5.0 2MDQ15 Wire length of MDQS1 Group (Average value): 2.1 2MDQ31 Wire length of MDQS3 Group (Average value): 6.4 2Note 1) The DQ signal can be shuffled in byte.Figure 4-7Wiring topology diagram of MDQx GroupFUJITSU SEMICONDUCTOR CONFIDENTIAL11
MB86R12 Application NoteDDR3 Interface PCB Design Guideline4.7.4.Wiring topology diagram of MCNTL Group/MCMD Group0.6mm or less DDR3MB86R12SDRAMFor DQ[15:0]L1 (31.0mm 44.7mm)RON: 60[Ω]L2(17.1mm 17.4mm)Wire length from MB86R12 toSDRAM at the farthest position0.6mm or less(48.7mm 62.7mm)DDR3SDRAMFor DQ[31:16]VTT DDRVDE/2L1/L8 layer- In wiring, the L3/L6 layer is assumption.- Wire length doesn't contain the length of the via.39ΩNo limitFigure 4-8Wiring topology diagram of MCNTL Group/MCMD GroupFUJITSU SEMICONDUCTOR CONFIDENTIAL12
MB86R12 Application NoteDDR3 Interface PCB Design Guideline5.Power system design restrictionsThis chapter describes the power system design restrictions for the DDR3 interface part of MB86R12.5.1.Number and capacity of bypass capacitorTable 5-1 shows recommended number of bypass capacitors for the high frequency noise removal forwhich mounting is necessary directly under MB86R12.Table 5-1Recommended number of bypass capacitorsRecommended number ofbypass capacitorsPin name ofMB86R12Power supplyvoltageDDRVDE1.5V0.1µF18VSS0V-RemarksFor DDR3 interface If capacity is a value close to 0.1µF (0.22µF etc. for instance), the bypass capacitor can be used. Place the 0.1µF capacitor as close as possible to the power/GND pins of MB86R12 (refer to "5.2.Pull-out wiring condition"). For the 0.1µF capacitor, we recommend the use of ceramic capacitors of under size 1005(1.0mm 0.5mm).In addition, use low ESL (Equivalent Series Inductance) value components where possible in order todecrease noise. Mount a high-capacity capacitor for the low frequency if needed. One 100µF is recommended to beused for the current variation of 1A only as a guide. Verify your board design by simulations and measurements if you can not mount capacitors of theabove number.FUJITSU SEMICONDUCTOR CONFIDENTIAL13
MB86R12 Application NoteDDR3 Interface PCB Design Guideline5.2.Pull-out wiring conditionThis section shows the example of mounting the bypass capacitor for the high frequency noise removal.Be sure to meet the following pull-out wiring conditions to reduce the inductance value by wiring and toreduce the noise. If it doesn't meet these conditions, widen the wire width as much as possible, and shortenthe wire length.Note 1) There is no problem even if the Chip on Via method without the pull-out wiring is used.PADGNDviaWire length (L)PADWire width(W)Pull-outwiringL1 Ln layer viaLn layer pull-out wiringPull-outwiringPowerviaPAD)(LGNDPAD Puw ll-oiri utngthngPowerPAD Puw ll-oiri utngleL1 layer pull-out wiringi reWL1L1 layer MB86R11MB86R12 PADPAD［Pull-out wiring conditions］Wire width (W): over 0.3mmWire length (L): under 0.71mm* Average value of all pull-outwiringPADBypass
MB86R12 Application Note DDR3 Interface PCB Design Guideline . 2. PCB laminating . This chapter shows the recommended laminating conditions of the PCB. Figure 2-1 PCB laminating . Specified condition of wiring layer L1 and L8 are used as wiring and pull-out wiring layer of CLK. L3 and L6 are used as wiring layer of DQS, DQ, and CMD/ADD.
Chassis Plans recommends ECC registered DDR3 memory modules for use on the JXT6966/JXTS6966 SHBs and these ECC registered (72-bit) DDR3 Mini-DIMMs must be PC3-10600 or PC3-8500 compliant. Unbuffered ECC DDR3 Mini-DIMMs are also supported on the JXT boards, but you cannot m
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- Supports Intel Turbo Boost 2.0 Technology - Supports K-Series unlocked CPU Chipset - Intel H61 - Supports Intel Rapid Start Technology and Smart Connect Technology Memory - Dual Channel DDR3 Memory Technology - 2 x DDR3 DIMM slots - Supports DDR3 1600/1333/1066 non-ECC, un-buffered memory (D
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The Xilinx UltraScale architecture DDR3, DDR4, and RLDRAM 3 memory interface cores provide solutions for interfacing with these SDRAM memory types. Both a complete Memory Controller and a physical (PHY) layer only solution are supported. The UltraScale architecture DDR3, DDR4,
21 TDR cable test interface (Optional) 22 SDI input (BNC interface) ( Optional) 23 RS485 Interface: RS485communication for the PTZ 24 HDMI IN 25 Video signal output（BNC interface）/ cable tracer interface 26 CVBS IN/AHD /TVI/CVI Coaxial interface /（BNC interface）(AHD /TVI/CVI) 27 Optical power meter interface (Optional)
Introduction A description logic (DL) knowledge base (KB) consists of a terminological box (TBox), storing conceptual knowledge, and an assertion box (ABox), storing data. Typical applica-tions of KBs involve answering queries over incomplete data sources (ABoxes) augmented by ontologies (TBoxes) that provide additional information about the domain of interest as well as a convenient .
