Gigabit Multimedia Serial Links (GMSL) For ADAS Design Guide

GMSL for ADAS Design Guidewww.maximintegrated.comPower Over CoaxAll of the current delivered across the cable must pass througheach inductor in the power filter, which places additionalconstraints on inductor parameter selection including:saturation current, DC winding resistance, and package size. If acurrent greater than ISAT flows through an inductor, its magneticfield saturates and the inductance drops steeply. There is apower loss proportional to the current through the inductorand its DCR, which causes self-heating to occur. If there is novoltage margin built into the power delivery rail, the voltagedrop across the power filter may cause insufficient voltagelevels at the load.In many systems, one STP cable actually has two pairs inside—one for power and one for data. Using coax cables instead of STPcables for SERDES links has advantages—they’re cheaper, lighter,more flexible, and less lossy at high frequencies. To make using alow-cost coax cable competitive, it must also provide both powerand data through a single cable. To achieve this, the availablefrequency spectrum on the inner conductor is divided into threebands—power, reverse-channel data, and forward-channel data(Figure 6). Filtering is used to pass the appropriate frequencyband to its corresponding circuit. The data channels are ACcoupled through a series capacitor to the transceiver inputs.DCAdaptive Equalizer0.05FORWARDCHANNELREVERSE CHANNELPOWER (OVER COAX)MAGNITUDEPOC FILTERTo avoid all three of these potential problems, a higher voltageis applied to the cable, which results in lower cable current.Additionally, inductors with sufficient size and saturation currentrating are chosen to handle the required cable current. TheMAX967xx product line features best-in-class power consumptionto ease the requirements in the power over coax circuit.1101500 FREQUENCY(MHz)Figure 6. Frequency Bands Used in Coax GMSL SystemsThe DC power typically uses the lowpass quality of seriesinductors to construct filters whose impedance rise above1kΩ in the reverse-channel and forward-channel frequencybands. Since the data channels operate with 50Ω termination,the 20x increase in impedance is sufficient to couple the DCvoltage and filter the high-frequency content. Since everyinductor has parasitic capacitance that causes self-resonanceand a corresponding drop in impedance at high frequencies,inductors of different sizes are chosen to filter out all thebands of interest (Figure 7).OUT J-OUT All cables have a parasitic impedance that degrades signalquality as frequencies increase. Longer cable lengths alsocontribute to signal degradation. Many high-speed transmissionsystems compensate for the lowpass nature of a transmissioncable by placing a cable equalizer at the front end of the receiverinput. Equalizers amplify high-frequency signals of interest suchthat, when combined with the frequency response of the cable,the receiver can recover broadband signals with higher fidelity.The MAX967xx deserializers have built-in adaptive equalizercircuitry. With 12 different compensation levels, the equalizerallows the SERDES system to handle up to 30m coax and 15mSTP cable lengths.The adaptive equalizer can be programmed to readaptperiodically, or it can be triggered manually to compensatefor any changes in the transmission environment. As cablesare worn over time and replaced, the system can adapt itselffor optimal operation by automatically setting the adaptiveequalizer level (Figure 8).R302kΩR312kΩ04020402 7V TO 12VL2L3MPZ160847µHADL3225V-470M-TL000Figure 7. Power Over Coax Schematicwww.maximintegrated.com/ADAS7

GMSL for ADAS Design Guidewww.maximintegrated.com8b/10b EncodingUnderstanding 8b/10b encoding is an important prerequisitebefore determining parameters like pixel clock rate and data buswidth in a camera application. Maxim GMSL technology utilizesencoding schemes to enhance the quality of its serial links.8b/10b encoding uses an algorithm to encode data for atransmission line in which each 8-bit data byte is converted intoa 10-bit symbol. An 8b/10b encoded data stream has an equalnumber of 1s and 0s, and limits the number of consecutive 1s or0s to 5 bits (Table 2).Table 2. 8b/10b Encoding Format ExamplesFigure 8. Eye Diagram at GMSL Receiver with Varying SettingsValue (Decimal)Value (Binary)10-Bit CodeAlternate CodeHGF EDCBAabcdei fghjabcdei fghj0000 000001000111 0100011000 1011Eye-Width Monitor1000 00001011011 0100100010 1011Another feature for increasing the robustness of high-speedcommunication over a long cable is the addition of eye-widthmonitoring circuitry. By sending a pseudo-random bit sequence(PRBS) across a transmission line and plotting the transitions,a persistent plot is generated that represents an eye. With astable clock and compensated cable, the transitions in an eyediagram are narrow, resulting in an ‘open’ eye. As cable qualitydecreases or cable length increases, the high-frequency contentof each transition is attenuated and the eye starts to close.2000 00010101101 0100010010 10113000 00011110001 1011110001 01004000 00100110101 0100001010 10115000 00101101001 1011101001 01006000 00110011001 1011011001 01007000 00111111000 1011000111 01008000 010001110001 0100000110 1011The MAX96706 includes an eye-width monitor that senses theeye-width opening. If it senses the eye width decreasing below athreshold, it raises a flag on the ERRB output pin or even triggers are-tuning of the adaptive cable equalizer (Figure 9). By constantlymeasuring the eye width and adjusting the system settings whenperformance drops, the optional eye-width monitor circuitryprovides an additional level of reliability to the SERDES link.Figure 9. Contrast Between Closed (left) and Open (right) Eye Diagrams89000 01001100101 1011100101 010010000 01010010101 1011010101 0100""""If a transmission line is not DC-balanced, a voltage canaccumulate over time on the line, which leads to bit errors. Forexample, when consecutive 1s are transmitted, the AC-couplingcapacitors in a SERDES link develop a DC voltage that appearsincorrectly as a ‘0’ at the receiver. 8b/10b encoding tracks therunning disparity (RD) of 1s and 0s and ensures that the nextgenerated symbol keeps the running disparity within 1. Over along period, the number of 1s and 0s transmitted is split 50-50.Since the transmission clock is embedded in a SERDES datastream, it must be extracted from the data at the receiver. To dothis, the receiver monitors the transitions that occur in the data.Long patterns of 1s or 0s disrupt the ability of the receiver torecover the clock signal. 8b/10b encoding avoids this by limitingthe number of consecutive 1s or 0s.www.maximintegrated.com/ADAS

GMSL for ADAS Design Guidewww.maximintegrated.comCalculating the Pixel Clock RateSelecting Input Data WidthAn image sensor typically outputs information from one pixelfor every pixel clock cycle. Thus, the pixel clock for a givencamera application is calculated from the image size andnumber of images displayed every second:The high flexibility of the MAX967xx SERDES parts allow for avariety of configurations in setting the parallel data width. Thecalculated pixel clock rate limits the available settings for BWS, DBL,and HIBW. Other settings limit the parallel input mappings available:PXL CRC, HVEN, and the number of input/output pins (Table 4).Pixel rows x Pixel columns x frame rate Pixel Clock (Hz)When communicating from serializer to deserializer, MaximGMSL devices internally use data widths of 24, 27, or 32 bits.The use of 8b/10b (and 9b/10b) encoding translates these datawidths into 30- or 40-bit packets that are sent across the link.This packet encoding happens automatically and internally,but the user should keep this packet structure in mind whendeciding how to choose a pixel clock rate and allocate theparallel data to be sent across the link.The MAX967xx product family features a maximum serial datarate of 1.74Gbps. Since data is sent in 30- or 40-bit packets,this translates to a maximum packet update rate of 58MHzor 43.5MHz, respectively. Three hardware configuration pinsset the allowable pixel clock range that can be applied to aMAX967xx serializer: BWS, DBL, and HIBW (Table 3).Table 3. PCLK Range for Various Packet SettingsDBLBWSHIBWTable 4. MAX967xx Input Data Width SelectionRegister Bit SettingsDBLBWSHIBWInput Mapping(with MAX96706)Input MappingHVEN(with Other)11—11DIN11:0, HS, VSDIN11:0, HS, VS11—10DIN11:0,DIN11:0,11—01DIN11:0*, HS, VSDIN13:0*, HS, VS11—00DIN13:0*DIN14:0*1011—DIN8.0, HS, VSDIN8.0, HS, VS1010—DIN11:0, HS, VSDIN11:0, HS, VS10011DIN7:0, HS, VSDIN7:0, HS, VS10010DIN7:0DIN7:010001DIN10:0, HS, VSDIN10:0, HS, VS10000DIN10:0DIN10:001—11DIN11:0*, HS, VSDIN13:0*, HS, VS01—10DIN13:0*DIN15:0*PCLK Range (MHz)01—01DIN11:0*, HS, VSDIN13:0*, HS, VS01—00DIN13:0*DIN15:0*11025 to 8710033.3 to 11610173.3 to 11601012.5 to 43.5000000016.7 to 5800000136.6 to 58BWS determines the internal bus width, which is 32 bits whenBWS 1 or 24/27 bits when BWS 0. BWS is directly relatedto whether encoded serial packets are 30 or 40 bits wide, whichimposes a maximum clock range of 58MHz or 43.5MHz.DBL controls whether the serializer has single-input modeor double-input mode enabled. Single-input mode serializesone parallel input word into one serial word for transmission,whereas double-input mode combines two parallel input wordsof half-width into one serial word for transmission. Double-inputmode allows for twice the pixel clock to be used, at the expenseof the parallel input width.HIBW enables high-bandwidth mode, and is only active whenBWS 0. HIBW 1 selects a 27-bit wide internal data bus, andHIBW 0 selects a 24-bit wide internal data bus.www.maximintegrated.com/ADASPXL CRC001——DIN11:0*, HS, VSDIN13:0*, HS, VS00011DIN11:0*, HS, VSDIN13:0*, HS, VS010DIN13:0*DIN15:0*001DIN11:0*, HS, VSDIN13:0*, HS, VS00DIN13:0*DIN15:0** The input bit width is limited by the number of available serializer inputs and deserializer outputs.PXL CRC enables additional error checking on each serialpacket sent across the link. If enabled, this feature takes anadditional 6 bits of internal bus width.HVEN enables the HSYNC and VSYNC inputs to be encodedand sent in separate transmissions from the internal databus, which frees additional slots for parallel input data. Thisfeature is useful when there are more input data pins than slotsavailable in the internal data bus. If disabled, any HSYNC/VSYNC signal must be applied to an input slot.I/O Pin Count can be a limiting factor to the input data width.If single-input mode is enabled, or if the pixel CRC feature isdisabled, there may be many internal data bus slots available.If there are more bits available than parallel inputs or paralleloutputs, these slots in the packet go unused and bandwidth is lost.9

GMSL for ADAS Design Guidewww.maximintegrated.com32-BIT

object detection relies on the images it needs to process. Hence, high-quality images are absolutely essential. ADAS Overview Road safety has vastly increased due to continued developments in the automotive space known as ADAS. Some technologies take effect autonomously, operating the vehicle with complete control during given events (Table 1). Other technologies provide information to those .