04 ARM Architecture Overview - Web.eecs.umich.edu

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ARM ArchitectureOverview1Development of the ARM Architecture§Processor Architecture Instruction Set Programmer’s model4TARM7TDMIARM922TThumbinstruction set5TE6ARM926EJ- SARM946E-SARM966E-SARM1136JF -SARM1176JZF-SARM11 MPCoreImprovedARM/ThumbInterworkingSIMD InstructionsDSP instructionsExtensions:Jazelle (5TEJ)Unaligned data supportExtensions:Thumb-2 (6T2)7Cortex-A8/R4/M3/M1Thumb-2Extensions:v7A (applications) – NEONv7R (real time) – HW DivideV7M (microcontroller) – HWDivide and Thumb-2 onlyTrustZone (6Z)Multicore (6K)§Note: Implementations of the same architecture can be very different§§ARM7TDMI - architecture v4T. Von Neuman core with 3 stage pipelineARM920T - architecture v4T. Harvard core with 5 stage pipeline and MMU2Confidential1

ARM Architecture profiles§Application profile (ARMv7-A à e.g. Cortex-A8)§§§§§Memory management support (MMU)Highest performance at low power§ Influenced by multi-tasking OS system requirementsTrustZone and Jazelle-RCT for a safe, extensible systemReal-time profile (ARMv7-R à e.g. Cortex-R4)§§§Protected memory (MPU)Low latency and predictability ‘real-time’ needsEvolutionary path for traditional embedded businessMicrocontroller profile (ARMv7-M à e.g. Cortex-M3)§§§Lowest gate count entry pointDeterministic and predictable behavior a key priorityDeeply embedded use3Programmer’s Model4Confidential2

Data Sizes and Instruction Sets§When used in relation to the ARM:§§§§Doubleword means 64 bits (eight bytes)32-bit ARM Instruction Set16-bit Thumb Instruction SetLatest ARM cores introduce a new instruction set Thumb-2§§§Word means 32 bits (four bytes)Most ARMs implement two instruction sets§§§Halfword means 16 bits (two bytes)Provides a mixture of 32-bit and 16-bit instructionsMaintains code density with increased flexibilityJazelle-DBX cores can also execute Java bytecode5Processor Modes§The ARM has seven basic operating modes:Exception modes§§Each mode has access to own stack and a different subset of registersSome operations can only be carried out in a privileged modeModeDescriptionSupervisorEntered on reset and when a Software Interruptinstruction (SWI) is executed(SVC)FIQEntered when a high priority (fast) interrupt israisedIRQEntered when a low priority (normal) interruptis raisedAbortUsed to handle memory access violationsUndefUsed to handle undefined instructionsSystemPrivileged mode using the same registers asUser modeUserMode under which most Applications / OStasks runPrivilegedmodesUnprivilegedmode6Confidential3

The ARM Register SetUser modeIRQr0r1r2r3r4r5r6r7r8r9r10r11r12r13 (sp)r14 (lr)r15 (pc)FIQUndefAbortSVCARM has 37 registers, all 32-bits longA subset of these registers is accessiblein each moder13 (sp)r14 (lr)r8r9r10r11r12r13 (sp)r14 (lr)r13 (sp)r14 (lr)r13 (sp)r14 (lr)r13 (sp)r14 (lr)spsrspsrspsrspsrspsrcpsrCurrent modeBanked out registers7Program Status Registers3128 27N Z C V Q de2423Jf19Un16 15dGE[3:0]e fs§§98E A7§ N Negative result from ALU§ Z Zero result from ALU§ C ALU operation Carried out§ V ALU operation oVerflowedSticky Overflow flag - Q flag§ Architecture 5TE and later only§ Indicates if saturation has occurredJ bit§ Architecture 5TEJ and later only§ J 1: Processor in Jazelle stateInterrupt Disable bits§ I 1: Disables IRQ§ F 1: Disables FIQ6540I F Tx§ Condition code flags§10IT cond abcin e dmodec§ T Bit§§§ T 0: Processor in ARM state§ T 1: Processor in Thumb state§ Introduced in Architecture 4TMode bits§ Specify the processor modeNew bits in V6§GE[3:0] used by some SIMDinstructions§§§E bit controls load/store endiannessA bit disables imprecise data abortsIT [abcde] IF THEN conditionalexecution of Thumb2 instructiongroups8Confidential4

Data alignment§Prior to architecture v6 data accesses must be appropriately aligned foraccess size§Unaligned addresses will produce unexpected/undefined resultsByte access(byte aligned)§Halfword access(halfword aligned)Word access(word aligned)32102007654644ba98a88fedceccUnaligned data can be accessed using multiple aligned accessescombined with shift/mask operations9Exception Handling§When an exception occurs, the core:§§§§§Copies CPSR into SPSR mode Sets appropriate CPSR bits§ Change to ARM state§ Change to exception mode§ Disable interrupts (if appropriate)Stores the return address in LR mode Sets PC to vector addressTo return, exception handler needs to:§§FIQIRQ(Reserved)Data AbortPrefetch Abort0x1C0x180x140x100x0C0x08Software Interrupt0x04Undefined Instruction0x00ResetRestore CPSR from SPSR mode Restore PC from LR mode Vector TableVector table can also be at0xFFFF0000 on most cores§Must be done in ARM state in most cores, but.Thumb-2 capable cores can do this in Thumb state10Confidential5

Introduction toInstruction Sets11ARM Instruction Set§§§All instructions are 32 bits long / many execute in a single cycleInstructions are conditionally executedA load / store architecture§Example data processing instructionsSUBr0,r1,#5ADDr2,r3,r3,LSL #2ADDEQ r5,r5,r6§Example branching instructionB Label §Example memory access instructionsLDRr0,[r1]STRNEB r2,[r3,r4]STMFD sp!,{r4-r8,lr}r0 r1 - 5r2 r3 (r3 * 4)IF EQ condition true r5 r5 r6Branch forwards or backwards relative tocurrent PC ( /- 32MB range)Load word at address r1 into r0IF NE condition true, store bottom byteof r2 to address r3 r4Store registers r4 to r8 and lr onstack. Then update stack pointer12Confidential6

Thumb Instruction Set§Thumb is a 16-bit instruction set§§§§Optimized for code density from C code ( 65% of ARM code size)Improved performance from narrow memorySubset of the functionality of the ARM instruction setThumb is not a “regular” instruction set!§§Constraints are not generally consistentTargeted at compiler generation, not hand coding13Thumb-2 Instruction Set§Thumb-2 is a major extension to the Thumb ISA§§§Adds 32-bit instructions to implement almost all of the ARM ISA functionalityRetains the complete 16-bit Thumb instruction setDesign objective: ARM performance with Thumb code density§§No switching between ARM-Thumb statesCompiler automatically selects mix of 16 and 32 bit instructions14Confidential7

Thumb 2 Performance / Density100% ARM codePerformanceThumb-2Random mix‘Profiled’ mix100% Thumb codeCode density15Processor Cores16Confidential8

ARM7TDMI Processor§§§Architecture v4T3-stage pipelineSingle interface to memory17ARM926EJ-S ProcessorARM926EJ-S§§§§§§§Architecture v5TE5-stage pipelineSingle-cycle 32x16 multiplierCaches and TCMsMemory management unit (MMU)2 AHB memory interfacesJazelle technology18Confidential9

ARM1176JZ(F)-S Processor Core§§§§§§TrustZone8-stage pipelineBranch predictionFour AXI memory portsIEM (Intelligent EnergyManagement)Integrated VFP coprocessor19ARM11 MPCore ProcessorMP11MP11MP11MP11§ 1 – 4 MP11 processors§ Cache coherency§ Distributed interrupt controller20Confidential10

ARM Cortex-M3 Processor§Architecture v7-M (Thumb-2 only) àVery different from previous ARMprocessors§ No CPSR register§ Vector table contains addresses, notinstructions§ Processor automatically saves/restoresstate in exceptions§ Only 2 processor modes (Thread/Handler)§ No Coprocessor 15 3-stage pipeline withstatic branch prediction§Atypical Implementation§ Fixed memory map§ Integrated interrupt controller§ Serial-Wire Debug21ARM Cortex-A8 Processor§ Architecture v7-A§ 14 stage pipeline§ NEON media processor22Confidential11

The Instruction Pipeline23The Instruction Pipeline§The ARM7TDMI uses a 3-stage pipeline in order to increase thespeed of the flow of instructions to the processor§§Allows several operations to be performed simultaneously, rather thanseriallyARMThumbPCPCPC - 4PC-2PC - 8PC - 4FETCHDECODEEXECUTEInstruction fetched from memoryDecoding of registers used in instructionRegister(s) read from Register BankShift and ALU operationWrite register(s) back to Register BankThe PC points to the instruction being fetched, not executed§§Debug tools will hide this from youThis is now part of the ARM Architecture and applies to all processors24Confidential12

Optimal DEFDEFDORRANDORREORF - Fetch§§§D - DecodeEWE - ExecuteAll operations here are on registers (single cycle execution)In this example it takes 6 clock cycles to execute 6 instructionsClock cycles per Instruction (CPI) 125Branch Pipeline ExampleCycle1AddressOperation0x8000BL RF - Fetch§§FDEFD2356789EL EAFMFD - Decode4DEFDEFDE – Execute L – LinkretEWA - AdjustBreaking the pipelineNote that the core is executing in ARM state26Confidential13

Cortex-A8 Integer PipelineBranch Mispredict PenaltyReplay ECDECScore RegfileboardQueue & Issue RemapLogicPred.Instruction MUL2ADDWBMULPIPE0ShiftALUSATBPUpdateWBRAM FormatBPTLBFwd LUPIPE1Instruction DecodeAGULOADSTOREInstruction Execute / Load Store§§Optimising code to make use of the processor pipeline is very difficultLeave it to the compiler!!27Reference Slides28Confidential14

Reference Material§ARM ARM (“Architecture Reference Manual”)§ ARM DDI 0100E covers v5TE DSP extensions§ Can be purchased from booksellers - ISBN 0-201-737191 (Addison-Wesley)§ Available for download from ARM’s website§ ARM v7-M ARM available for download from ARM’s website§ Contact ARM if you need a different version (v6, v7-AR, etc.)§Steve Furber “ARM system-on-chip architecture” - 2nd edition§ ISBN 0-201-67519-6 (Addison-Wesley)§Sloss, Symes & Wright – “ARM System Developer's Guide”§ ISBN: 1-55860-874-5 (Morgan Kaufman)§RVCT Assembler Guide§ Available for download from ARM’s website§Technical Reference Manuals for processor core being used§ Available for download from ARM’s website29Naming Conventions§ARMx1z (e.g. ARM710T) indicates cache & full MMU§ARMx2z (e.g. ARM720T) indicates cache, MMU & Process ID support§ARMx3z (e.g. ARM1136J-S) indicates physically mapped caches and MMU§ARMx4z (e.g. ARM740T) indicates cache and MPU§ARMx5z (e.g. ARM1156T2-S) indicates cache, MPU and error correcting memory§ARMx6z (e.g. ARM966E-S) indicates write buffer but no caches§ARMx7z (e.g. ARM1176JZ-S) indicates AXI bus, & physically mapped caches andMMU§ARMxy6 (e.g. ARM946E-S) indicates TCMs30Confidential15

Which architecture is my processor?§§§Processor coreArchitectureARM7TDMI familyv4T§ARM720T, ARM740TARM9TDMI family§ARM9E family§ARM10E family§ARM11 family§v5TE, v5TEJARM946E-S, ARM966E-S, ARM926EJ -S§§v4TARM920T,ARM922T,ARM940Tv5TE, v5TEJ§ ARM1020E, ARM1022E, ARM1026EJ )-SARM11 MPCorev6v6T2v6Zv6Cortex family§§§§ARM Cortex -A8ARM Cortex -R4(F)ARM Cortex -M3ARM Cortex -M1v7-Av7-Rv7-Mv6-MFor ARM processor naming conventions and features, please see the Appendix31ARMv4T Cores:Architecture7TDMI720T740T920T940TSA1100von Neumannvon Neumannvon NeumannHarvardHarvardHarvard4K Instr 4KData4 words/line16K Instr 16K Data4 words/lineCacheNone8K Unified4 words/line8K Unified4 words/line16K Instr 16K Data8 words/lineAssociativityN/A4-way4-way64- way64- way32- wayTCMNoNoNoNoNoNoRandomRound RobinReplacementN/ARandomRandomRandomRound RobinWriteStrategyN/AWrite ThroughWrite ThroughWrite ThroughWrite BackWrite ThroughWrite BackWrite BackWrite BufferNone8 Words4 Addresses8 Words4 Addresses16 Words4 Addresses8 Words4 Addresses8 Words4 AddressesMMU/MPUNoneMMUMPUMMUMPUMMUHi StandbyModeNoNoNoYesYesYes32Confidential16

ARMv5 -1024K Instr0-1024K Data8 words/lineNoneNoneCache4-128K Instr4-128K Data8 words/line0-128K Instr0-128K Data8 words/line32K Instr32K Data8 words/lineAssociativity4-way4-wayN/AN/A4-way32- wayTCM0-1024K Instr0-1024K Data0-1024K Instr0-1024K Data0-64M Instr0-64M Data0-64M Instr0-64M Data0-1024K Instr0-1024K DataNoReplacementRandomRound RobinRandomRound RobinN/AN/ARandomRound RobinRandomRound RobinWriteStrategyWrite ThroughWrite BackWrite ThroughWrite BackN/AWrite ThroughWrite BackWrite ThroughWrite BackWrite ThroughWrite BackWrite Buffer16 Words4 Addresses16 WordsData orAddress12 WordsData orAddress12 WordsData orAddress8 WordsData orAddress8 x 16 BytesCoalescingMMU/MPUMMUMPUNoneNoneMMU or MPUMMUWithextensionsHi esStandbyModeYesYesYesYesYesYes33ARMv6 ectureHarvardHarvardHarvardHarvardCache4-64K Instr4-64K Data8 words/line0-64K Instr0-64K Data8 words/line4-64K Instr4-64K Data8 words/line16-64K Instr16-64K Data8 K Instr0-64K Data0-256K Instr0-256K Data0-64K Instr0-64K DataNoneReplacementRandomRound RobinRandomRound RobinRandomRound RobinRandomRound RobinWriteStrategyWrite ThroughWrite BackWrite ThroughWrite BackWrite ThroughWrite BackWrite ThroughWrite BackMMU/MPUMMUMPUMMUMMUHi eYesYesYesYesBusAHB/APBAXIAXIAXIVFP SupportYesYesYesYes34Confidential17

Cortex arvardHarvardHarvardNoneNone4-64K Instr4-64K Data8 words/line16 or 32 Instr16 or 32 Data16 words/lineN/AN/A4-way4-wayTCMNone0-1M Instr0-1M Data0-8M Instr0-8M N/AN/AWrite ThroughWrite BackWrite ThroughWrite BackMMU/MPUMPUNoneMPU(optional)MMUHi esYesYesYesBusAHB Lite/APBAHB Lite/APBAXIAXIVFP rustZone Computing§TrustZone adds a “parallel world” to allow trusted programs and data tobe safely separated from the OS and applications§Introduced for ARM1176, standard for ARMv7-A Cores§Features:§ New Secure Monitor Mode:§§§gate -keeper for secure stateNew S-bit in CP15 to indicate whenthe processor is running in asecured stateSecurity state exposed on externalbus accesses to permit securityaware memory and peripheralsAbility to restrict debug to nonsecure state36Confidential18

NEON Media Processor Features§Single Instruction Multiple Data (SIMD) Media Processor§Targets audio and video codecs, image and speechprocessing, graphics, baseband processing, and generalsignal processing§3 Processing pipelines: Integer/fixed point, single precisionfloating point, IEEE vector floating point§Efficient data handling§§§§Best use of available memory bandwidthEliminates data arrangement overheadOperates on separate register fileSIMD Framework excellent target for compilers37End38Confidential19

Reference Material §ARM ARM(“Architecture Reference Manual ”) §ARM DDI 0100E covers v5TE DSP extensions §Can be purchased from booksellers - ISBN 0-201-737191 (Addison-Wesley) §Available for download from ARM’swebsite §ARM v7-M ARM available for download from ARM’swebsite §Conta

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