Vivado Hello World Tutorial

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esignSeptember9,2013VIVADOTUTORIAL1

TableofContentsRequirements.3Part1:BuildingaZynq- nq- .272VIVADOTUTORIAL

stutorial: Vivadow/XilinxSDK(tested,version2013.2) Zedboard(tested,versionD)Part1:BuildingaZynq- etutorialyoucreateaZynq- oject1. e1:GettingStartedPageVIVADOTUTORIAL3

2. heNewProjectwizardopens(FIGURE2).3. ClickNextFigure2:CreateNewProjectWizard4. ,andthenclickNext.5. ckNext.6. geissettoVHDL,thenclickNext.7. IntheAddExistingIPdialogbox,clickNext.8. IntheAddConstraintsdialogbox,clickNext.9. rtedintheVivadoIDE.ClickNext.10. TUTORIAL

Step 2: Create an IP Integrator DesignStep 2: Create an IP Integrator DesignStep2:CreateananIPIPIntegratorDesign DesignStep ckDesign.Step1.2:InCreatean IP Integrator Design1. In the Flow Navigator, select Create Block Design.1. In the Flow Navigator, select Create Block igure3: Create Block Design from Flow NavigatorFigure 3: Create Block Design from Flow Navigator2. menu,sforpecifynameforyourIP2. In the CreateBlocka nameyouraIPsubsystemdesign.subsystemesign.popup menu, specify a name for your IP subsystem design.2. In the CreateBlockdDesignFigure 4:Create Block Design Dialog BoxFigure4:CreateBlockDesignDialogBoxFigure 4: Create Block Design Dialog BoxEmbedded Processor Hardware DesignUG940Embedded(v 2013.2)June 19, 2013ProcessorHardware DesignUG940 (v 2013.2) June 19, 2013www.xilinx.comwww.xilinx.comVIVADOTUTORIAL13 513

Step 2: Create an IP Integrator DesignStep 2: Create an IP Integrator Design3. Right-clickRight-clickin thethe VivadoVivadoIPVintegratorintegratordiagram window,window,andselect AddAdd3. Right- OptionFigure 5:5: AddAdd IPIP OptionOptionFigure4. heIPdiagramintegratordiagramarea.4. Alternatively,Alternatively,you cancan clickclicklinkin thetheintegratorarea.4.youthe AddIP linkinIP integratordiagram area.Figure6:AddIPLinkinIPIntegratorCanvasFigure 6:6: AddAdd IPIP LinkLink inin IPIP IntegratorIntegrator CanvasCanvasFigureTheIPCatalogopens.The IPIP Catalogopens.The5. qtofindthe ZYNQ7ZYNQ7Processing SystemSystem IP,IP, andand thenthen presspress ard.Processing5. In the searchzynqtheon thethe ogFigure 7:7: TheThe IPIP IntegratorIntegrator IPIP esthedesignppropriately.BecauseIPyouselected cthetheZC702 boardboardwhenayouyoucreated thetheproject,project, thethe VivadoVivado IPIPBecauseyouselectedZC702whencreatedintegrator configures the designappropriately.integrator configures the design 13.2)June19,2013UG940 (v 2013.2) June 19, 2013www.xilinx.comwww.xilinx.com1414

Step 2:2: CreateCreate anan IPIP IntegratorIntegrator age:Stepcreate bd cellip -vlnvInConsole,themessage:In thethe TclTclConsole, youyou seesee-typethe followingfollowingmessage:xilinx.com:ip:processing system7:5.2 processing system7 1create bd cellcreate bd cell -type-type ipip -vlnv-vlnv xilinx.com:ip:processing system7:5.2xilinx.com:ip:processing system7:5.2processing system7 1processing system7 1INFO: [PS7-6] Configuring Board Preset zed. Please wait .INFO:INFO: [PS7-6][PS7-6] ConfiguringConfiguring BoardBoard PresetPreset zc702.zc702. PleasePlease waitwait rmedintheIPTherecommandactionsintegratorThere isis aa correspondingcorresponding Tclcommand forfor allactions performedperformed inin thethe IPintegrator sshownSeediagram.Thosecommandsarenotshown inin thisthisdocument.See thethe TclTcl ConsoleConsole ation on those commands.6. ckRun6. InIn thetheIPInintegratordiagram header,clickRun atingthattheFIXED IOandTheBlockAutomationdialog boxstating thatThe RunRunDDRBlockAutomationbox fopens,opens,that thethe FIXED IOFIXED IO andand DDRDDR rthestatingZynqcore.willfortheZynqcore.will bebe createdcreatedfortheZynqcore.ClickOK.7.7. AL7EmbeddedEmbedded ProcessorProcessor HardwareHardware DesignDesignUG940(v2013.2)JuneUG940 (v 2013.2) June 19,19, 20132013www.xilinx.comwww.xilinx.com1515

Step 2: Create an IP Integrator r,theIPintegratordiagramshouldlookasfollows:After running block automation on the Zynq processor, the IP integrator diagram shouldlook as lockAutomation8. dothis,right- ‐10: Zynq Processing System after Running Block electAddIP.Nowyoucan addfield,peripheralsthe tprocessinglogic(PL).To doIP,this,right-clickthe IPEnterto9.8. ntegrator diagram, and select Add IP.addtheAXIGPIOIPtothedesign.9.In the search field, type gpi to find the AXI GPIO IP, and then press Enter to add the AXIGPIO IP totheadesign.10. Repeatthection,typingaxi findbramandtoaddlockemoryenerator.10.andRepeatthe action,typingfindBandaddMAXIBRAM GController,andtyping blockto find and add Block Memory elativepositionsoftheThe Block Design window matches FIGURE 11. The relative positions of the IP will ingIP IPFigurelockDesignafterafterInstantiatingEmbedded Processor Hardware DesignUG940 (v 2013.2) June 19, 20138VIVADOTUTORIALwww.xilinx.com16

CustomizeInstantiatedIP1. Double- ‐clicktheBlockMemoryGeneratorIP,orright- :CustomizeBlockOptionTheRe- ‐customizeIPdialogboxopens.2.2. OntheBasictabofthedialogbox,set: ModetoBRAMController ORIAL9

3. onnecttheAXIGPIOandAXIBRAMControllertotheZynq- ‐7000PS.1. ClickRunConnectionAutomationandthenselect/axi gpio 1/s RIAL

interfaceoftheGPIOandtheZynq- ‐7000PS.2. SelectRunConnectionAutomationagain,andthe/axi gpio 1/gpioshowninFIGURE17.Figure17:axi cludesoptionstohookuptotheGPIOport.4.3. Selectleds nsVIVADOTUTORIAL11

4. nConstraints(XDC).5. iningoption/axi bram ctrl 1/S AXI(FIGURE19).Figure19:axi bram ProcessorSystem6. necessary.12VIVADOTUTORIAL

7. nFIGURE21.Figure21:axi bram ctrlto64kRange8. SaveyourdesignbypressingCtrl- ‐S,orselectFile SaveBlockDesign.9. ted.10. Fromthetoolbar,runDesign- ‐Rules- URE22).Alternatively,youcandothesamefromthemenuby: SelectingTools ValidateDesignfromthemenu. Right- dateDesignMessage11. ClickOK.VIVADOTUTORIAL13

lesforthedesign.1. IntheSourcewindow,right- ‐clickthetop- file.4: Generate HDLDesign FilesStep 4: Generate HDL Design FilesFigure24:GenerateOutputProductsOptionFigure 29: Generate Output Products OptionFigure 29: Generate Output Products Option2. TheManageOutputProductsdialogboxopens.ClickOK.2. The Manage Output Products dialog box opens. Click OK.2. The Manage Output Products dialog box opens. Click tOutput ProductsProducts Dialog3. IntheSourceswindow,selectthetop- ‐levelsubsystemsource,andselect3. 3.In dandselectselectCreateCreateHDLIn ateHSourcesDLWrappertothecreateanexampletop- ‐levelHDLfile(FIGURE25).Wrapperto tocreateananexampleIGURE 31).31).Wrappercreateexampletoptoplevellevel HDLHDL file (FIGURE4. Click OK when the Create HDL Wrapper dialog box opens.Click OK when the Create HDL Wrapper dialog box opens.4. p5: Assign Signals to DebugEmbedded Processor Hardware DesignUG940 (vProcessor2013.2) June19, 2013DesignEmbeddedHardwareUG940 (v 2013.2) June 19, 2013www.xilinx.comFigure25:CreateHDLWrapperFigure 31: Create HDL Wrapper14VIVADOTUTORIALStep 5: Assign25www.xilinx.comSignals to DebugNow assign the signals to debug in the hardware.25

Figure 39: Save Constraints OptionStep 7: Implement Design and Generate 1. In FlowNavigator,click Generateimplementdesign anda BIT1. file.Note: Ifthe system requests to re-synthesize the design before implementing, click No.Note:Ifthesystemrequeststore- ‐synthesizethedesignbeforeimplementing,The previous step of saving the constraints caused the flow to mark intscausedtheflowtomarkout-of-date.synthesisout- ‐of- ‐date.Ordinarily,youmightwanttore- ,yoummightwantto re-synthesizethe 26).constraints, but for this tutorial, it is safe to ignore this condition (F IGURE streamYoumightseeadialogbox enu,selectExportHardwareforSDK(FIGUREFrom the main Vivado File menu, select Export Hardware for SDK (F IGURE 48).31).Figure 48: Export Hardware for SDKFigure 48: Export Hardware for SDKThe Export Hardware for SDK dialogboxopens.Figure 48:ExportHardware for SDKFigure31:boxExportHardwareforSDKThe Export Hardware for SDKdialogopens.If you want to go on to Lab 2 then ensure that Export Hardware, Include Bitstream, andIfTheyouExportwant Hardwareto go on tothen ensurethat Export Hardware, Include Bitstream, andforLabSDK2 dialogbox atExportLaunch TheSDKchecked(F IGURE49).Otherwise,youocancanleavethe tLaunchSDK optionLaunchSDKare checked(F IGURE49).Otherwise, youleavethe LaunchSDK optionIf you want toIncludego on to Lab2 then ensurethatExport Hardware,IncludeBitstream,and REunchecked.unchecked.Launch SDK are checked (F IGURE 49). Otherwise, you can leave the Launch SDK optionunchecked.Figure 49: Export Hardware for SDKFigure 49: Export Hardware for SDKConclusionConclusionFigure49: Export Hardware for SDKFigure32:ExportHardwareforSDKIn this lab you have:In this lab you have:ConclusionEmbedded Processor Hardware DesignIn thisUG940(v 2013.2)JuneHardware19, 2013 DesignEmbeddedProcessorlab UG940you have:(v 2013.2) June 19, 34

Chapter 3Part2:BuildZynq- HelloWorld”totheserialport.Lab 2: Using SDK and the Vivado plication1. .YoucanalsostartSDKfromtheWindowsStartmenucan run this lab after Lab 1. Make sure that you followed all the steps in Lab 1 beforebyYouclickingonStart AllPrograms XilinxDesignTools Vivado2013.2proceeding. SDK toensurethatyouinthecorrectworkspace.Step 1: Start SDK and Create a Software Application1. cIfanyoudareas a continuationof Labthen SDKhave launchedin a2. orkspace OtherinSDK.Inseparate window (if you checked the Launch SDK option while exporting hardware). You field,pointtothestart SDK from the Windows Start menu by clicking on Start All Programs XilinxSDK .Design Tools Vivado2013.2y SDK XilinxSDK 2013.2.Usually,islSDKocatedatyou need to ensure that you in the correct workspace.Whenthisstartingin this manner.\project name\project name.sdk\SDK\SDK Export.2. You can do that by clicking on File Switch Workspace Other in SDK. In the WorkspaceLauncher dialog box in the Workspace field, point to the SDK Export folder where you hadyour hardware from lab 1. Usually, this is located roject name\project name.sdk\SDK\SDK Export.Now you can create a peripheral test application.3. SelectFile New ApplicationProject(FIGURE33).3. Select File New Application Project (F IGURE 50).Figure33:File- ‐ New- ‐ ApplicationProjectFigure 50: File New Application ProjectNewProjectdialogboxopensEmbedded Processor Hardware DesignUG940 (v 2013.2) June 19, 201318VIVADOTUTORIALwww.xilinx.com36

Step 1: Start SDK and Create a Software ApplicationThe New Project dialog box opens.4. ProjectIntheNameProjectNamefield,typeZync Design,andclickNext(FIGURE34).51).4. In thefield,typeZynq Design,and click Next(F IGUREFigure34:SDKApplicationProjectFigure 51: SDK Application ProjectEmbedded Processor Hardware DesignUG940 (v 2013.2) June 19, 2013www.xilinx.com37VIVADOTUTORIAL19

Step 1: Start SDK and Create a Software 5. FromAvailableselect Peripheral(F IGUREand ing,finishcompiling,ouwillseethefollowingWhen theprogramyou seeythefollowing(F IGURE53). nEmbeddedProcessorTHardware(v 2013.2) June 19, 2013UG940Figure 53: SDK Messagewww.xilinx.com38

theZedBoard.1. URE37).Figure37:ConfigureJTAGSettings2. eJTAGSettingsVIVADOTUTORIAL21

3. inxTools stheProgramFPGAdialogbox.4. 5. Selectandright- ‐clicktheZynq Designapplication.6. VADOTUTORIAL

Step 2: Run the Software eFigure457:7. In the Debug Configurations dialog box, right-click Xilinx C/C Application (GDB) and7. IntheNew.DebugConfigurationsdialogbox,right- ‐clickXilinxC/C Applicationselect(GDB)andselectNew.Embedded Processor Hardware DesignUG940 (v 2013.2) June 19, 2013www.xilinx.com42VIVADOTUTORIAL23

Figure41:DebugConfigurationDialogBox8. e42:RunDebugConfigurations9. OTUTORIAL

Figure 60: Confirm Perspective Switch Dialog Box10. gtheSettings10. Set the terminal by selecting the Terminal 1 tab and clicking the Settings buttonbutton(FIGURE44).(F IGURE 61).Figure 61: Settings ButtonFigure44:SettingsButtonStep 2: Run the Software Application11.UseUse thesettingsfor the fZC702board(F IGURE 62).Click heZedBoard(FIGUREStep 2: Run the Software ApplicationEmbedded Processor Hardware DesignUG940 (v 2013.2) June 19, pressUSB- ‐to- ‐Serial.Figure45:TerminalSettingsFigure 62: Terminal Settings for ZC702 BoardFigure 62: Terminal Settings for ZC702 Board12. Verify the Terminal connection by checking the status at the top of the usatthetopofthetab12. Verifythe Terminalconnection by checking the status at the top of the tab63).(F IGURE(FIGUREIGURE 63). 46).(FFigure 63: Terminal Connection VerificationFigure 63: Terminal Connection nEmbedded Processor Hardware DesignUG940 (v 2013.2) June 19, 2013Embedded Processor Hardware DesignUG940 (v 2013.2) June 19, 45

13. rocessorCoretoDebug14. Ifitisnotalreadyopen,select nline43.1. SelectNavigate AL

2. IntheGoToLinedialogbox,type43.3. t.1. ClicktheResumebuttonorpressF82. ClicktheStepOverbuttonorpressF63. utVIVADOTUTORIAL27

Step 2: Create an IP Integrator Design Embedded Processor Hardware Design www.xilinx.com 13 UG940 (v 2013.2) June 19, 2013 Step 2: Create an IP Integrator Design 1. In the Flow Navigator, select Create Block Design. 3:Create Block Design from Flow Navigator 2. In the Create Block Design

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