Supertex Inc. PS10 Sequencing Controller
Supertex inc.PS10Quad PowerSequencing ControllerFeaturesGeneral Description Sequencing of four supplies, ICs, or subsystems Independently programmable delays between opendrain PWRGD flags (5.0 to 200ms) 10 to 90V operation Tracking in combination with Schottky diodes Input supervisors including: UV/OV lock out/enable Power-on-Reset (POR) Low power consumption, 0.4mA supply current Available in a space saving 14-Lead SOIC packageMany of today’s high performance FPGA’s, microprocessors,DSP and industrial/embedded subsystems require sequencingof the input power. Historically this has been accomplishedby: i) discretely using comparators, references & RC circuits;ii) using expensive programmable controllers; or iii) with lowvoltage sequencers requiring resistor drop downs and severalhigh voltage optocoupler or level shift components.The PS10 saves board space, improves accuracy, eliminatesoptocouplers or level shifts and reduces overall componentcount by combining four timers, programmable input UV/OVsupervisors, a programmable POR, and four 90V open drainoutputs. A high reliability, high voltage, junction isolated processallows the PS10 to be connected directly across the high voltageinput rails.Applications Power supply sequencing -48V telecom and networking distributed systems -24V cellular and fixed wireless systems -24V PBX systems 48V storage systems FPGA, microprocessor tracking Industrial/embedded system timing/sequencing High voltage MEMs driver’s supply sequencing High voltage display driver’s supply sequencingThe power-on-reset interval (POR) may be programmed by acapacitor on CRAMP. To sequence additional systems, multiplePS10s may be daisy-chained together. If at any time the inputsupply falls outside the UV/OV detector range, the PWRGDoutputs will immediately become IN-ACTIVE.The PS10 is available in a space saving 14-Lead SOIC package.Typical Application CircuitGND or D-BOVVEETBTC11RTB-48V or C/DCConverter/ENDC/DCConverter 12VCOM 5VCOM 3.3VCOM 2.5VCOMNotes:1. Under Voltage Shutdown (UV) set to 37V.2. Over Voltage Shutdown (OV) to 57.8V.Supertex inc.www.supertex.com
PS10Pin ConfigurationOrdering InformationPart NumberPackage OptionPackingPS10NG-G14-Lead SOIC53/TubePS10NG-G-G M90514-Lead SOIC2500/Reel141-G indicates package is RoHS compliant (‘Green’)Absolute Maximum RatingsParameterValueVEE referenced to VIN pin 0.3V to -100VVPWRGD referenced to VEE voltage-0.3V to 100VVUV and VOV referenced to VEE voltage(top view)-0.3V to 12VOperating ambient temperature-40 C to 85 COperating junction temperature-40 C to 125 CStorage temperature range14-Lead SOICProduct MarkingTop Marking-65 to 150 CPower dissipation @ 25 CPS10NG750mWOYWWAbsolute Maximum Ratings are those values beyond which damage to the device mayoccur. Functional operation under these conditions is not implied. Continuous operationof the device at the absolute rating level may affect device reliability. All voltages arereferenced to device ground.LLLLLLLLBottom MarkingCCCCCCCCC AAA*May be part of top markingPWRGD LogicConditionPackage may or may not include the following marks: Si orPWRGD-A/B/C/DInactive (not ready)0VEEActive (ready)1Hi ZElectrical Characteristics (-10V VINSymY Last Digit of Year SealedWW Week SealedL Lot NumberC Country of OriginA Assembler ID* “Green” Packaging14-Lead SOICTypical Thermal ResistancePackageθja14-Lead SOIC75OC/W* -90V, TA 25 C unless otherwise specified)ParameterMinTypMaxUnitsConditionsSupply (Referenced to VIN pin)VEESupply voltage--90--10V---IEESupply current--400450µAVEE -48VOV and UV Control (Referenced to VEE pin)VUVHUV high threshold#1.161.221.28VLow to high transitionVUVLUV low threshold#1.061.121.18VHigh to low transitionVUVHYUV hysteresis#-100-mV---UV input current---1.0nAVUV VEE 1.9VVOVHOV high threshold#1.161.221.28VLow to high transitionVOVLOV low threshold#1.061.121.18VVOVHYOV hysteresis#-100-mV---OV input current---1.0nAVUV VEE 1.9VIUVIOVHigh to low transition# Specifications apply over 0OC TA 70OCDoc.#DSFP-PS10C0806132Supertex inc.www.supertex.com
PS10Electrical Characteristics (cont.) (-10V VINSym -90V, TA 25 C unless otherwise specified)ParameterMinTypMaxUnitsConditionsPower Good Timing (Test Conditions: CRAMP 10nF, VUV VEE 1.9V, VOV VEE 0.5V)IRAMPRamp pin output current--10-µA---tPWRGD-ATime from UV high to PWRGD-A--8.8-msVEE -48V,CRAMP 10nF, seetypical application circuittPWRGD-BMaximum time from PWRGD-A to PWRGD-B-150200*250msRTB 120kΩtPWRGD-BMinimum time from PWRGD-A to PWRGD-B-3.05.0*8.0msRTD 3.0kΩtPWRGD-CMaximum time from PWRGD-B to PWRGD-C-150200*250msRTB 120kΩtPWRGD-CMinimum time from PWRGD-B to PWRGD-C-3.05.0*8.0msRTD 3.0kΩtPWRGD-DMaximum time from PWRGD-C to PWRGD-D-150200*250msRTB 120kΩtPWRGD-DMinimum time from PWRGD-C to PWRGD-D-3.05.0*8.0msRTD 3.0kΩ* Variations will track. For example if tPWRGD-A is 250ms, then so will be tPWRGD-B/C/D. Contact factory for tighter tolerance version.Power Good Outputs (Test Conditions: VUV VEE 1.9V, VOV VEE 0.5V)VPWRGD-X(hi)Power good pin breakdown voltage-90--VVPWRGD-X(lo)Power good pin output low voltage--0.40.5VIPWRGD-X(lk)Maximum leakage current-- 1.010µAPWRGD-X HI ZIPWRGD 1.0mA,PWRGD-X LOWVPWRGD 90V,PWRGD-X HI ZFunctional Block DiagramVINTBand GapReferenceUVVINRegulator &POR LogicVBGPWRGD-AUVLO-OV PWRGD-BVEEPWRGD-CVINTProgrammableTimer- TDSupertex inc.www.supertex.com
PS10Functional DescriptionThe PS10 is designed to sequence up to 4 power supplymodules, ICs or subsystems when the backplane voltageis within the programmed under voltage and over voltagelimits. The power good open drain outputs are sequentiallyenabled starting from PWRGD-A to PWRGD-D. The timedelay between power goods is programmable up to 200mssimply by changing the value(s) of RTB, RTC, and RTD. Theinitial time between satisfaction of the UV/OV supervisors &PWRGD-A can be programmed with CRAMP.The undervoltage and overvoltage shut down thresholdscan be programmed by means of the three resistor dividerformed by R1, R2 and R3. Since the input currents on theUV and OV pins are negligible the resistor values may becalculated as follows:Description of OperationWhere (VEEUV(off)) and (VEEOV(off)) relative to VEE are under andover voltage shut down threshold points.UVOFF VUVL 1.12 (VEEUV(off)) x (R2 R3)/(R1 R2 R3)OVOFF VOVL 1.22 (VEEOV(off)) x R3/(R1 R2 R3)During the initial power application, the Power Good pinsare held low (rising with VIN). Once the internal under voltagelock out has been satisfied, the circuit checks the input supply under voltage (UV) and over voltage (OV) sense circuitsto ensure that the input voltage is within programmed limits.These limits are determined by the selected values for R1,R2, and R3, which form a voltage divider.If we select a divider current of 100µA at a nominal operating input voltage of 50V, then:R1 R2 R3 50V/100µA 500kΩFrom the second equation, for an OV shut down threshold of65V, the value of R3 may be calculated.At the same time, a 10µA current source is enabled, chargingthe external capacitor connected to the ramp pin. The risetime of the RAMP pin is determined by the value of the capacitor (10µA/CRAMP). When the ramp voltage reaches 8.8V,the PWRGD-A pin will change into an active state. PWRGDB will change into an active state after a programmed timedelay from PWRGD-A inactive to active transition. PWRGDC will change into an active state after a programmed timedelay from PWRGD-B inactive to active transition. PWRGDD will change into an active state after a programmed timedelay from PWRGD-C inactive to active transition.OVOFF 1.22 (65xR3)/500kΩR3 (1.22x 500kΩ)/65 9.38kΩThe closest 1% value is 9.31kΩ.From the first equation, for a UV shut down threshold of 35V,the value of R2 can be calculated.UVOFF 1.12 35 x (R2 R3)/ 500kΩThe controller continuously monitors the UV and OV pins aslong as the internal UVLO and POR circuits are satis-fied.At any time during the start up cycle or thereafter, crossingthe UV low and OV high limits will cause an im-mediate discharge on Cramp and reset on the power good pins. Whenthe input voltage returns to a value within the programmedUV and OV limits, a new start up sequence will initiate immediately.R2 ((1.12 x 500kΩ)/35) – 9.76kΩ 6.69kΩ6.65kΩ is a standard 1% valueThen:R1 500kΩ – R2 – R3 484.04kΩ.487kΩ, is a standard 1% value.Programming the Under and Over VoltageLimitsFrom the calculated resistor values the OV and UV start upthreshold voltages can be calculated as follows:The UV and OV pins are connected to comparators withnominal 1.17V thresholds and 100mV of hysteresis (1.17V 50mV). They are used to detect under voltage and overvoltage conditions at the input to the circuit. Whenever theOV pin rises above its high threshold (1.22V) or the UV pinfalls below its low threshold (1.12V), the PWRGD outputsimmediately deactivate.UVON VUVH 1.22 (VEEUV(on)) x (R2 R3)/(R1 R2 R3)OVON VOVL 1.12 (VEEOV(on)) x R3/(R1 R2 R3)Where (VEEUV(on)) and (VEEOV(on)) are under and over voltagestart up threshold points relative to VEE.Calculations can be based on either the desired input voltage operating limits or the input voltage shutdown limits. Inthe following equations the shutdown limits are assumed.Doc.#DSFP-PS10C0806134Supertex inc.www.supertex.com
PS10PWRGD Flags Delay ProgrammingThen:When the ramp voltage hits VINT - 1.17V, PWRGD-A becomes active indicating that the input supply voltage is withinthe programmed limits. PWRGD-B goes active after a programmed time delay after PWRGD-A went active. PWRGDC goes active after a programmed time delay after PWRGDB went active. PWRGD-D goes active after a programmedtime delay after PWRGD-C went active.(VEEUV(on)) 1.22 x (R1 R2 R3)/(R2 R3)(VEEUV(on)) 1.22 x (487k 6.65k 9.31k)/(6.65k 9.31k) 38.45VAnd:The resistors connected from TB, TC, and TD to VEE pindetermines the delay times between the PWRGD flags.(VEEOV(on)) 1.12 x (R1 R2 R3)/R3(VEEOV(on)) 1.12 x (487kΩ 6.65kΩ 9.31kΩ)/9.31kΩThe value of the resistors determines the capacitor chargingand discharging current of a triangular wave oscillator. Theoscillator output is fed into an 8-bit counter to generate thedesired time delay. 60.51VTherefore, the circuit will start when the input supply voltageis in the range of 38.45V to 60.51V.The respective time delay is defined by the following equation:Undervoltage/Overvoltage ProtectiontTX (255 x 2 x COSC x VPP)/ICDGNDandUVOFFUVONICD VBG / (4 x RTX)VINWhere:OVONOVOFFPWRGDSETtTX Time delay between respective PWRGD flagsCOSC 120pF (internal oscillator capacitor)VPP 8.2V (peak-to-peak voltage swing of oscillator)ICD Charge and discharge current of oscillatorVBG 1.17V (internal band gap reference)RTX Programming resistor at TB, TC, or TDRESETtPWRGD-A is the time delay from VEEUV(on) to PWRGD-A goingactive. It can be approximated by:Combining the two equations and solving for RTX yields:RTX (VBG x tTX) / (2040 x COSC x VPP)tPWRGD-A CRAMP x (VINT-1.17)/IRAMP 0.585 x 106 x tTXwhere:For a time delay of 200msCRAMP capacitor connected from RAMP pin to VEE pinVINT internal regulated power supply voltage (10V typ.)IRAMP 10µA charge currentRTX 0.585 x 106 x 0.2 117kΩFor a time delay of 5msRTX 0.585 x 106 x 0.005 2.925kΩDoc.#DSFP-PS10C0806135Supertex inc.www.supertex.com
PS10PWRGD Output ConfigurationThe PS10 open drain power good outputs can be connected directly to the Enable pins of the DC/DC converter. Theinternal pull-up and clamp of the DC/DC converter sets thelogic High Enable/Disable voltage.GND487kΩVINUVPWRGD-CCOMTBRTB-48V 81kΩVEEV PWRGD-DTCRTDRTCV-RAMPTD10nFNotes:1. Under Voltage Shutdown (UV) set to 37V.2. Over Voltage Shutdown (OV) to 57.8V.3. Other power good outputs will have the same configurationas PWGRGD-A for Active High Enabled Converters.Opto-isolated EnableSome applications require opto-isolator interface to the Enable pin of the DC/DC converter.GND487KΩ49.9kΩVINV NPWRGD-ADC/DCConverter TCRTCTDRTDRAMP10nFNotes:1. Under Voltage Shutdown (UV) set to 37V.2. Over Voltage Shutdown (OV) to 57.8V.3. Other power good outputs will have the same configurationas PWGRGD-A for Active High Enabled Converters.6Supertex inc.www.supertex.com
PS10Increasing the Under and Over VoltageHysteresisIf the internal UV hysteresis is insufficient for a particularsystem application, then it may be increased by using separate resis-tor dividers for UV and OV and providing a resistorfeedback from UV pin to the PWRGD pin.GND487kΩ499kΩVINPWRGD-DUVPWRGD-CR UVHYSPS10OVVEE16.5kΩV PWRGD-BPWRGD-ADC/DCConverter :1. Other power good outputs will have the same configuration as:PWGRGD-A for Active High Enabled Converters.2. Over voltage shut down set to 63.6VRUVHYS can be calculated based on higher UV On voltage (say 42V):RUVHYS (VUVON - VDIODE - VPWRGDLOW )/((VIN - VUVON )/487kΩ - VUVON /16.5kΩ) (1.22-0.65-0.4)/((42-1.22)/487kΩ - 1.22/16.5kΩ) 17.35kΩDoc.#DSFP-PS10C0806137Supertex inc.www.supertex.com
PS10Pin DescriptionPinFunction1PWRGD-DDescriptionThis open drain Power Good Output Pin is held inactive on initial power applicationand goes active a programmed time delay after PWRGD-C goes active.To function asan indicator, apullup resistormust beconnected fromthis pin to avoltage rail nomore than 90Vfrom VEE.2PWRGD-CThis open drain Power Good Output Pin is held inactive on initial power applicationand goes active a programmed time delay after PWRGD-B goes active.3PWRGD-BThis open drain Power Good Output Pin is held inactive on initial power applicationand goes active a programmed time delay after PWRGD-A goes active.4PWRGD-AThis open drain Power Good Output Pin is held inactive on initial power applicationand goes active one POR delay after the UV pin goes above its High threshold(provided VIN stays within the UV/OV window during this period).5OVThis Over Voltage (OV) sense pin, when raised above its high threshold will immediately cause thePower Good Outputs to be pulled low. These outputs will remain low until the voltage on this pin fallsbelow the low threshold limit, initiating a new start-up cycle.6UVThis Under Voltage (UV) sense pin, when lowered below its low threshold will immediately cause thePower Good Outputs to be pulled low. These outputs will remain low until the voltage on this pin risesabove the low threshold limit, initiating a new start-up cycle.7VEE8NC9NC10RAMPThis pin provides a current output so that a timing ramp is generated when a capacitor is connected.This timing Ramp is used to program POR and the time from satisfaction of the UV/OV supervisorsto PWRGD-A.11TBThe resistor connected from this pin to VEE pin sets the time delay from PWRGD-A going active toPWRGD-B going active.12TCThe resistor connected from this pin to VEE pin sets the time delay from PWRGD-B going active toPWRGD-C going active.13TDThe resistor connected from this pin to VEE pin sets the time delay from PWRGD-C going active toPWRGD-D going active.14VINThis pin is the positive terminal of the power supply input to the circuit and can withstand 90V withrespect to VEE.Doc.#DSFP-PS10C080613This pin is the negative terminal of the power supply input to the circuit.No Connect. This pin can be grounded or left floating.8Supertex inc.www.supertex.com
PS1014-Lead SOIC (Narrow Body) Package Outline (NG)8.65x3.90mm body, 1.75mm height (max), 1.27mm pitchDθ114Note 1(Index AreaD/2 x E1/2)E1 EGaugePlaneL2e1L1bTop ViewLSeatingPlaneθView BView BAhhAA2SeatingPlaneA1Side ViewView A-AANote:1. This chamfer feature is optional. If it is not present, then a Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be:a molded mark/identifier; an embedded metal marker; or a printed indicator.SymbolAMIN 1.35*DimensionNOM(mm)MAX 1.75A1A2b0.101.250.31---0.251.65*0.51DEE18.55* 5.80* 3.80*8.656.003.908.75* 6.20* Cθθ10O5O--8O15OJEDEC Registration MS-012, Variation AB, Issue E, Sept. 2005.* This dimension is not specified in the JEDEC drawing.Drawings are not to scale.Supertex Doc. #: DSPD-14SOICNG, Version F041309.(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outlineinformation go to http://www.supertex.com/packaging.html.)Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receivesan adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liabilityto the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry andspecifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)Supertex inc. 2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited.Doc.#DSFP-PS10C08061391235 Bordeaux Drive, Sunnyvale, CA 94089Tel: 408-222-8888www.supertex.com
L Lot Number C Country of Origin A Assembler ID* “Green” Packaging *May be part of top marking Top Marking Bottom Marking PS10NG YWW LLLLLLLL CCCCCCCCC AAA 14-Lead SOIC Electrical Characteristics (-10V V IN -90V, T A 25 C unless otherwise specified) 1 14 14-Lead SOIC .
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